87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* PNX8550 global definitions
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*
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* Author: source@mvista.com
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef __PNX8550_GLB_H
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#define __PNX8550_GLB_H
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#define PNX8550_GLB1_BASE 0xBBE63000
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#define PNX8550_GLB2_BASE 0xBBE4d000
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#define PNX8550_RESET_BASE 0xBBE60000
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/* PCI Inta Output Enable Registers */
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#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
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/* Bit 1:Enable DAC Powerdown
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0:DACs are enabled and are working normally
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1:DACs are powerdown
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*/
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#define PNX8550_GLB_DAC_PD 0x2
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/* Bit 0:Enable of PCI inta output
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0 = Disable PCI inta output
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1 = Enable PCI inta output
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*/
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#define PNX8550_GLB_ENABLE_INTA_O 0x1
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/* PCI Direct Mappings */
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#define PNX8550_PCIMEM 0x12000000
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#define PNX8550_PCIMEM_SIZE 0x08000000
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#define PNX8550_PCIIO 0x1c000000
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#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
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#define PNX8550_PORT_BASE KSEG1
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// GPIO def
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#define PNX8550_GPIO_BASE 0x1Be00000
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#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
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#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
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#define PNX8550_GPIO_MC_31_BIT 30
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#define PNX8550_GPIO_MC_30_BIT 28
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#define PNX8550_GPIO_MC_29_BIT 26
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#define PNX8550_GPIO_MC_28_BIT 24
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#define PNX8550_GPIO_MC_27_BIT 22
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#define PNX8550_GPIO_MC_26_BIT 20
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#define PNX8550_GPIO_MC_25_BIT 18
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#define PNX8550_GPIO_MC_24_BIT 16
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#define PNX8550_GPIO_MC_23_BIT 14
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#define PNX8550_GPIO_MC_22_BIT 12
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#define PNX8550_GPIO_MC_21_BIT 10
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#define PNX8550_GPIO_MC_20_BIT 8
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#define PNX8550_GPIO_MC_19_BIT 6
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#define PNX8550_GPIO_MC_18_BIT 4
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#define PNX8550_GPIO_MC_17_BIT 2
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#define PNX8550_GPIO_MC_16_BIT 0
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#define PNX8550_GPIO_MODE_PRIMOP 0x1
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#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
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#define PNX8550_GPIO_MODE_OPENDR 0x3
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// RESET module
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#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
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#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
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#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
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#define PNX8550_RST_REL_MIPS_RST_N 0x8
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#define PNX8550_RST_DO_SW_RST 0x4
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#define PNX8550_RST_REL_SYS_RST_OUT 0x2
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#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
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#endif
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