2008-04-27 07:55:59 -04:00
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/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2005-2008 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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/* Common definitions for all Efx net driver code */
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#ifndef EFX_NET_DRIVER_H
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#define EFX_NET_DRIVER_H
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#include <linux/version.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/timer.h>
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#include <linux/mii.h>
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#include <linux/list.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/highmem.h>
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#include <linux/workqueue.h>
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#include <linux/inet_lro.h>
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#include "enum.h"
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#include "bitfield.h"
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#include "i2c-direct.h"
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#define EFX_MAX_LRO_DESCRIPTORS 8
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#define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
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/**************************************************************************
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*
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* Build definitions
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*
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**************************************************************************/
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#ifndef EFX_DRIVER_NAME
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#define EFX_DRIVER_NAME "sfc"
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#endif
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#define EFX_DRIVER_VERSION "2.2.0136"
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#ifdef EFX_ENABLE_DEBUG
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#define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
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#define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
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#else
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#define EFX_BUG_ON_PARANOID(x) do {} while (0)
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#define EFX_WARN_ON_PARANOID(x) do {} while (0)
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#endif
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#define NET_DEV_REGISTERED(efx) \
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((efx)->net_dev->reg_state == NETREG_REGISTERED)
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/* Include net device name in log messages if it has been registered.
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* Use efx->name not efx->net_dev->name so that races with (un)registration
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* are harmless.
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*/
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#define NET_DEV_NAME(efx) (NET_DEV_REGISTERED(efx) ? (efx)->name : "")
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/* Un-rate-limited logging */
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#define EFX_ERR(efx, fmt, args...) \
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dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, NET_DEV_NAME(efx), ##args)
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#define EFX_INFO(efx, fmt, args...) \
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dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, NET_DEV_NAME(efx), ##args)
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#ifdef EFX_ENABLE_DEBUG
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#define EFX_LOG(efx, fmt, args...) \
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dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
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#else
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#define EFX_LOG(efx, fmt, args...) \
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dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
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#endif
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#define EFX_TRACE(efx, fmt, args...) do {} while (0)
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#define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
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/* Rate-limited logging */
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#define EFX_ERR_RL(efx, fmt, args...) \
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do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
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#define EFX_INFO_RL(efx, fmt, args...) \
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do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
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#define EFX_LOG_RL(efx, fmt, args...) \
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do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
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/* Kernel headers may redefine inline anyway */
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#ifndef inline
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#define inline inline __attribute__ ((always_inline))
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#endif
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/**************************************************************************
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*
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* Efx data structures
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*
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**************************************************************************/
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#define EFX_MAX_CHANNELS 32
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#define EFX_MAX_TX_QUEUES 1
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#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
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/**
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* struct efx_special_buffer - An Efx special buffer
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* @addr: CPU base address of the buffer
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* @dma_addr: DMA base address of the buffer
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* @len: Buffer length, in bytes
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* @index: Buffer index within controller;s buffer table
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* @entries: Number of buffer table entries
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*
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* Special buffers are used for the event queues and the TX and RX
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* descriptor queues for each channel. They are *not* used for the
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* actual transmit and receive buffers.
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*
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* Note that for Falcon, TX and RX descriptor queues live in host memory.
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* Allocation and freeing procedures must take this into account.
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*/
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struct efx_special_buffer {
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void *addr;
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dma_addr_t dma_addr;
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unsigned int len;
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int index;
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int entries;
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};
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/**
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* struct efx_tx_buffer - An Efx TX buffer
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* @skb: The associated socket buffer.
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* Set only on the final fragment of a packet; %NULL for all other
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* fragments. When this fragment completes, then we can free this
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* skb.
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2008-05-07 07:51:12 -04:00
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* @tsoh: The associated TSO header structure, or %NULL if this
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* buffer is not a TSO header.
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2008-04-27 07:55:59 -04:00
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* @dma_addr: DMA address of the fragment.
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* @len: Length of this fragment.
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* This field is zero when the queue slot is empty.
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* @continuation: True if this fragment is not the end of a packet.
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* @unmap_single: True if pci_unmap_single should be used.
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* @unmap_addr: DMA address to unmap
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* @unmap_len: Length of this fragment to unmap
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*/
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struct efx_tx_buffer {
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const struct sk_buff *skb;
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2008-05-07 07:51:12 -04:00
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struct efx_tso_header *tsoh;
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2008-04-27 07:55:59 -04:00
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dma_addr_t dma_addr;
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unsigned short len;
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unsigned char continuation;
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unsigned char unmap_single;
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dma_addr_t unmap_addr;
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unsigned short unmap_len;
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};
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/**
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* struct efx_tx_queue - An Efx TX queue
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*
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* This is a ring buffer of TX fragments.
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* Since the TX completion path always executes on the same
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* CPU and the xmit path can operate on different CPUs,
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* performance is increased by ensuring that the completion
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* path and the xmit path operate on different cache lines.
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* This is particularly important if the xmit path is always
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* executing on one CPU which is different from the completion
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* path. There is also a cache line for members which are
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* read but not written on the fast path.
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*
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* @efx: The associated Efx NIC
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* @queue: DMA queue number
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* @used: Queue is used by net driver
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* @channel: The associated channel
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* @buffer: The software buffer ring
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* @txd: The hardware descriptor ring
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* @read_count: Current read pointer.
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* This is the number of buffers that have been removed from both rings.
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* @stopped: Stopped flag.
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* Set if this TX queue is currently stopping its port.
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* @insert_count: Current insert pointer
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* This is the number of buffers that have been added to the
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* software ring.
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* @write_count: Current write pointer
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* This is the number of buffers that have been added to the
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* hardware ring.
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* @old_read_count: The value of read_count when last checked.
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* This is here for performance reasons. The xmit path will
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* only get the up-to-date value of read_count if this
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* variable indicates that the queue is full. This is to
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* avoid cache-line ping-pong between the xmit path and the
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* completion path.
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2008-05-07 07:51:12 -04:00
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* @tso_headers_free: A list of TSO headers allocated for this TX queue
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* that are not in use, and so available for new TSO sends. The list
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* is protected by the TX queue lock.
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* @tso_bursts: Number of times TSO xmit invoked by kernel
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* @tso_long_headers: Number of packets with headers too long for standard
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* blocks
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* @tso_packets: Number of packets via the TSO xmit path
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2008-04-27 07:55:59 -04:00
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*/
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struct efx_tx_queue {
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/* Members which don't change on the fast path */
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struct efx_nic *efx ____cacheline_aligned_in_smp;
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int queue;
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int used;
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struct efx_channel *channel;
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struct efx_nic *nic;
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struct efx_tx_buffer *buffer;
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struct efx_special_buffer txd;
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/* Members used mainly on the completion path */
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unsigned int read_count ____cacheline_aligned_in_smp;
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int stopped;
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/* Members used only on the xmit path */
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unsigned int insert_count ____cacheline_aligned_in_smp;
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unsigned int write_count;
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unsigned int old_read_count;
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2008-05-07 07:51:12 -04:00
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struct efx_tso_header *tso_headers_free;
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unsigned int tso_bursts;
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unsigned int tso_long_headers;
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unsigned int tso_packets;
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2008-04-27 07:55:59 -04:00
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};
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/**
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* struct efx_rx_buffer - An Efx RX data buffer
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* @dma_addr: DMA base address of the buffer
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* @skb: The associated socket buffer, if any.
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* If both this and page are %NULL, the buffer slot is currently free.
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* @page: The associated page buffer, if any.
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* If both this and skb are %NULL, the buffer slot is currently free.
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* @data: Pointer to ethernet header
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* @len: Buffer length, in bytes.
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* @unmap_addr: DMA address to unmap
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*/
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struct efx_rx_buffer {
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dma_addr_t dma_addr;
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struct sk_buff *skb;
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struct page *page;
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char *data;
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unsigned int len;
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dma_addr_t unmap_addr;
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};
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/**
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* struct efx_rx_queue - An Efx RX queue
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* @efx: The associated Efx NIC
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* @queue: DMA queue number
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* @used: Queue is used by net driver
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* @channel: The associated channel
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* @buffer: The software buffer ring
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* @rxd: The hardware descriptor ring
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* @added_count: Number of buffers added to the receive queue.
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* @notified_count: Number of buffers given to NIC (<= @added_count).
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* @removed_count: Number of buffers removed from the receive queue.
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* @add_lock: Receive queue descriptor add spin lock.
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* This lock must be held in order to add buffers to the RX
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* descriptor ring (rxd and buffer) and to update added_count (but
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* not removed_count).
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* @max_fill: RX descriptor maximum fill level (<= ring size)
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* @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
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* (<= @max_fill)
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* @fast_fill_limit: The level to which a fast fill will fill
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* (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
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* @min_fill: RX descriptor minimum non-zero fill level.
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* This records the minimum fill level observed when a ring
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* refill was triggered.
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* @min_overfill: RX descriptor minimum overflow fill level.
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* This records the minimum fill level at which RX queue
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* overflow was observed. It should never be set.
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* @alloc_page_count: RX allocation strategy counter.
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* @alloc_skb_count: RX allocation strategy counter.
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* @work: Descriptor push work thread
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* @buf_page: Page for next RX buffer.
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* We can use a single page for multiple RX buffers. This tracks
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* the remaining space in the allocation.
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* @buf_dma_addr: Page's DMA address.
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* @buf_data: Page's host address.
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*/
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struct efx_rx_queue {
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struct efx_nic *efx;
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int queue;
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int used;
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struct efx_channel *channel;
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struct efx_rx_buffer *buffer;
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struct efx_special_buffer rxd;
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int added_count;
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int notified_count;
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int removed_count;
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spinlock_t add_lock;
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unsigned int max_fill;
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unsigned int fast_fill_trigger;
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unsigned int fast_fill_limit;
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unsigned int min_fill;
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unsigned int min_overfill;
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unsigned int alloc_page_count;
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unsigned int alloc_skb_count;
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struct delayed_work work;
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unsigned int slow_fill_count;
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struct page *buf_page;
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dma_addr_t buf_dma_addr;
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char *buf_data;
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};
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/**
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* struct efx_buffer - An Efx general-purpose buffer
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* @addr: host base address of the buffer
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* @dma_addr: DMA base address of the buffer
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* @len: Buffer length, in bytes
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*
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* Falcon uses these buffers for its interrupt status registers and
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* MAC stats dumps.
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*/
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struct efx_buffer {
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void *addr;
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dma_addr_t dma_addr;
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unsigned int len;
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};
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/* Flags for channel->used_flags */
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#define EFX_USED_BY_RX 1
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#define EFX_USED_BY_TX 2
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#define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
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enum efx_rx_alloc_method {
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RX_ALLOC_METHOD_AUTO = 0,
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RX_ALLOC_METHOD_SKB = 1,
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RX_ALLOC_METHOD_PAGE = 2,
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};
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/**
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* struct efx_channel - An Efx channel
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*
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* A channel comprises an event queue, at least one TX queue, at least
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* one RX queue, and an associated tasklet for processing the event
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* queue.
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*
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* @efx: Associated Efx NIC
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* @evqnum: Event queue number
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* @channel: Channel instance number
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* @used_flags: Channel is used by net driver
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* @enabled: Channel enabled indicator
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* @irq: IRQ number (MSI and MSI-X only)
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* @has_interrupt: Channel has an interrupt
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* @irq_moderation: IRQ moderation value (in us)
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* @napi_dev: Net device used with NAPI
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* @napi_str: NAPI control structure
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* @reset_work: Scheduled reset work thread
|
|
|
|
* @work_pending: Is work pending via NAPI?
|
|
|
|
* @eventq: Event queue buffer
|
|
|
|
* @eventq_read_ptr: Event queue read pointer
|
|
|
|
* @last_eventq_read_ptr: Last event queue read pointer value.
|
|
|
|
* @eventq_magic: Event queue magic value for driver-generated test events
|
|
|
|
* @lro_mgr: LRO state
|
|
|
|
* @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
|
|
|
|
* and diagnostic counters
|
|
|
|
* @rx_alloc_push_pages: RX allocation method currently in use for pushing
|
|
|
|
* descriptors
|
|
|
|
* @rx_alloc_pop_pages: RX allocation method currently in use for popping
|
|
|
|
* descriptors
|
|
|
|
* @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
|
|
|
|
* @n_rx_ip_frag_err: Count of RX IP fragment errors
|
|
|
|
* @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
|
|
|
|
* @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
|
|
|
|
* @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
|
|
|
|
* @n_rx_overlength: Count of RX_OVERLENGTH errors
|
|
|
|
* @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
|
|
|
|
*/
|
|
|
|
struct efx_channel {
|
|
|
|
struct efx_nic *efx;
|
|
|
|
int evqnum;
|
|
|
|
int channel;
|
|
|
|
int used_flags;
|
|
|
|
int enabled;
|
|
|
|
int irq;
|
|
|
|
unsigned int has_interrupt;
|
|
|
|
unsigned int irq_moderation;
|
|
|
|
struct net_device *napi_dev;
|
|
|
|
struct napi_struct napi_str;
|
|
|
|
struct work_struct reset_work;
|
|
|
|
int work_pending;
|
|
|
|
struct efx_special_buffer eventq;
|
|
|
|
unsigned int eventq_read_ptr;
|
|
|
|
unsigned int last_eventq_read_ptr;
|
|
|
|
unsigned int eventq_magic;
|
|
|
|
|
|
|
|
struct net_lro_mgr lro_mgr;
|
|
|
|
int rx_alloc_level;
|
|
|
|
int rx_alloc_push_pages;
|
|
|
|
int rx_alloc_pop_pages;
|
|
|
|
|
|
|
|
unsigned n_rx_tobe_disc;
|
|
|
|
unsigned n_rx_ip_frag_err;
|
|
|
|
unsigned n_rx_ip_hdr_chksum_err;
|
|
|
|
unsigned n_rx_tcp_udp_chksum_err;
|
|
|
|
unsigned n_rx_frm_trunc;
|
|
|
|
unsigned n_rx_overlength;
|
|
|
|
unsigned n_skbuff_leaks;
|
|
|
|
|
|
|
|
/* Used to pipeline received packets in order to optimise memory
|
|
|
|
* access with prefetches.
|
|
|
|
*/
|
|
|
|
struct efx_rx_buffer *rx_pkt;
|
|
|
|
int rx_pkt_csummed;
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct efx_blinker - S/W LED blinking context
|
|
|
|
* @led_num: LED ID (board-specific meaning)
|
|
|
|
* @state: Current state - on or off
|
|
|
|
* @resubmit: Timer resubmission flag
|
|
|
|
* @timer: Control timer for blinking
|
|
|
|
*/
|
|
|
|
struct efx_blinker {
|
|
|
|
int led_num;
|
|
|
|
int state;
|
|
|
|
int resubmit;
|
|
|
|
struct timer_list timer;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct efx_board - board information
|
|
|
|
* @type: Board model type
|
|
|
|
* @major: Major rev. ('A', 'B' ...)
|
|
|
|
* @minor: Minor rev. (0, 1, ...)
|
|
|
|
* @init: Initialisation function
|
|
|
|
* @init_leds: Sets up board LEDs
|
|
|
|
* @set_fault_led: Turns the fault LED on or off
|
|
|
|
* @blink: Starts/stops blinking
|
|
|
|
* @blinker: used to blink LEDs in software
|
|
|
|
*/
|
|
|
|
struct efx_board {
|
|
|
|
int type;
|
|
|
|
int major;
|
|
|
|
int minor;
|
|
|
|
int (*init) (struct efx_nic *nic);
|
|
|
|
/* As the LEDs are typically attached to the PHY, LEDs
|
|
|
|
* have a separate init callback that happens later than
|
|
|
|
* board init. */
|
|
|
|
int (*init_leds)(struct efx_nic *efx);
|
|
|
|
void (*set_fault_led) (struct efx_nic *efx, int state);
|
|
|
|
void (*blink) (struct efx_nic *efx, int start);
|
|
|
|
struct efx_blinker blinker;
|
|
|
|
};
|
|
|
|
|
|
|
|
enum efx_int_mode {
|
|
|
|
/* Be careful if altering to correct macro below */
|
|
|
|
EFX_INT_MODE_MSIX = 0,
|
|
|
|
EFX_INT_MODE_MSI = 1,
|
|
|
|
EFX_INT_MODE_LEGACY = 2,
|
|
|
|
EFX_INT_MODE_MAX /* Insert any new items before this */
|
|
|
|
};
|
|
|
|
#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
|
|
|
|
|
|
|
|
enum phy_type {
|
|
|
|
PHY_TYPE_NONE = 0,
|
|
|
|
PHY_TYPE_CX4_RTMR = 1,
|
|
|
|
PHY_TYPE_1G_ALASKA = 2,
|
|
|
|
PHY_TYPE_10XPRESS = 3,
|
|
|
|
PHY_TYPE_XFP = 4,
|
|
|
|
PHY_TYPE_PM8358 = 6,
|
|
|
|
PHY_TYPE_MAX /* Insert any new items before this */
|
|
|
|
};
|
|
|
|
|
|
|
|
#define PHY_ADDR_INVALID 0xff
|
|
|
|
|
|
|
|
enum nic_state {
|
|
|
|
STATE_INIT = 0,
|
|
|
|
STATE_RUNNING = 1,
|
|
|
|
STATE_FINI = 2,
|
|
|
|
STATE_RESETTING = 3, /* rtnl_lock always held */
|
|
|
|
STATE_DISABLED = 4,
|
|
|
|
STATE_MAX,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Alignment of page-allocated RX buffers
|
|
|
|
*
|
|
|
|
* Controls the number of bytes inserted at the start of an RX buffer.
|
|
|
|
* This is the equivalent of NET_IP_ALIGN [which controls the alignment
|
|
|
|
* of the skb->head for hardware DMA].
|
|
|
|
*/
|
|
|
|
#if defined(__i386__) || defined(__x86_64__)
|
|
|
|
#define EFX_PAGE_IP_ALIGN 0
|
|
|
|
#else
|
|
|
|
#define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Alignment of the skb->head which wraps a page-allocated RX buffer
|
|
|
|
*
|
|
|
|
* The skb allocated to wrap an rx_buffer can have this alignment. Since
|
|
|
|
* the data is memcpy'd from the rx_buf, it does not need to be equal to
|
|
|
|
* EFX_PAGE_IP_ALIGN.
|
|
|
|
*/
|
|
|
|
#define EFX_PAGE_SKB_ALIGN 2
|
|
|
|
|
|
|
|
/* Forward declaration */
|
|
|
|
struct efx_nic;
|
|
|
|
|
|
|
|
/* Pseudo bit-mask flow control field */
|
|
|
|
enum efx_fc_type {
|
|
|
|
EFX_FC_RX = 1,
|
|
|
|
EFX_FC_TX = 2,
|
|
|
|
EFX_FC_AUTO = 4,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct efx_phy_operations - Efx PHY operations table
|
|
|
|
* @init: Initialise PHY
|
|
|
|
* @fini: Shut down PHY
|
|
|
|
* @reconfigure: Reconfigure PHY (e.g. for new link parameters)
|
|
|
|
* @clear_interrupt: Clear down interrupt
|
|
|
|
* @blink: Blink LEDs
|
|
|
|
* @check_hw: Check hardware
|
|
|
|
* @reset_xaui: Reset XAUI side of PHY for (software sequenced reset)
|
|
|
|
* @mmds: MMD presence mask
|
|
|
|
*/
|
|
|
|
struct efx_phy_operations {
|
|
|
|
int (*init) (struct efx_nic *efx);
|
|
|
|
void (*fini) (struct efx_nic *efx);
|
|
|
|
void (*reconfigure) (struct efx_nic *efx);
|
|
|
|
void (*clear_interrupt) (struct efx_nic *efx);
|
|
|
|
int (*check_hw) (struct efx_nic *efx);
|
|
|
|
void (*reset_xaui) (struct efx_nic *efx);
|
|
|
|
int mmds;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Efx extended statistics
|
|
|
|
*
|
|
|
|
* Not all statistics are provided by all supported MACs. The purpose
|
|
|
|
* is this structure is to contain the raw statistics provided by each
|
|
|
|
* MAC.
|
|
|
|
*/
|
|
|
|
struct efx_mac_stats {
|
|
|
|
u64 tx_bytes;
|
|
|
|
u64 tx_good_bytes;
|
|
|
|
u64 tx_bad_bytes;
|
|
|
|
unsigned long tx_packets;
|
|
|
|
unsigned long tx_bad;
|
|
|
|
unsigned long tx_pause;
|
|
|
|
unsigned long tx_control;
|
|
|
|
unsigned long tx_unicast;
|
|
|
|
unsigned long tx_multicast;
|
|
|
|
unsigned long tx_broadcast;
|
|
|
|
unsigned long tx_lt64;
|
|
|
|
unsigned long tx_64;
|
|
|
|
unsigned long tx_65_to_127;
|
|
|
|
unsigned long tx_128_to_255;
|
|
|
|
unsigned long tx_256_to_511;
|
|
|
|
unsigned long tx_512_to_1023;
|
|
|
|
unsigned long tx_1024_to_15xx;
|
|
|
|
unsigned long tx_15xx_to_jumbo;
|
|
|
|
unsigned long tx_gtjumbo;
|
|
|
|
unsigned long tx_collision;
|
|
|
|
unsigned long tx_single_collision;
|
|
|
|
unsigned long tx_multiple_collision;
|
|
|
|
unsigned long tx_excessive_collision;
|
|
|
|
unsigned long tx_deferred;
|
|
|
|
unsigned long tx_late_collision;
|
|
|
|
unsigned long tx_excessive_deferred;
|
|
|
|
unsigned long tx_non_tcpudp;
|
|
|
|
unsigned long tx_mac_src_error;
|
|
|
|
unsigned long tx_ip_src_error;
|
|
|
|
u64 rx_bytes;
|
|
|
|
u64 rx_good_bytes;
|
|
|
|
u64 rx_bad_bytes;
|
|
|
|
unsigned long rx_packets;
|
|
|
|
unsigned long rx_good;
|
|
|
|
unsigned long rx_bad;
|
|
|
|
unsigned long rx_pause;
|
|
|
|
unsigned long rx_control;
|
|
|
|
unsigned long rx_unicast;
|
|
|
|
unsigned long rx_multicast;
|
|
|
|
unsigned long rx_broadcast;
|
|
|
|
unsigned long rx_lt64;
|
|
|
|
unsigned long rx_64;
|
|
|
|
unsigned long rx_65_to_127;
|
|
|
|
unsigned long rx_128_to_255;
|
|
|
|
unsigned long rx_256_to_511;
|
|
|
|
unsigned long rx_512_to_1023;
|
|
|
|
unsigned long rx_1024_to_15xx;
|
|
|
|
unsigned long rx_15xx_to_jumbo;
|
|
|
|
unsigned long rx_gtjumbo;
|
|
|
|
unsigned long rx_bad_lt64;
|
|
|
|
unsigned long rx_bad_64_to_15xx;
|
|
|
|
unsigned long rx_bad_15xx_to_jumbo;
|
|
|
|
unsigned long rx_bad_gtjumbo;
|
|
|
|
unsigned long rx_overflow;
|
|
|
|
unsigned long rx_missed;
|
|
|
|
unsigned long rx_false_carrier;
|
|
|
|
unsigned long rx_symbol_error;
|
|
|
|
unsigned long rx_align_error;
|
|
|
|
unsigned long rx_length_error;
|
|
|
|
unsigned long rx_internal_error;
|
|
|
|
unsigned long rx_good_lt64;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Number of bits used in a multicast filter hash address */
|
|
|
|
#define EFX_MCAST_HASH_BITS 8
|
|
|
|
|
|
|
|
/* Number of (single-bit) entries in a multicast filter hash */
|
|
|
|
#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
|
|
|
|
|
|
|
|
/* An Efx multicast filter hash */
|
|
|
|
union efx_multicast_hash {
|
|
|
|
u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
|
|
|
|
efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct efx_nic - an Efx NIC
|
|
|
|
* @name: Device name (net device name or bus id before net device registered)
|
|
|
|
* @pci_dev: The PCI device
|
|
|
|
* @type: Controller type attributes
|
|
|
|
* @legacy_irq: IRQ number
|
|
|
|
* @workqueue: Workqueue for resets, port reconfigures and the HW monitor
|
|
|
|
* @reset_work: Scheduled reset workitem
|
|
|
|
* @monitor_work: Hardware monitor workitem
|
|
|
|
* @membase_phys: Memory BAR value as physical address
|
|
|
|
* @membase: Memory BAR value
|
|
|
|
* @biu_lock: BIU (bus interface unit) lock
|
|
|
|
* @interrupt_mode: Interrupt mode
|
|
|
|
* @i2c: I2C interface
|
|
|
|
* @board_info: Board-level information
|
|
|
|
* @state: Device state flag. Serialised by the rtnl_lock.
|
|
|
|
* @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
|
|
|
|
* @tx_queue: TX DMA queues
|
|
|
|
* @rx_queue: RX DMA queues
|
|
|
|
* @channel: Channels
|
|
|
|
* @rss_queues: Number of RSS queues
|
|
|
|
* @rx_buffer_len: RX buffer length
|
|
|
|
* @rx_buffer_order: Order (log2) of number of pages for each RX buffer
|
|
|
|
* @irq_status: Interrupt status buffer
|
|
|
|
* @last_irq_cpu: Last CPU to handle interrupt.
|
|
|
|
* This register is written with the SMP processor ID whenever an
|
|
|
|
* interrupt is handled. It is used by falcon_test_interrupt()
|
|
|
|
* to verify that an interrupt has occurred.
|
|
|
|
* @n_rx_nodesc_drop_cnt: RX no descriptor drop count
|
|
|
|
* @nic_data: Hardware dependant state
|
|
|
|
* @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and
|
|
|
|
* efx_reconfigure_port()
|
|
|
|
* @port_enabled: Port enabled indicator.
|
|
|
|
* Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
|
|
|
|
* efx_reconfigure_work with kernel interfaces. Safe to read under any
|
|
|
|
* one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
|
|
|
|
* be held to modify it.
|
|
|
|
* @port_initialized: Port initialized?
|
|
|
|
* @net_dev: Operating system network device. Consider holding the rtnl lock
|
|
|
|
* @rx_checksum_enabled: RX checksumming enabled
|
|
|
|
* @netif_stop_count: Port stop count
|
|
|
|
* @netif_stop_lock: Port stop lock
|
|
|
|
* @mac_stats: MAC statistics. These include all statistics the MACs
|
|
|
|
* can provide. Generic code converts these into a standard
|
|
|
|
* &struct net_device_stats.
|
|
|
|
* @stats_buffer: DMA buffer for statistics
|
|
|
|
* @stats_lock: Statistics update lock
|
|
|
|
* @mac_address: Permanent MAC address
|
|
|
|
* @phy_type: PHY type
|
|
|
|
* @phy_lock: PHY access lock
|
|
|
|
* @phy_op: PHY interface
|
|
|
|
* @phy_data: PHY private data (including PHY-specific stats)
|
|
|
|
* @mii: PHY interface
|
|
|
|
* @link_up: Link status
|
|
|
|
* @link_options: Link options (MII/GMII format)
|
|
|
|
* @n_link_state_changes: Number of times the link has changed state
|
|
|
|
* @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
|
|
|
|
* @multicast_hash: Multicast hash table
|
|
|
|
* @flow_control: Flow control flags - separate RX/TX so can't use link_options
|
|
|
|
* @reconfigure_work: work item for dealing with PHY events
|
|
|
|
*
|
|
|
|
* The @priv field of the corresponding &struct net_device points to
|
|
|
|
* this.
|
|
|
|
*/
|
|
|
|
struct efx_nic {
|
|
|
|
char name[IFNAMSIZ];
|
|
|
|
struct pci_dev *pci_dev;
|
|
|
|
const struct efx_nic_type *type;
|
|
|
|
int legacy_irq;
|
|
|
|
struct workqueue_struct *workqueue;
|
|
|
|
struct work_struct reset_work;
|
|
|
|
struct delayed_work monitor_work;
|
|
|
|
unsigned long membase_phys;
|
|
|
|
void __iomem *membase;
|
|
|
|
spinlock_t biu_lock;
|
|
|
|
enum efx_int_mode interrupt_mode;
|
|
|
|
|
|
|
|
struct efx_i2c_interface i2c;
|
|
|
|
struct efx_board board_info;
|
|
|
|
|
|
|
|
enum nic_state state;
|
|
|
|
enum reset_type reset_pending;
|
|
|
|
|
|
|
|
struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES];
|
|
|
|
struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
|
|
|
|
struct efx_channel channel[EFX_MAX_CHANNELS];
|
|
|
|
|
|
|
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int rss_queues;
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unsigned int rx_buffer_len;
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|
|
unsigned int rx_buffer_order;
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|
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struct efx_buffer irq_status;
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volatile signed int last_irq_cpu;
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|
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unsigned n_rx_nodesc_drop_cnt;
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void *nic_data;
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|
struct mutex mac_lock;
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|
|
int port_enabled;
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|
int port_initialized;
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struct net_device *net_dev;
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|
int rx_checksum_enabled;
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atomic_t netif_stop_count;
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|
spinlock_t netif_stop_lock;
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struct efx_mac_stats mac_stats;
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|
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struct efx_buffer stats_buffer;
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|
|
spinlock_t stats_lock;
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|
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unsigned char mac_address[ETH_ALEN];
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|
enum phy_type phy_type;
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|
|
spinlock_t phy_lock;
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|
|
struct efx_phy_operations *phy_op;
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|
|
void *phy_data;
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|
|
struct mii_if_info mii;
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int link_up;
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|
|
unsigned int link_options;
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|
|
unsigned int n_link_state_changes;
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|
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|
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|
|
int promiscuous;
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|
|
union efx_multicast_hash multicast_hash;
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|
|
enum efx_fc_type flow_control;
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|
|
struct work_struct reconfigure_work;
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|
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|
|
atomic_t rx_reset;
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|
|
|
};
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|
|
|
|
|
|
|
/**
|
|
|
|
* struct efx_nic_type - Efx device type definition
|
|
|
|
* @mem_bar: Memory BAR number
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|
|
|
* @mem_map_size: Memory BAR mapped size
|
|
|
|
* @txd_ptr_tbl_base: TX descriptor ring base address
|
|
|
|
* @rxd_ptr_tbl_base: RX descriptor ring base address
|
|
|
|
* @buf_tbl_base: Buffer table base address
|
|
|
|
* @evq_ptr_tbl_base: Event queue pointer table base address
|
|
|
|
* @evq_rptr_tbl_base: Event queue read-pointer table base address
|
|
|
|
* @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
|
|
|
|
* @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
|
|
|
|
* @evq_size: Event queue size (must be a power of two)
|
|
|
|
* @max_dma_mask: Maximum possible DMA mask
|
|
|
|
* @tx_dma_mask: TX DMA mask
|
|
|
|
* @bug5391_mask: Address mask for bug 5391 workaround
|
|
|
|
* @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
|
|
|
|
* @rx_xon_thresh: RX FIFO XON watermark (bytes)
|
|
|
|
* @rx_buffer_padding: Padding added to each RX buffer
|
|
|
|
* @max_interrupt_mode: Highest capability interrupt mode supported
|
|
|
|
* from &enum efx_init_mode.
|
|
|
|
* @phys_addr_channels: Number of channels with physically addressed
|
|
|
|
* descriptors
|
|
|
|
*/
|
|
|
|
struct efx_nic_type {
|
|
|
|
unsigned int mem_bar;
|
|
|
|
unsigned int mem_map_size;
|
|
|
|
unsigned int txd_ptr_tbl_base;
|
|
|
|
unsigned int rxd_ptr_tbl_base;
|
|
|
|
unsigned int buf_tbl_base;
|
|
|
|
unsigned int evq_ptr_tbl_base;
|
|
|
|
unsigned int evq_rptr_tbl_base;
|
|
|
|
|
|
|
|
unsigned int txd_ring_mask;
|
|
|
|
unsigned int rxd_ring_mask;
|
|
|
|
unsigned int evq_size;
|
|
|
|
dma_addr_t max_dma_mask;
|
|
|
|
unsigned int tx_dma_mask;
|
|
|
|
unsigned bug5391_mask;
|
|
|
|
|
|
|
|
int rx_xoff_thresh;
|
|
|
|
int rx_xon_thresh;
|
|
|
|
unsigned int rx_buffer_padding;
|
|
|
|
unsigned int max_interrupt_mode;
|
|
|
|
unsigned int phys_addr_channels;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**************************************************************************
|
|
|
|
*
|
|
|
|
* Prototypes and inline functions
|
|
|
|
*
|
|
|
|
*************************************************************************/
|
|
|
|
|
|
|
|
/* Iterate over all used channels */
|
|
|
|
#define efx_for_each_channel(_channel, _efx) \
|
|
|
|
for (_channel = &_efx->channel[0]; \
|
|
|
|
_channel < &_efx->channel[EFX_MAX_CHANNELS]; \
|
|
|
|
_channel++) \
|
|
|
|
if (!_channel->used_flags) \
|
|
|
|
continue; \
|
|
|
|
else
|
|
|
|
|
|
|
|
/* Iterate over all used channels with interrupts */
|
|
|
|
#define efx_for_each_channel_with_interrupt(_channel, _efx) \
|
|
|
|
for (_channel = &_efx->channel[0]; \
|
|
|
|
_channel < &_efx->channel[EFX_MAX_CHANNELS]; \
|
|
|
|
_channel++) \
|
|
|
|
if (!(_channel->used_flags && _channel->has_interrupt)) \
|
|
|
|
continue; \
|
|
|
|
else
|
|
|
|
|
|
|
|
/* Iterate over all used TX queues */
|
|
|
|
#define efx_for_each_tx_queue(_tx_queue, _efx) \
|
|
|
|
for (_tx_queue = &_efx->tx_queue[0]; \
|
|
|
|
_tx_queue < &_efx->tx_queue[EFX_MAX_TX_QUEUES]; \
|
|
|
|
_tx_queue++) \
|
|
|
|
if (!_tx_queue->used) \
|
|
|
|
continue; \
|
|
|
|
else
|
|
|
|
|
|
|
|
/* Iterate over all TX queues belonging to a channel */
|
|
|
|
#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
|
|
|
|
for (_tx_queue = &_channel->efx->tx_queue[0]; \
|
|
|
|
_tx_queue < &_channel->efx->tx_queue[EFX_MAX_TX_QUEUES]; \
|
|
|
|
_tx_queue++) \
|
|
|
|
if ((!_tx_queue->used) || \
|
|
|
|
(_tx_queue->channel != _channel)) \
|
|
|
|
continue; \
|
|
|
|
else
|
|
|
|
|
|
|
|
/* Iterate over all used RX queues */
|
|
|
|
#define efx_for_each_rx_queue(_rx_queue, _efx) \
|
|
|
|
for (_rx_queue = &_efx->rx_queue[0]; \
|
|
|
|
_rx_queue < &_efx->rx_queue[EFX_MAX_RX_QUEUES]; \
|
|
|
|
_rx_queue++) \
|
|
|
|
if (!_rx_queue->used) \
|
|
|
|
continue; \
|
|
|
|
else
|
|
|
|
|
|
|
|
/* Iterate over all RX queues belonging to a channel */
|
|
|
|
#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
|
|
|
|
for (_rx_queue = &_channel->efx->rx_queue[0]; \
|
|
|
|
_rx_queue < &_channel->efx->rx_queue[EFX_MAX_RX_QUEUES]; \
|
|
|
|
_rx_queue++) \
|
|
|
|
if ((!_rx_queue->used) || \
|
|
|
|
(_rx_queue->channel != _channel)) \
|
|
|
|
continue; \
|
|
|
|
else
|
|
|
|
|
|
|
|
/* Returns a pointer to the specified receive buffer in the RX
|
|
|
|
* descriptor queue.
|
|
|
|
*/
|
|
|
|
static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
|
|
|
|
unsigned int index)
|
|
|
|
{
|
|
|
|
return (&rx_queue->buffer[index]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set bit in a little-endian bitfield */
|
|
|
|
static inline void set_bit_le(int nr, unsigned char *addr)
|
|
|
|
{
|
|
|
|
addr[nr / 8] |= (1 << (nr % 8));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear bit in a little-endian bitfield */
|
|
|
|
static inline void clear_bit_le(int nr, unsigned char *addr)
|
|
|
|
{
|
|
|
|
addr[nr / 8] &= ~(1 << (nr % 8));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* EFX_MAX_FRAME_LEN - calculate maximum frame length
|
|
|
|
*
|
|
|
|
* This calculates the maximum frame length that will be used for a
|
|
|
|
* given MTU. The frame length will be equal to the MTU plus a
|
|
|
|
* constant amount of header space and padding. This is the quantity
|
|
|
|
* that the net driver will program into the MAC as the maximum frame
|
|
|
|
* length.
|
|
|
|
*
|
|
|
|
* The 10G MAC used in Falcon requires 8-byte alignment on the frame
|
|
|
|
* length, so we round up to the nearest 8.
|
|
|
|
*/
|
|
|
|
#define EFX_MAX_FRAME_LEN(mtu) \
|
|
|
|
((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
|
|
|
|
|
|
|
|
|
|
|
|
#endif /* EFX_NET_DRIVER_H */
|