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android_kernel_xiaomi_sm8350/arch/powerpc/kernel/misc.S

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[POWERPC] Consolidate some of kernel/misc*.S There were some common functions (mainly i/o). Also some small white space cleanups and remove a couple of small unused functions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-27 21:55:49 -04:00
/*
* This file contains miscellaneous low-level functions.
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras.
*
* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
*
[POWERPC] Make setjmp/longjmp code usable outside of xmon This makes the setjmp/longjmp code used by xmon, generically available to other code. It also removes the requirement for debugger hooks to be only called on 0x300 (data storage) exception. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-17 23:50:30 -05:00
* setjmp/longjmp code by Paul Mackerras.
*
[POWERPC] Consolidate some of kernel/misc*.S There were some common functions (mainly i/o). Also some small white space cleanups and remove a couple of small unused functions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-27 21:55:49 -04:00
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/ppc_asm.h>
[POWERPC] kernel_execve is identical in 32 and 64 bit so consolidate it into misc.S. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-27 19:13:02 -05:00
#include <asm/unistd.h>
[POWERPC] Make setjmp/longjmp code usable outside of xmon This makes the setjmp/longjmp code used by xmon, generically available to other code. It also removes the requirement for debugger hooks to be only called on 0x300 (data storage) exception. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-17 23:50:30 -05:00
#include <asm/asm-compat.h>
#include <asm/asm-offsets.h>
[POWERPC] Consolidate some of kernel/misc*.S There were some common functions (mainly i/o). Also some small white space cleanups and remove a couple of small unused functions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-27 21:55:49 -04:00
.text
/*
* Returns (address we are running at) - (address we were linked at)
* for use before the text and data are mapped to KERNELBASE.
*/
_GLOBAL(reloc_offset)
mflr r0
bl 1f
1: mflr r3
powerpc: Use LOAD_REG_IMMEDIATE only for constants on 64-bit Using LOAD_REG_IMMEDIATE to get the address of kernel symbols generates 5 instructions where LOAD_REG_ADDR can do it in one, and will generate R_PPC64_ADDR16_* relocations in the output when we get to making the kernel as a position-independent executable, which we'd rather not have to handle. This changes various bits of assembly code to use LOAD_REG_ADDR when we need to get the address of a symbol, or to use suitable position-independent code for cases where we can't access the TOC for various reasons, or if we're not running at the address we were linked at. It also cleans up a few minor things; there's no reason to save and restore SRR0/1 around RTAS calls, __mmu_off can get the return address from LR more conveniently than the caller can supply it in R4 (and we already assume elsewhere that EA == RA if the MMU is on in early boot), and enable_64b_mode was using 5 instructions where 2 would do. Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-29 21:41:12 -04:00
PPC_LL r4,(2f-1b)(r3)
[POWERPC] Consolidate some of kernel/misc*.S There were some common functions (mainly i/o). Also some small white space cleanups and remove a couple of small unused functions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-27 21:55:49 -04:00
subf r3,r4,r3
mtlr r0
blr
powerpc: Use LOAD_REG_IMMEDIATE only for constants on 64-bit Using LOAD_REG_IMMEDIATE to get the address of kernel symbols generates 5 instructions where LOAD_REG_ADDR can do it in one, and will generate R_PPC64_ADDR16_* relocations in the output when we get to making the kernel as a position-independent executable, which we'd rather not have to handle. This changes various bits of assembly code to use LOAD_REG_ADDR when we need to get the address of a symbol, or to use suitable position-independent code for cases where we can't access the TOC for various reasons, or if we're not running at the address we were linked at. It also cleans up a few minor things; there's no reason to save and restore SRR0/1 around RTAS calls, __mmu_off can get the return address from LR more conveniently than the caller can supply it in R4 (and we already assume elsewhere that EA == RA if the MMU is on in early boot), and enable_64b_mode was using 5 instructions where 2 would do. Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-29 21:41:12 -04:00
.align 3
2: PPC_LONG 1b
[POWERPC] Consolidate some of kernel/misc*.S There were some common functions (mainly i/o). Also some small white space cleanups and remove a couple of small unused functions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-27 21:55:49 -04:00
/*
* add_reloc_offset(x) returns x + reloc_offset().
*/
_GLOBAL(add_reloc_offset)
mflr r0
bl 1f
1: mflr r5
powerpc: Use LOAD_REG_IMMEDIATE only for constants on 64-bit Using LOAD_REG_IMMEDIATE to get the address of kernel symbols generates 5 instructions where LOAD_REG_ADDR can do it in one, and will generate R_PPC64_ADDR16_* relocations in the output when we get to making the kernel as a position-independent executable, which we'd rather not have to handle. This changes various bits of assembly code to use LOAD_REG_ADDR when we need to get the address of a symbol, or to use suitable position-independent code for cases where we can't access the TOC for various reasons, or if we're not running at the address we were linked at. It also cleans up a few minor things; there's no reason to save and restore SRR0/1 around RTAS calls, __mmu_off can get the return address from LR more conveniently than the caller can supply it in R4 (and we already assume elsewhere that EA == RA if the MMU is on in early boot), and enable_64b_mode was using 5 instructions where 2 would do. Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-29 21:41:12 -04:00
PPC_LL r4,(2f-1b)(r5)
[POWERPC] Consolidate some of kernel/misc*.S There were some common functions (mainly i/o). Also some small white space cleanups and remove a couple of small unused functions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-27 21:55:49 -04:00
subf r5,r4,r5
add r3,r3,r5
mtlr r0
blr
[POWERPC] kernel_execve is identical in 32 and 64 bit so consolidate it into misc.S. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-27 19:13:02 -05:00
powerpc: Use LOAD_REG_IMMEDIATE only for constants on 64-bit Using LOAD_REG_IMMEDIATE to get the address of kernel symbols generates 5 instructions where LOAD_REG_ADDR can do it in one, and will generate R_PPC64_ADDR16_* relocations in the output when we get to making the kernel as a position-independent executable, which we'd rather not have to handle. This changes various bits of assembly code to use LOAD_REG_ADDR when we need to get the address of a symbol, or to use suitable position-independent code for cases where we can't access the TOC for various reasons, or if we're not running at the address we were linked at. It also cleans up a few minor things; there's no reason to save and restore SRR0/1 around RTAS calls, __mmu_off can get the return address from LR more conveniently than the caller can supply it in R4 (and we already assume elsewhere that EA == RA if the MMU is on in early boot), and enable_64b_mode was using 5 instructions where 2 would do. Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-29 21:41:12 -04:00
.align 3
2: PPC_LONG 1b
[POWERPC] kernel_execve is identical in 32 and 64 bit so consolidate it into misc.S. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-11-27 19:13:02 -05:00
_GLOBAL(kernel_execve)
li r0,__NR_execve
sc
bnslr
neg r3,r3
blr
[POWERPC] Make setjmp/longjmp code usable outside of xmon This makes the setjmp/longjmp code used by xmon, generically available to other code. It also removes the requirement for debugger hooks to be only called on 0x300 (data storage) exception. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-17 23:50:30 -05:00
_GLOBAL(setjmp)
mflr r0
PPC_STL r0,0(r3)
PPC_STL r1,SZL(r3)
PPC_STL r2,2*SZL(r3)
mfcr r0
PPC_STL r0,3*SZL(r3)
PPC_STL r13,4*SZL(r3)
PPC_STL r14,5*SZL(r3)
PPC_STL r15,6*SZL(r3)
PPC_STL r16,7*SZL(r3)
PPC_STL r17,8*SZL(r3)
PPC_STL r18,9*SZL(r3)
PPC_STL r19,10*SZL(r3)
PPC_STL r20,11*SZL(r3)
PPC_STL r21,12*SZL(r3)
PPC_STL r22,13*SZL(r3)
PPC_STL r23,14*SZL(r3)
PPC_STL r24,15*SZL(r3)
PPC_STL r25,16*SZL(r3)
PPC_STL r26,17*SZL(r3)
PPC_STL r27,18*SZL(r3)
PPC_STL r28,19*SZL(r3)
PPC_STL r29,20*SZL(r3)
PPC_STL r30,21*SZL(r3)
PPC_STL r31,22*SZL(r3)
li r3,0
blr
_GLOBAL(longjmp)
PPC_LCMPI r4,0
bne 1f
li r4,1
1: PPC_LL r13,4*SZL(r3)
PPC_LL r14,5*SZL(r3)
PPC_LL r15,6*SZL(r3)
PPC_LL r16,7*SZL(r3)
PPC_LL r17,8*SZL(r3)
PPC_LL r18,9*SZL(r3)
PPC_LL r19,10*SZL(r3)
PPC_LL r20,11*SZL(r3)
PPC_LL r21,12*SZL(r3)
PPC_LL r22,13*SZL(r3)
PPC_LL r23,14*SZL(r3)
PPC_LL r24,15*SZL(r3)
PPC_LL r25,16*SZL(r3)
PPC_LL r26,17*SZL(r3)
PPC_LL r27,18*SZL(r3)
PPC_LL r28,19*SZL(r3)
PPC_LL r29,20*SZL(r3)
PPC_LL r30,21*SZL(r3)
PPC_LL r31,22*SZL(r3)
PPC_LL r0,3*SZL(r3)
mtcrf 0x38,r0
PPC_LL r0,0(r3)
PPC_LL r1,SZL(r3)
PPC_LL r2,2*SZL(r3)
mtlr r0
mr r3,r4
blr
powerpc: Add cputable entry for POWER7 Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-06-17 20:47:26 -04:00
_GLOBAL(__setup_cpu_power7)
_GLOBAL(__restore_cpu_power7)
/* place holder */
blr
powerpc/perf_events: Fix call-graph recording, add perf_arch_fetch_caller_regs This implements a powerpc version of perf_arch_fetch_caller_regs to get correct call-graphs. It's implemented in assembly because that way we can be sure there isn't a stack frame for perf_arch_fetch_caller_regs. If it was in C, gcc might or might not create a stack frame for it, which would affect the number of levels we have to skip. With this, we see results from perf record -e lock:lock_acquire like this: # Samples: 24878 # # Overhead Command Shared Object Symbol # ........ .............. ................. ...... # 14.99% perf [kernel.kallsyms] [k] ._raw_spin_lock | --- ._raw_spin_lock | |--25.00%-- .alloc_fd | (nil) | | | |--50.00%-- .anon_inode_getfd | | .sys_perf_event_open | | syscall_exit | | syscall | | create_counter | | __cmd_record | | run_builtin | | main | | 0xfd2e704 | | 0xfd2e8c0 | | (nil) ... etc. Signed-off-by: Paul Mackerras <paulus@samba.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: anton@samba.org Cc: linuxppc-dev@ozlabs.org Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> LKML-Reference: <20100318050513.GA6575@drongo> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-18 01:05:13 -04:00
/*
* Get a minimal set of registers for our caller's nth caller.
* r3 = regs pointer, r5 = n.
*
* We only get R1 (stack pointer), NIP (next instruction pointer)
* and LR (link register). These are all we can get in the
* general case without doing complicated stack unwinding, but
* fortunately they are enough to do a stack backtrace, which
* is all we need them for.
*/
_GLOBAL(perf_arch_fetch_caller_regs)
mr r6,r1
cmpwi r5,0
mflr r4
ble 2f
mtctr r5
1: PPC_LL r6,0(r6)
bdnz 1b
PPC_LL r4,PPC_LR_STKOFF(r6)
2: PPC_LL r7,0(r6)
PPC_LL r7,PPC_LR_STKOFF(r7)
PPC_STL r6,GPR1-STACK_FRAME_OVERHEAD(r3)
PPC_STL r4,_NIP-STACK_FRAME_OVERHEAD(r3)
PPC_STL r7,_LINK-STACK_FRAME_OVERHEAD(r3)
blr
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