417 lines
11 KiB
C
417 lines
11 KiB
C
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/*
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* drivers/mtd/tx4925ndfmc.c
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* Toshiba RBTX4925 reference board, which is a SmartMediaCard. It supports
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* 16MiB, 32MiB and 64MiB cards.
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*
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* Author: MontaVista Software, Inc. source@mvista.com
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*
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* Derived from drivers/mtd/autcpu12.c
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* Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
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*
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* $Id: tx4925ndfmc.c,v 1.5 2004/10/05 13:50:20 gleixner Exp $
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*
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* Copyright (C) 2001 Toshiba Corporation
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*
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* 2003 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/tx4925/tx4925_nand.h>
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extern struct nand_oobinfo jffs2_oobinfo;
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/*
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* MTD structure for RBTX4925 board
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*/
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static struct mtd_info *tx4925ndfmc_mtd = NULL;
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/*
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* Define partitions for flash devices
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*/
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static struct mtd_partition partition_info16k[] = {
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{ .name = "RBTX4925 flash partition 1",
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.offset = 0,
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.size = 8 * 0x00100000 },
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{ .name = "RBTX4925 flash partition 2",
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.offset = 8 * 0x00100000,
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.size = 8 * 0x00100000 },
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};
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static struct mtd_partition partition_info32k[] = {
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{ .name = "RBTX4925 flash partition 1",
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.offset = 0,
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.size = 8 * 0x00100000 },
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{ .name = "RBTX4925 flash partition 2",
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.offset = 8 * 0x00100000,
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.size = 24 * 0x00100000 },
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};
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static struct mtd_partition partition_info64k[] = {
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{ .name = "User FS",
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.offset = 0,
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.size = 16 * 0x00100000 },
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{ .name = "RBTX4925 flash partition 2",
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.offset = 16 * 0x00100000,
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.size = 48 * 0x00100000},
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};
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static struct mtd_partition partition_info128k[] = {
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{ .name = "Skip bad section",
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.offset = 0,
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.size = 16 * 0x00100000 },
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{ .name = "User FS",
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.offset = 16 * 0x00100000,
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.size = 112 * 0x00100000 },
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};
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#define NUM_PARTITIONS16K 2
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#define NUM_PARTITIONS32K 2
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#define NUM_PARTITIONS64K 2
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#define NUM_PARTITIONS128K 2
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/*
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* hardware specific access to control-lines
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*/
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static void tx4925ndfmc_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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switch(cmd){
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case NAND_CTL_SETCLE:
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tx4925_ndfmcptr->mcr |= TX4925_NDFMCR_CLE;
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break;
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case NAND_CTL_CLRCLE:
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tx4925_ndfmcptr->mcr &= ~TX4925_NDFMCR_CLE;
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break;
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case NAND_CTL_SETALE:
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tx4925_ndfmcptr->mcr |= TX4925_NDFMCR_ALE;
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break;
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case NAND_CTL_CLRALE:
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tx4925_ndfmcptr->mcr &= ~TX4925_NDFMCR_ALE;
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break;
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case NAND_CTL_SETNCE:
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tx4925_ndfmcptr->mcr |= TX4925_NDFMCR_CE;
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break;
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case NAND_CTL_CLRNCE:
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tx4925_ndfmcptr->mcr &= ~TX4925_NDFMCR_CE;
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break;
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case NAND_CTL_SETWP:
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tx4925_ndfmcptr->mcr |= TX4925_NDFMCR_WE;
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break;
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case NAND_CTL_CLRWP:
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tx4925_ndfmcptr->mcr &= ~TX4925_NDFMCR_WE;
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break;
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}
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}
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/*
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* read device ready pin
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*/
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static int tx4925ndfmc_device_ready(struct mtd_info *mtd)
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{
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int ready;
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ready = (tx4925_ndfmcptr->sr & TX4925_NDSFR_BUSY) ? 0 : 1;
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return ready;
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}
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void tx4925ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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/* reset first */
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tx4925_ndfmcptr->mcr |= TX4925_NDFMCR_ECC_CNTL_MASK;
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tx4925_ndfmcptr->mcr &= ~TX4925_NDFMCR_ECC_CNTL_MASK;
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tx4925_ndfmcptr->mcr |= TX4925_NDFMCR_ECC_CNTL_ENAB;
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}
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static void tx4925ndfmc_disable_ecc(void)
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{
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tx4925_ndfmcptr->mcr &= ~TX4925_NDFMCR_ECC_CNTL_MASK;
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}
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static void tx4925ndfmc_enable_read_ecc(void)
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{
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tx4925_ndfmcptr->mcr &= ~TX4925_NDFMCR_ECC_CNTL_MASK;
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tx4925_ndfmcptr->mcr |= TX4925_NDFMCR_ECC_CNTL_READ;
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}
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void tx4925ndfmc_readecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code){
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int i;
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u_char *ecc = ecc_code;
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tx4925ndfmc_enable_read_ecc();
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for (i = 0;i < 6;i++,ecc++)
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*ecc = tx4925_read_nfmc(&(tx4925_ndfmcptr->dtr));
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tx4925ndfmc_disable_ecc();
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}
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void tx4925ndfmc_device_setup(void)
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{
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*(unsigned char *)0xbb005000 &= ~0x08;
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/* reset NDFMC */
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tx4925_ndfmcptr->rstr |= TX4925_NDFRSTR_RST;
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while (tx4925_ndfmcptr->rstr & TX4925_NDFRSTR_RST);
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/* setup BusSeparete, Hold Time, Strobe Pulse Width */
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tx4925_ndfmcptr->mcr = TX4925_BSPRT ? TX4925_NDFMCR_BSPRT : 0;
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tx4925_ndfmcptr->spr = TX4925_HOLD << 4 | TX4925_SPW;
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}
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static u_char tx4925ndfmc_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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return tx4925_read_nfmc(this->IO_ADDR_R);
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}
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static void tx4925ndfmc_nand_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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tx4925_write_nfmc(byte, this->IO_ADDR_W);
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}
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static void tx4925ndfmc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++)
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tx4925_write_nfmc(buf[i], this->IO_ADDR_W);
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}
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static void tx4925ndfmc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++)
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buf[i] = tx4925_read_nfmc(this->IO_ADDR_R);
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}
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static int tx4925ndfmc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++)
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if (buf[i] != tx4925_read_nfmc(this->IO_ADDR_R))
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return -EFAULT;
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return 0;
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}
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/*
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* Send command to NAND device
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*/
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static void tx4925ndfmc_nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
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{
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register struct nand_chip *this = mtd->priv;
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/* Begin command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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/*
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* Write out the command to the device.
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*/
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->oobblock) {
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/* OOB area */
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column -= mtd->oobblock;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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this->write_byte(mtd, readcmd);
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}
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this->write_byte(mtd, command);
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/* Set ALE and clear CLE to start address cycle */
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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if (column != -1 || page_addr != -1) {
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this->hwcontrol(mtd, NAND_CTL_SETALE);
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/* Serially input address */
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if (column != -1)
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this->write_byte(mtd, column);
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if (page_addr != -1) {
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this->write_byte(mtd, (unsigned char) (page_addr & 0xff));
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this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff));
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/* One more address cycle for higher density devices */
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if (mtd->size & 0x0c000000)
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this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0x0f));
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}
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/* Latch in address */
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this->hwcontrol(mtd, NAND_CTL_CLRALE);
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}
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/*
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* program and erase have their own busy handlers
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* status and sequential in needs no delay
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*/
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switch (command) {
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case NAND_CMD_PAGEPROG:
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/* Turn off WE */
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this->hwcontrol (mtd, NAND_CTL_CLRWP);
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return;
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case NAND_CMD_SEQIN:
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/* Turn on WE */
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this->hwcontrol (mtd, NAND_CTL_SETWP);
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return;
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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if (this->dev_ready)
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break;
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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this->write_byte(mtd, NAND_CMD_STATUS);
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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while ( !(this->read_byte(mtd) & 0x40));
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return;
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/* This applies to read commands */
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default:
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/*
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* If we don't have access to the busy pin, we apply the given
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* command delay
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*/
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if (!this->dev_ready) {
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udelay (this->chip_delay);
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return;
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}
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}
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/* wait until command is processed */
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while (!this->dev_ready(mtd));
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}
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partitio
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n **pparts, char *);
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#endif
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/*
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* Main initialization routine
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*/
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extern int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
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int __init tx4925ndfmc_init (void)
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{
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struct nand_chip *this;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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tx4925ndfmc_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
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GFP_KERNEL);
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if (!tx4925ndfmc_mtd) {
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printk ("Unable to allocate RBTX4925 NAND MTD device structure.\n");
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err = -ENOMEM;
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goto out;
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}
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tx4925ndfmc_device_setup();
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/* io is indirect via a register so don't need to ioremap address */
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/* Get pointer to private data */
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this = (struct nand_chip *) (&tx4925ndfmc_mtd[1]);
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/* Initialize structures */
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memset((char *) tx4925ndfmc_mtd, 0, sizeof(struct mtd_info));
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memset((char *) this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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tx4925ndfmc_mtd->priv = this;
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = (void __iomem *)&(tx4925_ndfmcptr->dtr);
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this->IO_ADDR_W = (void __iomem *)&(tx4925_ndfmcptr->dtr);
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this->hwcontrol = tx4925ndfmc_hwcontrol;
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this->enable_hwecc = tx4925ndfmc_enable_hwecc;
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this->calculate_ecc = tx4925ndfmc_readecc;
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this->correct_data = nand_correct_data;
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this->eccmode = NAND_ECC_HW6_512;
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this->dev_ready = tx4925ndfmc_device_ready;
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/* 20 us command delay time */
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this->chip_delay = 20;
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this->read_byte = tx4925ndfmc_nand_read_byte;
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this->write_byte = tx4925ndfmc_nand_write_byte;
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this->cmdfunc = tx4925ndfmc_nand_command;
|
||
|
|
this->write_buf = tx4925ndfmc_nand_write_buf;
|
||
|
|
this->read_buf = tx4925ndfmc_nand_read_buf;
|
||
|
|
this->verify_buf = tx4925ndfmc_nand_verify_buf;
|
||
|
|
|
||
|
|
/* Scan to find existance of the device */
|
||
|
|
if (nand_scan (tx4925ndfmc_mtd, 1)) {
|
||
|
|
err = -ENXIO;
|
||
|
|
goto out_ior;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Register the partitions */
|
||
|
|
#ifdef CONFIG_MTD_CMDLINE_PARTS
|
||
|
|
{
|
||
|
|
int mtd_parts_nb = 0;
|
||
|
|
struct mtd_partition *mtd_parts = 0;
|
||
|
|
mtd_parts_nb = parse_cmdline_partitions(tx4925ndfmc_mtd, &mtd_parts, "tx4925ndfmc");
|
||
|
|
if (mtd_parts_nb > 0)
|
||
|
|
add_mtd_partitions(tx4925ndfmc_mtd, mtd_parts, mtd_parts_nb);
|
||
|
|
else
|
||
|
|
add_mtd_device(tx4925ndfmc_mtd);
|
||
|
|
}
|
||
|
|
#else /* ifdef CONFIG_MTD_CMDLINE_PARTS */
|
||
|
|
switch(tx4925ndfmc_mtd->size){
|
||
|
|
case 0x01000000: add_mtd_partitions(tx4925ndfmc_mtd, partition_info16k, NUM_PARTITIONS16K); break;
|
||
|
|
case 0x02000000: add_mtd_partitions(tx4925ndfmc_mtd, partition_info32k, NUM_PARTITIONS32K); break;
|
||
|
|
case 0x04000000: add_mtd_partitions(tx4925ndfmc_mtd, partition_info64k, NUM_PARTITIONS64K); break;
|
||
|
|
case 0x08000000: add_mtd_partitions(tx4925ndfmc_mtd, partition_info128k, NUM_PARTITIONS128K); break;
|
||
|
|
default: {
|
||
|
|
printk ("Unsupported SmartMedia device\n");
|
||
|
|
err = -ENXIO;
|
||
|
|
goto out_ior;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* ifdef CONFIG_MTD_CMDLINE_PARTS */
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
out_ior:
|
||
|
|
out:
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(tx4925ndfmc_init);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Clean up routine
|
||
|
|
*/
|
||
|
|
#ifdef MODULE
|
||
|
|
static void __exit tx4925ndfmc_cleanup (void)
|
||
|
|
{
|
||
|
|
/* Release resources, unregister device */
|
||
|
|
nand_release (tx4925ndfmc_mtd);
|
||
|
|
|
||
|
|
/* Free the MTD device structure */
|
||
|
|
kfree (tx4925ndfmc_mtd);
|
||
|
|
}
|
||
|
|
module_exit(tx4925ndfmc_cleanup);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_AUTHOR("Alice Hennessy <ahennessy@mvista.com>");
|
||
|
|
MODULE_DESCRIPTION("Glue layer for SmartMediaCard on Toshiba RBTX4925");
|