285 lines
5.8 KiB
ArmAsm
285 lines
5.8 KiB
ArmAsm
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/*
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* linux/arch/m32r/kernel/head.S
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*
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* M32R startup code.
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*
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* Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto
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*/
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#include <linux/init.h>
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__INIT
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__INITDATA
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.text
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/assembler.h>
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#include <asm/m32r.h>
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#include <asm/mmu_context.h>
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/*
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* References to members of the boot_cpu_data structure.
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*/
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.text
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.global start_kernel
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.global __bss_start
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.global _end
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ENTRY(stext)
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ENTRY(_stext)
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ENTRY(startup_32)
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/* Setup up the stack pointer */
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LDIMM (r0, spi_stack_top)
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LDIMM (r1, spu_stack_top)
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mvtc r0, spi
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mvtc r1, spu
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/* Initilalize PSW */
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ldi r0, #0x0000 /* use SPI, disable EI */
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mvtc r0, psw
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/* Set up the stack pointer */
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LDIMM (r0, stack_start)
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ld r0, @r0
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mvtc r0, spi
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/*
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* Clear BSS first so that there are no surprises...
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*/
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#ifdef CONFIG_ISA_DUAL_ISSUE
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LDIMM (r2, __bss_start)
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LDIMM (r3, _end)
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sub r3, r2 ; BSS size in bytes
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; R4 = BSS size in longwords (rounded down)
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mv r4, r3 || ldi r1, #0
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srli r4, #4 || addi r2, #-4
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beqz r4, .Lendloop1
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.Lloop1:
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#ifndef CONFIG_CHIP_M32310
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; Touch memory for the no-write-allocating cache.
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ld r0, @(4,r2)
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#endif
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st r1, @+r2 || addi r4, #-1
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st r1, @+r2
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st r1, @+r2
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st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
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bnc .Lloop1
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.Lendloop1:
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and3 r4, r3, #15
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addi r2, #4
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beqz r4, .Lendloop2
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.Lloop2:
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stb r1, @r2 || addi r4, #-1
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addi r2, #1
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bnez r4, .Lloop2
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.Lendloop2:
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#else /* not CONFIG_ISA_DUAL_ISSUE */
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LDIMM (r2, __bss_start)
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LDIMM (r3, _end)
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sub r3, r2 ; BSS size in bytes
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mv r4, r3
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srli r4, #2 ; R4 = BSS size in longwords (rounded down)
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ldi r1, #0 ; clear R1 for longwords store
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addi r2, #-4 ; account for pre-inc store
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beqz r4, .Lendloop1 ; any more to go?
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.Lloop1:
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st r1, @+r2 ; yep, zero out another longword
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addi r4, #-1 ; decrement count
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bnez r4, .Lloop1 ; go do some more
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.Lendloop1:
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and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear
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addi r2, #4 ; account for pre-inc store
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beqz r4, .Lendloop2 ; any more to go?
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.Lloop2:
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stb r1, @r2 ; yep, zero out another byte
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addi r2, #1 ; bump address
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addi r4, #-1 ; decrement count
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bnez r4, .Lloop2 ; go do some more
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.Lendloop2:
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#endif /* not CONFIG_ISA_DUAL_ISSUE */
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#if 0 /* M32R_FIXME */
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/*
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* Copy data segment from ROM to RAM.
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*/
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.global ROM_D, TOP_DATA, END_DATA
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LDIMM (r1, ROM_D)
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LDIMM (r2, TOP_DATA)
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LDIMM (r3, END_DATA)
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addi r2, #-4
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addi r3, #-4
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loop1:
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ld r0, @r1+
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st r0, @+r2
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cmp r2, r3
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bc loop1
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#endif /* 0 */
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/* Jump to kernel */
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LDIMM (r2, start_kernel)
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jl r2
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.fillinsn
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1:
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bra 1b ; main should never return here, but
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; just in case, we know what happens.
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#ifdef CONFIG_SMP
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/*
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* AP startup routine
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*/
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.text
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.global eit_vector
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ENTRY(startup_AP)
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;; setup EVB
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LDIMM (r4, eit_vector)
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mvtc r4, cr5
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;; enable MMU
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LDIMM (r2, init_tlb)
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jl r2
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seth r4, #high(MATM)
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or3 r4, r4, #low(MATM)
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ldi r5, #0x01
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st r5, @r4 ; Set MATM Reg(T bit ON)
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ld r6, @r4 ; MATM Check
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LDIMM (r5, 1f)
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jmp r5 ; enable MMU
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nop
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.fillinsn
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1:
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;; ISN check
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ld r6, @r4 ; MATM Check
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seth r4, #high(M32R_ICU_ISTS_ADDR)
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or3 r4, r4, #low(M32R_ICU_ISTS_ADDR)
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ld r5, @r4 ; Read ISTSi reg.
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mv r6, r5
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slli r5, #13 ; PIML check
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srli r5, #13 ;
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seth r4, #high(M32R_ICU_IMASK_ADDR)
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or3 r4, r4, #low(M32R_ICU_IMASK_ADDR)
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st r5, @r4 ; Write IMASKi reg.
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slli r6, #4 ; ISN check
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srli r6, #26 ;
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seth r4, #high(M32R_IRQ_IPI5)
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or3 r4, r4, #low(M32R_IRQ_IPI5)
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bne r4, r6, 2f ; if (ISN != CPU_BOOT_IPI) goto sleep;
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;; check cpu_bootout_map and set cpu_bootin_map
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LDIMM (r4, cpu_bootout_map)
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ld r4, @r4
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seth r5, #high(M32R_CPUID_PORTL)
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or3 r5, r5, #low(M32R_CPUID_PORTL)
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ld r5, @r5
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ldi r6, #1
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sll r6, r5
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and r4, r6
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beqz r4, 2f
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LDIMM (r4, cpu_bootin_map)
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ld r5, @r4
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or r5, r6
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st r6, @r4
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;; clear PSW
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ldi r4, #0
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mvtc r4, psw
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;; setup SPI
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LDIMM (r4, stack_start)
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ld r4, @r4
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mvtc r4, spi
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;; setup BPC (start_secondary)
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LDIMM (r4, start_secondary)
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mvtc r4, bpc
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rte ; goto startup_secondary
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nop
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nop
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.fillinsn
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2:
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;; disable MMU
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seth r4, #high(MATM)
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or3 r4, r4, #low(MATM)
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ldi r5, #0
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st r5, @r4 ; Set MATM Reg(T bit OFF)
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ld r6, @r4 ; MATM Check
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LDIMM (r4, 3f)
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seth r5, #high(__PAGE_OFFSET)
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or3 r5, r5, #low(__PAGE_OFFSET)
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not r5, r5
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and r4, r5
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jmp r4 ; disable MMU
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nop
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.fillinsn
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3:
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;; SLEEP and wait IPI
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LDIMM (r4, AP_loop)
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seth r5, #high(__PAGE_OFFSET)
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or3 r5, r5, #low(__PAGE_OFFSET)
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not r5, r5
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and r4, r5
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jmp r4
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nop
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nop
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#endif /* CONFIG_SMP */
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ENTRY(stack_start)
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.long init_thread_union+8192
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.long __KERNEL_DS
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/*
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* This is initialized to create a identity-mapping at 0-4M (for bootup
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* purposes) and another mapping of the 0-4M area at virtual address
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* PAGE_OFFSET.
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*/
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.text
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#define MOUNT_ROOT_RDONLY 1
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#define RAMDISK_FLAGS 0 ; 1024KB
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#define ORIG_ROOT_DEV 0x0100 ; /dev/ram0 (major:01, minor:00)
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#define LOADER_TYPE 1 ; (??? - non-zero value seems
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; to be needed to boot from initrd)
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#define COMMAND_LINE ""
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.section .empty_zero_page, "aw"
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ENTRY(empty_zero_page)
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.long MOUNT_ROOT_RDONLY /* offset: +0x00 */
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.long RAMDISK_FLAGS
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.long ORIG_ROOT_DEV
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.long LOADER_TYPE
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.long 0 /* INITRD_START */ /* +0x10 */
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.long 0 /* INITRD_SIZE */
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.long 0 /* CPU_CLOCK */
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.long 0 /* BUS_CLOCK */
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.long 0 /* TIMER_DIVIDE */ /* +0x20 */
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.balign 256,0
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.asciz COMMAND_LINE
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.byte 0
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.balign 4096,0,4096
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/*------------------------------------------------------------------------
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* Stack area
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*/
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.section .spi
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ALIGN
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.global spi_stack_top
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.zero 1024
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spi_stack_top:
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.section .spu
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ALIGN
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.global spu_stack_top
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.zero 1024
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spu_stack_top:
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.end
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