72 lines
2.8 KiB
C
72 lines
2.8 KiB
C
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/*
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* include/asm-mips/dec/kn05.h
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*
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* DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
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* definitions.
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*
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* Copyright (C) 2002, 2003 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* WARNING! All this information is pure guesswork based on the
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* ROM. It is provided here in hope it will give someone some
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* food for thought. No documentation for the KN05 module has
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* been located so far.
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*/
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#ifndef __ASM_MIPS_DEC_KN05_H
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#define __ASM_MIPS_DEC_KN05_H
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#include <asm/dec/ioasic_addrs.h>
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/*
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* The oncard MB (Memory Buffer) ASIC provides an additional address
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* decoder. Certain address ranges within the "high" 16 slots are
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* passed to the I/O ASIC's decoder like with the KN03. Others are
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* handled locally. "Low" slots are always passed.
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*/
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#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */
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#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */
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#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
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#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
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#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */
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#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */
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#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */
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#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */
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#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */
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#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */
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#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */
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/*
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* Bits for the MB interrupt register.
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* The register appears read-only.
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*/
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#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */
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#define KN05_MB_INT_RTC (1<<1) /* RTC? */
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#define KN05_MB_INT_MT (1<<3) /* ??? */
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/*
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* Bits for the MB control & status register.
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* Set to 0x00bf8001 on my system by the ROM.
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*/
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#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */
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#define KN05_MB_CSR_F (1<<1) /* ??? */
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#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */
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#define KN05_MB_CSR_OD (1<<10) /* ??? */
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#define KN05_MB_CSR_CP (1<<11) /* ??? */
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#define KN05_MB_CSR_UNC (1<<12) /* ??? */
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#define KN05_MB_CSR_IM (1<<13) /* ??? */
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#define KN05_MB_CSR_NC (1<<14) /* ??? */
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#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
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#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */
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#define KN05_MB_CSR_FW (1<<21) /* ??? */
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#endif /* __ASM_MIPS_DEC_KN05_H */
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