115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
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/*
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* A collection of structures, addresses, and values associated with
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* the RPCG RPX-Classic board. Copied from the RPX-Lite stuff.
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*/
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#ifdef __KERNEL__
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#ifndef __MACH_RPX_DEFS
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#define __MACH_RPX_DEFS
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#ifndef __ASSEMBLY__
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/* A Board Information structure that is given to a program when
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* prom starts it up.
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*/
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typedef struct bd_info {
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unsigned int bi_memstart; /* Memory start address */
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unsigned int bi_memsize; /* Memory (end) size in bytes */
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unsigned int bi_intfreq; /* Internal Freq, in Hz */
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unsigned int bi_busfreq; /* Bus Freq, in Hz */
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unsigned char bi_enetaddr[6];
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unsigned int bi_baudrate;
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} bd_t;
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extern bd_t m8xx_board_info;
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/* Memory map is configured by the PROM startup.
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* We just map a few things we need. The CSR is actually 4 byte-wide
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* registers that can be accessed as 8-, 16-, or 32-bit values.
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*/
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#define PCI_ISA_IO_ADDR ((unsigned)0x80000000)
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#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024))
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#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000)
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#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024))
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#define RPX_CSR_ADDR ((uint)0xfa400000)
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#define RPX_CSR_SIZE ((uint)(4 * 1024))
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#define IMAP_ADDR ((uint)0xfa200000)
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#define IMAP_SIZE ((uint)(64 * 1024))
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#define PCI_CSR_ADDR ((uint)0x80000000)
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#define PCI_CSR_SIZE ((uint)(64 * 1024))
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#define PCMCIA_MEM_ADDR ((uint)0xe0000000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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#define PCMCIA_IO_ADDR ((uint)0xe4000000)
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#define PCMCIA_IO_SIZE ((uint)(4 * 1024))
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#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000)
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#define PCMCIA_ATTRB_SIZE ((uint)(4 * 1024))
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/* Things of interest in the CSR.
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*/
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#define BCSR0_ETHEN ((uint)0x80000000)
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#define BCSR0_ETHLPBK ((uint)0x40000000)
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#define BCSR0_COLTESTDIS ((uint)0x20000000)
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#define BCSR0_FULLDPLXDIS ((uint)0x10000000)
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#define BCSR0_ENFLSHSEL ((uint)0x04000000)
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#define BCSR0_FLASH_SEL ((uint)0x02000000)
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#define BCSR0_ENMONXCVR ((uint)0x01000000)
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#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) /* CLLF */
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#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) /* CLLF */
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#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) /* CLLF */
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#define BCSR1_IPB5SEL ((uint)0x00100000)
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#define BCSR1_PCVCTL4 ((uint)0x00080000)
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#define BCSR1_PCVCTL5 ((uint)0x00040000)
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#define BCSR1_PCVCTL6 ((uint)0x00020000)
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#define BCSR1_PCVCTL7 ((uint)0x00010000)
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#define BCSR2_EN232XCVR ((uint)0x00008000)
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#define BCSR2_QSPACESEL ((uint)0x00004000)
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#define BCSR2_FETHLEDMODE ((uint)0x00000800) /* CLLF */
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/* define IO_BASE for pcmcia, CLLF only */
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#if !defined(CONFIG_PCI)
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#define _IO_BASE 0x80000000
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#define _IO_BASE_SIZE 0x1000
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/* for pcmcia sandisk */
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#ifdef CONFIG_IDE
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# define MAX_HWIFS 1
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#endif
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#endif
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/* Interrupt level assignments.
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*/
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#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
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/* CPM Ethernet through SCCx.
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*
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* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use.
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*/
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#define PA_ENET_RXD ((ushort)0x0001)
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#define PA_ENET_TXD ((ushort)0x0002)
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#define PA_ENET_TCLK ((ushort)0x0200)
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#define PA_ENET_RCLK ((ushort)0x0800)
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#define PB_ENET_TENA ((uint)0x00001000)
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#define PC_ENET_CLSN ((ushort)0x0010)
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#define PC_ENET_RENA ((ushort)0x0020)
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/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
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* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x000000ff)
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#define SICR_ENET_CLKRT ((uint)0x0000003d)
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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#endif /* !__ASSEMBLY__ */
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#endif /* __MACH_RPX_DEFS */
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#endif /* __KERNEL__ */
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