95 lines
2.0 KiB
ArmAsm
95 lines
2.0 KiB
ArmAsm
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#include <linux/linkage.h>
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#include <asm/entry.h>
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#include <asm/page.h>
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#include <asm/contregs.h>
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#include <asm/sun3-head.h>
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PSL_HIGHIPL = 0x2700
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NBSG = 0x20000
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ICACHE_ONLY = 0x00000009
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CACHES_OFF = 0x00000008 | actually a clear and disable --m
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#define MAS_STACK INT_STACK
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ROOT_TABLE_SIZE = 128
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PAGESIZE = 8192
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SUN3_INVALID_PMEG = 255
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.globl bootup_user_stack
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.globl bootup_kernel_stack
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.globl pg0
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.globl swapper_pg_dir
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.globl kernel_pmd_table
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.globl availmem
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.global m68k_pgtable_cachemode
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.global kpt
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| todo: all these should be in bss!
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swapper_pg_dir: .skip 0x2000
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pg0: .skip 0x2000
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kernel_pmd_table: .skip 0x2000
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.globl kernel_pg_dir
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.equ kernel_pg_dir,kernel_pmd_table
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.section .head
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ENTRY(_stext)
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ENTRY(_start)
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/* Firstly, disable interrupts and set up function codes. */
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movew #PSL_HIGHIPL, %sr
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moveq #FC_CONTROL, %d0
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movec %d0, %sfc
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movec %d0, %dfc
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/* Make sure we're in context zero. */
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moveq #0, %d0
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movsb %d0, AC_CONTEXT
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/* map everything the bootloader left us into high memory, clean up the
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excess later */
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lea (AC_SEGMAP+0),%a0
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lea (AC_SEGMAP+KERNBASE),%a1
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1:
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movsb %a0@, %d1
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movsb %d1, %a1@
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cmpib #SUN3_INVALID_PMEG, %d1
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beq 2f
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addl #NBSG,%a0
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addl #NBSG,%a1
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jmp 1b
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2:
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/* Disable caches and jump to high code. */
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moveq #ICACHE_ONLY,%d0 | Cache disabled until we're ready to enable it
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movc %d0, %cacr | is this the right value? (yes --m)
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jmp 1f:l
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/* Following code executes at high addresses (0xE000xxx). */
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1: lea init_task,%curptr | get initial thread...
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lea init_thread_union+THREAD_SIZE,%sp | ...and its stack.
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/* Point MSP at an invalid page to trap if it's used. --m */
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movl #(PAGESIZE),%d0
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movc %d0,%msp
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moveq #-1,%d0
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movsb %d0,(AC_SEGMAP+0x0)
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jbsr sun3_init
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jbsr base_trap_init
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jbsr start_kernel
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trap #15
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.data
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.even
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kpt:
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.long 0
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availmem:
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.long 0
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| todo: remove next two. --m
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is_medusa:
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.long 0
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m68k_pgtable_cachemode:
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.long 0
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