From 0d444f9089357cf3076c73707b735c15ac59d4ac Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Sun, 25 Apr 2021 12:21:29 +0530 Subject: [PATCH] icc: dt-bindings: add endpoint IDs for interconnects for QCS405 Add master and slave ID constants for all Qualcomm Technologies, Inc. QCS405 interconnect providers which consumers can use to set bandwidth constraints and find paths in the NoC (Network-On-Chip) topology. Change-Id: I09685dbec2872cae8fc2d23ca94ccb35c3698848 Signed-off-by: Veera Vegivada --- .../dt-bindings/interconnect/qcom,qcs405.h | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,qcs405.h diff --git a/include/dt-bindings/interconnect/qcom,qcs405.h b/include/dt-bindings/interconnect/qcom,qcs405.h new file mode 100644 index 000000000000..2b3c35f2b0f3 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,qcs405.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS405_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS405_H + +#define MASTER_AMPSS_M0 0 +#define MASTER_GRAPHICS_3D 1 +#define MASTER_MDP_PORT0 2 +#define SNOC_BIMC_1_MAS 3 +#define MASTER_TCU_0 4 +#define MASTER_CRYPTO_CORE0 5 +#define MASTER_SPDM 6 +#define MASTER_BLSP_1 7 +#define MASTER_BLSP_2 8 +#define MASTER_XM_USB_HS1 9 +#define MASTER_CRVIRT_PCNOC 10 +#define MASTER_SDCC_1 11 +#define MASTER_SDCC_2 12 +#define SNOC_PCNOC_MAS 13 +#define MASTER_QPIC 14 +#define PCNOC_INT_0 15 +#define PCNOC_INT_2 16 +#define PCNOC_INT_3 17 +#define PCNOC_SLV_0 18 +#define PCNOC_SLV_1 19 +#define PCNOC_SLV_2 20 +#define PCNOC_SLV_3 21 +#define PCNOC_SLV_4 22 +#define PCNOC_SLV_6 23 +#define PCNOC_SLV_7 24 +#define PCNOC_SLV_8 25 +#define PCNOC_SLV_9 26 +#define MASTER_PCNOC_S_10 27 +#define MASTER_PCNOC_S_11 28 +#define MASTER_QDSS_BAM 29 +#define BIMC_SNOC_MAS 30 +#define PNOC_SNOC_MAS 31 +#define MASTER_QDSS_ETR 32 +#define MASTER_EMAC 33 +#define MASTER_PCIE 34 +#define MASTER_USB3 35 +#define SNOC_QDSS_INT 36 +#define SNOC_INT_0 37 +#define SNOC_INT_1 38 +#define SNOC_INT_2 39 +#define SLAVE_EBI_CH0 512 +#define BIMC_SNOC_SLV 513 +#define SLAVE_CRVIRT_PCNOC 514 +#define SLAVE_SPDM_WRAPPER 515 +#define SLAVE_PDM 516 +#define SLAVE_PRNG 517 +#define SLAVE_TCSR 518 +#define SLAVE_SNOC_CFG 519 +#define SLAVE_MESSAGE_RAM 520 +#define SLAVE_DISPLAY_CFG 521 +#define SLAVE_GRAPHICS_3D_CFG 522 +#define SLAVE_BLSP_1 523 +#define SLAVE_TLMM_NORTH 524 +#define SLAVE_PCIE_1 525 +#define SLAVE_EMAC 526 +#define SLAVE_BLSP_2 527 +#define SLAVE_TLMM_EAST 528 +#define SLAVE_TCU 529 +#define SLAVE_PMIC_ARB 530 +#define SLAVE_SDCC_1 531 +#define SLAVE_SDCC_2 532 +#define SLAVE_TLMM_SOUTH 533 +#define SLAVE_USB_HS 534 +#define SLAVE_USB3 535 +#define SLAVE_CRYPTO_0_CFG 536 +#define PCNOC_SNOC_SLV 537 +#define SLAVE_APPSS 538 +#define SLAVE_WCSS 539 +#define SNOC_BIMC_1_SLV 540 +#define SLAVE_OCIMEM 541 +#define SNOC_PCNOC_SLV 542 +#define SLAVE_QDSS_STM 543 +#define SLAVE_CATS_128 544 +#define SLAVE_OCMEM_64 545 +#define SLAVE_LPASS 546 + +#endif