qcacld-3.0: Add ini entry for wow pulse configuration

qcacld-2.0 to qcacld-3.0 propagation

Add ini entry to configure wow pulse repetition count
and wow pulse init level.

Change-Id: Ic23d2ae80f6f0adef9f35bfef5a59eb0220c70ae
CRs-Fixed: 2722997
This commit is contained in:
Li Feng 2020-05-27 09:59:18 +08:00 committed by nshrivas
parent 95ea7c675f
commit 0e6dc924e5
8 changed files with 116 additions and 8 deletions

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@ -111,6 +111,10 @@ static void wlan_pmo_wow_pulse_init_cfg(struct wlan_objmgr_psoc *psoc,
cfg_get(psoc, CFG_PMO_WOW_PULSE_HIGH);
psoc_cfg->wow_pulse_interval_low =
cfg_get(psoc, CFG_PMO_WOW_PULSE_LOW);
psoc_cfg->wow_pulse_repeat_count =
cfg_get(psoc, CFG_PMO_WOW_PULSE_REPEAT);
psoc_cfg->wow_pulse_init_state =
cfg_get(psoc, CFG_PMO_WOW_PULSE_INIT);
}
#else
static void wlan_pmo_wow_pulse_init_cfg(struct wlan_objmgr_psoc *psoc,

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@ -294,6 +294,8 @@ enum active_apf_mode {
* @wow_pulse_pin: GPIO pin of wow pulse feature
* @wow_pulse_interval_high: The interval of high level in the pulse
* @wow_pulse_interval_low: The interval of low level in the pulse
* @wow_pulse_repeat_count: Pulse repeat count
* @wow_pulse_init_state: Pulse init level
* @packet_filters_bitmap: Packet filter bitmap configuration
* @wow_data_inactivity_timeout: power save wow data inactivity timeout
* @ps_data_inactivity_timeout: Power save data inactivity timeout for non
@ -353,6 +355,8 @@ struct pmo_psoc_cfg {
uint8_t wow_pulse_pin;
uint16_t wow_pulse_interval_high;
uint16_t wow_pulse_interval_low;
uint32_t wow_pulse_repeat_count;
uint32_t wow_pulse_init_state;
#endif
#ifdef WLAN_FEATURE_PACKET_FILTERING
uint8_t packet_filters_bitmap;

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@ -1010,6 +1010,22 @@ uint16_t ucfg_pmo_get_wow_pulse_interval_high(struct wlan_objmgr_psoc *psoc);
* Return: wow pulse interval high configuration
*/
uint16_t ucfg_pmo_get_wow_pulse_interval_low(struct wlan_objmgr_psoc *psoc);
/**
* ucfg_pmo_get_wow_pulse_repeat_count() - to get wow pulse repeat count
* @psoc: objmgr psoc handle
*
* Return: wow pulse repeat count configuration
*/
uint32_t ucfg_pmo_get_wow_pulse_repeat_count(struct wlan_objmgr_psoc *psoc);
/**
* ucfg_pmo_get_wow_pulse_init_state() - to get wow pulse init state
* @psoc: objmgr psoc handle
*
* Return: wow pulse init state configuration
*/
uint32_t ucfg_pmo_get_wow_pulse_init_state(struct wlan_objmgr_psoc *psoc);
#else
static inline bool
ucfg_pmo_is_wow_pulse_enabled(struct wlan_objmgr_psoc *psoc)
@ -1028,6 +1044,18 @@ ucfg_pmo_get_wow_pulse_interval_high(struct wlan_objmgr_psoc *psoc)
{
return 0;
}
static inline uint32_t
ucfg_pmo_get_wow_pulse_repeat_count(struct wlan_objmgr_psoc *psoc)
{
return 0;
}
static inline uint32_t
ucfg_pmo_get_wow_pulse_init_state(struct wlan_objmgr_psoc *psoc)
{
return 0;
}
#endif
/**

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@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2018 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -101,11 +101,54 @@
CFG_VALUE_OR_DEFAULT, \
"Interval of high pulse")
/*
* <ini>
* gwow_pulse_repeat_count - wow pulse repetition count
* @Min: 1
* @Max: 0xffffffff
* @Default: 1
*
* The repeat count of wow pin wave.
* Level low to level high is one time, 0xffffffff means endless.
*
* Supported Feature: WOW pulse
*
* Usage: External
*
* </ini>
*/
#define CFG_PMO_WOW_PULSE_REPEAT CFG_INI_UINT("gwow_pulse_repeat_count", \
1, 0xffffffff, 1, \
CFG_VALUE_OR_DEFAULT, \
"Pulse repetition count")
/*
* <ini>
* gwow_pulse_init_state - wow pulse init level
* @Min: 0
* @Max: 1
* @Default: 0
*
* The init level of wow pin, 1 is high level, 0 is low level.
*
* Supported Feature: WOW pulse
*
* Usage: External
*
* </ini>
*/
#define CFG_PMO_WOW_PULSE_INIT CFG_INI_UINT("gwow_pulse_init_state", \
0, 1, 1, \
CFG_VALUE_OR_DEFAULT, \
"Pulse init level")
#define CFG_WOW_PULSE_ALL \
CFG(CFG_PMO_WOW_PULSE_ENABLE) \
CFG(CFG_PMO_WOW_PULSE_PIN) \
CFG(CFG_PMO_WOW_PULSE_LOW) \
CFG(CFG_PMO_WOW_PULSE_HIGH)
CFG(CFG_PMO_WOW_PULSE_HIGH) \
CFG(CFG_PMO_WOW_PULSE_REPEAT) \
CFG(CFG_PMO_WOW_PULSE_INIT)
#else
#define CFG_WOW_PULSE_ALL
#endif /* WLAN_FEATURE_WOW_PULSE */

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@ -592,6 +592,20 @@ uint16_t ucfg_pmo_get_wow_pulse_interval_low(struct wlan_objmgr_psoc *psoc)
return pmo_psoc_ctx->psoc_cfg.wow_pulse_interval_low;
}
uint32_t ucfg_pmo_get_wow_pulse_repeat_count(struct wlan_objmgr_psoc *psoc)
{
struct pmo_psoc_priv_obj *pmo_psoc_ctx = pmo_psoc_get_priv(psoc);
return pmo_psoc_ctx->psoc_cfg.wow_pulse_repeat_count;
}
uint32_t ucfg_pmo_get_wow_pulse_init_state(struct wlan_objmgr_psoc *psoc)
{
struct pmo_psoc_priv_obj *pmo_psoc_ctx = pmo_psoc_get_priv(psoc);
return pmo_psoc_ctx->psoc_cfg.wow_pulse_init_state;
}
#endif
bool ucfg_pmo_is_active_mode_offloaded(struct wlan_objmgr_psoc *psoc)

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@ -10093,17 +10093,27 @@ static int wlan_hdd_set_wow_pulse(struct hdd_context *hdd_ctx, bool enable)
wow_pulse_set_info.wow_pulse_interval_low =
ucfg_pmo_get_wow_pulse_interval_low(hdd_ctx->psoc);
wow_pulse_set_info.wow_pulse_repeat_count =
ucfg_pmo_get_wow_pulse_repeat_count(hdd_ctx->psoc);
wow_pulse_set_info.wow_pulse_init_state =
ucfg_pmo_get_wow_pulse_init_state(hdd_ctx->psoc);
} else {
wow_pulse_set_info.wow_pulse_enable = false;
wow_pulse_set_info.wow_pulse_pin = 0;
wow_pulse_set_info.wow_pulse_interval_low = 0;
wow_pulse_set_info.wow_pulse_interval_high = 0;
wow_pulse_set_info.wow_pulse_repeat_count = 0;
wow_pulse_set_info.wow_pulse_init_state = 0;
}
hdd_debug("enable %d pin %d low %d high %d",
hdd_debug("enable %d pin %d low %d high %d count %d init %d",
wow_pulse_set_info.wow_pulse_enable,
wow_pulse_set_info.wow_pulse_pin,
wow_pulse_set_info.wow_pulse_interval_low,
wow_pulse_set_info.wow_pulse_interval_high);
wow_pulse_set_info.wow_pulse_interval_high,
wow_pulse_set_info.wow_pulse_repeat_count,
wow_pulse_set_info.wow_pulse_init_state);
status = sme_set_wow_pulse(&wow_pulse_set_info);
if (QDF_STATUS_E_FAILURE == status) {

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@ -5166,6 +5166,8 @@ struct sme_sta_inactivity_timeout {
* @wow_pulse_pin: GPIO PIN for Pulse
* @wow_pulse_interval_low: Pulse interval low
* @wow_pulse_interval_high: Pulse interval high
* @wow_pulse_repeat_count: Pulse repeat count
* @wow_pulse_init_state: Pulse init level
*
* SME uses this structure to configure wow pulse info
* and send it to WMA
@ -5175,6 +5177,8 @@ struct wow_pulse_mode {
uint8_t wow_pulse_pin;
uint16_t wow_pulse_interval_high;
uint16_t wow_pulse_interval_low;
uint32_t wow_pulse_repeat_count;
uint32_t wow_pulse_init_state;
};

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@ -7468,7 +7468,8 @@ static QDF_STATUS wma_send_wow_pulse_cmd(tp_wma_handle wma_handle,
cmd->pin = wow_pulse_cmd->wow_pulse_pin;
cmd->interval_low = wow_pulse_cmd->wow_pulse_interval_low;
cmd->interval_high = wow_pulse_cmd->wow_pulse_interval_high;
cmd->repeat_cnt = WMI_WOW_PULSE_REPEAT_CNT;
cmd->repeat_cnt = wow_pulse_cmd->wow_pulse_repeat_count;
cmd->init_state = wow_pulse_cmd->wow_pulse_init_state;
if (wmi_unified_cmd_send(wma_handle->wmi_handle, buf, len,
WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID)) {