qcacld-3.0: Add ini entry for wow pulse configuration
qcacld-2.0 to qcacld-3.0 propagation Add ini entry to configure wow pulse repetition count and wow pulse init level. Change-Id: Ic23d2ae80f6f0adef9f35bfef5a59eb0220c70ae CRs-Fixed: 2722997
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@ -111,6 +111,10 @@ static void wlan_pmo_wow_pulse_init_cfg(struct wlan_objmgr_psoc *psoc,
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cfg_get(psoc, CFG_PMO_WOW_PULSE_HIGH);
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psoc_cfg->wow_pulse_interval_low =
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cfg_get(psoc, CFG_PMO_WOW_PULSE_LOW);
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psoc_cfg->wow_pulse_repeat_count =
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cfg_get(psoc, CFG_PMO_WOW_PULSE_REPEAT);
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psoc_cfg->wow_pulse_init_state =
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cfg_get(psoc, CFG_PMO_WOW_PULSE_INIT);
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}
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#else
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static void wlan_pmo_wow_pulse_init_cfg(struct wlan_objmgr_psoc *psoc,
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@ -294,6 +294,8 @@ enum active_apf_mode {
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* @wow_pulse_pin: GPIO pin of wow pulse feature
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* @wow_pulse_interval_high: The interval of high level in the pulse
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* @wow_pulse_interval_low: The interval of low level in the pulse
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* @wow_pulse_repeat_count: Pulse repeat count
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* @wow_pulse_init_state: Pulse init level
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* @packet_filters_bitmap: Packet filter bitmap configuration
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* @wow_data_inactivity_timeout: power save wow data inactivity timeout
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* @ps_data_inactivity_timeout: Power save data inactivity timeout for non
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@ -353,6 +355,8 @@ struct pmo_psoc_cfg {
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uint8_t wow_pulse_pin;
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uint16_t wow_pulse_interval_high;
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uint16_t wow_pulse_interval_low;
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uint32_t wow_pulse_repeat_count;
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uint32_t wow_pulse_init_state;
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#endif
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#ifdef WLAN_FEATURE_PACKET_FILTERING
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uint8_t packet_filters_bitmap;
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@ -1010,6 +1010,22 @@ uint16_t ucfg_pmo_get_wow_pulse_interval_high(struct wlan_objmgr_psoc *psoc);
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* Return: wow pulse interval high configuration
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*/
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uint16_t ucfg_pmo_get_wow_pulse_interval_low(struct wlan_objmgr_psoc *psoc);
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/**
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* ucfg_pmo_get_wow_pulse_repeat_count() - to get wow pulse repeat count
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* @psoc: objmgr psoc handle
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*
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* Return: wow pulse repeat count configuration
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*/
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uint32_t ucfg_pmo_get_wow_pulse_repeat_count(struct wlan_objmgr_psoc *psoc);
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/**
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* ucfg_pmo_get_wow_pulse_init_state() - to get wow pulse init state
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* @psoc: objmgr psoc handle
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*
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* Return: wow pulse init state configuration
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*/
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uint32_t ucfg_pmo_get_wow_pulse_init_state(struct wlan_objmgr_psoc *psoc);
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#else
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static inline bool
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ucfg_pmo_is_wow_pulse_enabled(struct wlan_objmgr_psoc *psoc)
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@ -1028,6 +1044,18 @@ ucfg_pmo_get_wow_pulse_interval_high(struct wlan_objmgr_psoc *psoc)
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{
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return 0;
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}
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static inline uint32_t
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ucfg_pmo_get_wow_pulse_repeat_count(struct wlan_objmgr_psoc *psoc)
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{
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return 0;
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}
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static inline uint32_t
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ucfg_pmo_get_wow_pulse_init_state(struct wlan_objmgr_psoc *psoc)
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{
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return 0;
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}
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#endif
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/**
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2018 The Linux Foundation. All rights reserved.
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* Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@ -101,11 +101,54 @@
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CFG_VALUE_OR_DEFAULT, \
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"Interval of high pulse")
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/*
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* <ini>
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* gwow_pulse_repeat_count - wow pulse repetition count
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* @Min: 1
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* @Max: 0xffffffff
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* @Default: 1
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*
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* The repeat count of wow pin wave.
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* Level low to level high is one time, 0xffffffff means endless.
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*
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* Supported Feature: WOW pulse
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_PMO_WOW_PULSE_REPEAT CFG_INI_UINT("gwow_pulse_repeat_count", \
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1, 0xffffffff, 1, \
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CFG_VALUE_OR_DEFAULT, \
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"Pulse repetition count")
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/*
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* <ini>
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* gwow_pulse_init_state - wow pulse init level
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* @Min: 0
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* @Max: 1
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* @Default: 0
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*
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* The init level of wow pin, 1 is high level, 0 is low level.
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*
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* Supported Feature: WOW pulse
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_PMO_WOW_PULSE_INIT CFG_INI_UINT("gwow_pulse_init_state", \
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0, 1, 1, \
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CFG_VALUE_OR_DEFAULT, \
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"Pulse init level")
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#define CFG_WOW_PULSE_ALL \
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CFG(CFG_PMO_WOW_PULSE_ENABLE) \
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CFG(CFG_PMO_WOW_PULSE_PIN) \
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CFG(CFG_PMO_WOW_PULSE_LOW) \
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CFG(CFG_PMO_WOW_PULSE_HIGH)
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CFG(CFG_PMO_WOW_PULSE_HIGH) \
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CFG(CFG_PMO_WOW_PULSE_REPEAT) \
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CFG(CFG_PMO_WOW_PULSE_INIT)
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#else
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#define CFG_WOW_PULSE_ALL
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#endif /* WLAN_FEATURE_WOW_PULSE */
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@ -592,6 +592,20 @@ uint16_t ucfg_pmo_get_wow_pulse_interval_low(struct wlan_objmgr_psoc *psoc)
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return pmo_psoc_ctx->psoc_cfg.wow_pulse_interval_low;
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}
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uint32_t ucfg_pmo_get_wow_pulse_repeat_count(struct wlan_objmgr_psoc *psoc)
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{
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struct pmo_psoc_priv_obj *pmo_psoc_ctx = pmo_psoc_get_priv(psoc);
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return pmo_psoc_ctx->psoc_cfg.wow_pulse_repeat_count;
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}
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uint32_t ucfg_pmo_get_wow_pulse_init_state(struct wlan_objmgr_psoc *psoc)
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{
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struct pmo_psoc_priv_obj *pmo_psoc_ctx = pmo_psoc_get_priv(psoc);
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return pmo_psoc_ctx->psoc_cfg.wow_pulse_init_state;
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}
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#endif
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bool ucfg_pmo_is_active_mode_offloaded(struct wlan_objmgr_psoc *psoc)
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@ -10093,17 +10093,27 @@ static int wlan_hdd_set_wow_pulse(struct hdd_context *hdd_ctx, bool enable)
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wow_pulse_set_info.wow_pulse_interval_low =
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ucfg_pmo_get_wow_pulse_interval_low(hdd_ctx->psoc);
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wow_pulse_set_info.wow_pulse_repeat_count =
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ucfg_pmo_get_wow_pulse_repeat_count(hdd_ctx->psoc);
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wow_pulse_set_info.wow_pulse_init_state =
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ucfg_pmo_get_wow_pulse_init_state(hdd_ctx->psoc);
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} else {
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wow_pulse_set_info.wow_pulse_enable = false;
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wow_pulse_set_info.wow_pulse_pin = 0;
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wow_pulse_set_info.wow_pulse_interval_low = 0;
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wow_pulse_set_info.wow_pulse_interval_high = 0;
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wow_pulse_set_info.wow_pulse_repeat_count = 0;
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wow_pulse_set_info.wow_pulse_init_state = 0;
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}
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hdd_debug("enable %d pin %d low %d high %d",
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hdd_debug("enable %d pin %d low %d high %d count %d init %d",
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wow_pulse_set_info.wow_pulse_enable,
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wow_pulse_set_info.wow_pulse_pin,
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wow_pulse_set_info.wow_pulse_interval_low,
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wow_pulse_set_info.wow_pulse_interval_high);
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wow_pulse_set_info.wow_pulse_interval_high,
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wow_pulse_set_info.wow_pulse_repeat_count,
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wow_pulse_set_info.wow_pulse_init_state);
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status = sme_set_wow_pulse(&wow_pulse_set_info);
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if (QDF_STATUS_E_FAILURE == status) {
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@ -5166,6 +5166,8 @@ struct sme_sta_inactivity_timeout {
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* @wow_pulse_pin: GPIO PIN for Pulse
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* @wow_pulse_interval_low: Pulse interval low
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* @wow_pulse_interval_high: Pulse interval high
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* @wow_pulse_repeat_count: Pulse repeat count
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* @wow_pulse_init_state: Pulse init level
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*
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* SME uses this structure to configure wow pulse info
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* and send it to WMA
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@ -5175,6 +5177,8 @@ struct wow_pulse_mode {
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uint8_t wow_pulse_pin;
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uint16_t wow_pulse_interval_high;
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uint16_t wow_pulse_interval_low;
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uint32_t wow_pulse_repeat_count;
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uint32_t wow_pulse_init_state;
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};
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@ -7468,7 +7468,8 @@ static QDF_STATUS wma_send_wow_pulse_cmd(tp_wma_handle wma_handle,
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cmd->pin = wow_pulse_cmd->wow_pulse_pin;
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cmd->interval_low = wow_pulse_cmd->wow_pulse_interval_low;
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cmd->interval_high = wow_pulse_cmd->wow_pulse_interval_high;
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cmd->repeat_cnt = WMI_WOW_PULSE_REPEAT_CNT;
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cmd->repeat_cnt = wow_pulse_cmd->wow_pulse_repeat_count;
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cmd->init_state = wow_pulse_cmd->wow_pulse_init_state;
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if (wmi_unified_cmd_send(wma_handle->wmi_handle, buf, len,
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WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID)) {
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