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drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition

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[ Upstream commit 049d919168458ac54e7fad27cd156a958b042d2f ]

When disabling a counter from ddr_perf_event_stop(), the counter value
is reset to 0 at the same time.

Preserve the counter value by performing a read-modify-write of the
PMU register and clearing only the enable bit.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Joakim Zhang 2020-02-25 20:56:43 +08:00 committed by Greg Kroah-Hartman
parent 0f6ae2cba3
commit 1002a094e0
1 changed files with 6 additions and 4 deletions
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10
drivers/perf/fsl_imx8_ddr_perf.c
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@ -327,9 +327,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
if (enable) { if (enable) {
/* /*
* must disable first, then enable again * cycle counter is special which should firstly write 0 then
* otherwise, cycle counter will not work * write 1 into CLEAR bit to clear it. Other counters only
* if previous state is enabled. * need write 0 into CLEAR bit and it turns out to be 1 by
* hardware. Below enable flow is harmless for all counters.
*/ */
writel(0, pmu->base + reg); writel(0, pmu->base + reg);
val = CNTL_EN | CNTL_CLEAR; val = CNTL_EN | CNTL_CLEAR;
@ -337,7 +338,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
writel(val, pmu->base + reg); writel(val, pmu->base + reg);
} else { } else {
/* Disable counter */ /* Disable counter */
writel(0, pmu->base + reg); val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
writel(val, pmu->base + reg);
} }
} }