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Merge "platform: msm: Migrate SCM calls in IPAv3"

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This commit is contained in:
qctecmdr 2019-11-21 10:51:40 -08:00 committed by Gerrit - the friendly Code Review server
commit 11b286fb73
6 changed files with 77 additions and 24 deletions
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36
drivers/firmware/qcom_scm-smc.c
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@ -806,6 +806,23 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
return ret ? : desc.res[0]; return ret ? : desc.res[0];
} }
int __qcom_scm_get_sec_dump_state(struct device *dev, u32 *dump_state)
{
int ret;
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_UTIL,
.cmd = QCOM_SCM_UTIL_GET_SEC_DUMP_STATE,
.owner = ARM_SMCCC_OWNER_SIP
};
ret = qcom_scm_call(dev, &desc);
if (dump_state)
*dump_state = desc.res[0];
return ret;
}
int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
unsigned int *val) unsigned int *val)
{ {
@ -972,6 +989,25 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
return ret; return ret;
} }
int __qcom_scm_mem_protect_region_id(struct device *dev, phys_addr_t paddr,
size_t size)
{
int ret;
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_MP,
.cmd = QCOM_SCM_MP_MEM_PROTECT_REGION_ID,
.owner = ARM_SMCCC_OWNER_SIP
};
desc.args[0] = paddr;
desc.args[1] = size;
desc.arginfo = QCOM_SCM_ARGS(2);
ret = qcom_scm_call(dev, &desc);
return ret;
}
int __qcom_scm_iommu_secure_map(struct device *dev, phys_addr_t sg_list_addr, int __qcom_scm_iommu_secure_map(struct device *dev, phys_addr_t sg_list_addr,
size_t num_sg, size_t sg_block_size, u64 sec_id, size_t num_sg, size_t sg_block_size, u64 sec_id,
int cbndx, unsigned long iova, size_t total_len) int cbndx, unsigned long iova, size_t total_len)

13
drivers/firmware/qcom_scm.c
View File

@ -322,6 +322,13 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = {
.deassert = qcom_scm_pas_reset_deassert, .deassert = qcom_scm_pas_reset_deassert,
}; };
int qcom_scm_get_sec_dump_state(u32 *dump_state)
{
return __qcom_scm_get_sec_dump_state(__scm->dev,
dump_state);
}
EXPORT_SYMBOL(qcom_scm_get_sec_dump_state);
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
{ {
return __qcom_scm_io_readl(__scm->dev, addr, val); return __qcom_scm_io_readl(__scm->dev, addr, val);
@ -365,6 +372,12 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
} }
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
int qcom_scm_mem_protect_region_id(phys_addr_t paddr, size_t size)
{
return __qcom_scm_mem_protect_region_id(__scm->dev, paddr, size);
}
EXPORT_SYMBOL(qcom_scm_mem_protect_region_id);
int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr, size_t num_sg, int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr, size_t num_sg,
size_t sg_block_size, u64 sec_id, int cbndx, size_t sg_block_size, u64 sec_id, int cbndx,
unsigned long iova, size_t total_len) unsigned long iova, size_t total_len)

7
drivers/firmware/qcom_scm.h
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@ -37,6 +37,10 @@ extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral); extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset); extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
#define QCOM_SCM_SVC_UTIL 0x03
#define QCOM_SCM_UTIL_GET_SEC_DUMP_STATE 0x10
extern int __qcom_scm_get_sec_dump_state(struct device *dev, u32 *dump_state);
#define QCOM_SCM_SVC_IO 0x05 #define QCOM_SCM_SVC_IO 0x05
#define QCOM_SCM_IO_READ 0x01 #define QCOM_SCM_IO_READ 0x01
#define QCOM_SCM_IO_WRITE 0x02 #define QCOM_SCM_IO_WRITE 0x02
@ -60,6 +64,7 @@ extern void __qcom_scm_mmu_sync(struct device *dev, bool sync);
#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02 #define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
#define QCOM_SCM_MP_MEM_PROTECT_REGION_ID 0x10
#define QCOM_SCM_MP_IOMMU_SECURE_MAP2_FLAT 0x12 #define QCOM_SCM_MP_IOMMU_SECURE_MAP2_FLAT 0x12
#define QCOM_SCM_MP_IOMMU_SECURE_UNMAP2_FLAT 0x13 #define QCOM_SCM_MP_IOMMU_SECURE_UNMAP2_FLAT 0x13
#define QCOM_SCM_MP_ASSIGN 0x16 #define QCOM_SCM_MP_ASSIGN 0x16
@ -69,6 +74,8 @@ extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
size_t *size); size_t *size);
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
u32 size, u32 spare); u32 size, u32 spare);
extern int __qcom_scm_mem_protect_region_id(struct device *dev,
phys_addr_t paddr, size_t size);
extern int __qcom_scm_iommu_secure_map(struct device *dev, extern int __qcom_scm_iommu_secure_map(struct device *dev,
phys_addr_t sg_list_addr, size_t num_sg, phys_addr_t sg_list_addr, size_t num_sg,
size_t sg_block_size, u64 sec_id, int cbndx, size_t sg_block_size, u64 sec_id, int cbndx,

38
drivers/platform/msm/ipa/ipa_v3/ipa.c
View File

@ -29,7 +29,7 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <soc/qcom/subsystem_restart.h> #include <soc/qcom/subsystem_restart.h>
#include <linux/soc/qcom/smem.h> #include <linux/soc/qcom/smem.h>
#include <soc/qcom/scm.h> #include <linux/qcom_scm.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <linux/soc/qcom/smem_state.h> #include <linux/soc/qcom/smem_state.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
@ -91,7 +91,6 @@ struct ipa_ioc_nat_ipv6ct_table_alloc32 {
#endif /* #ifdef CONFIG_COMPAT */ #endif /* #ifdef CONFIG_COMPAT */
#define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311 #define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311
#define TZ_MEM_PROTECT_REGION_ID 0x10
struct tz_smmu_ipa_protect_region_iovec_s { struct tz_smmu_ipa_protect_region_iovec_s {
u64 input_addr; u64 input_addr;
@ -6272,10 +6271,10 @@ static ssize_t ipa3_write(struct file *file, const char __user *buf,
*/ */
int ipa3_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs) int ipa3_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs)
{ {
int i, size, ret; int i, ret;
compat_size_t size;
struct tz_smmu_ipa_protect_region_iovec_s *ipa_tz_unlock_vec; struct tz_smmu_ipa_protect_region_iovec_s *ipa_tz_unlock_vec;
struct tz_smmu_ipa_protect_region_s cmd_buf; struct tz_smmu_ipa_protect_region_s cmd_buf;
struct scm_desc desc = {0};
if (reg_info == NULL || num_regs == 0) { if (reg_info == NULL || num_regs == 0) {
IPAERR("Bad parameters\n"); IPAERR("Bad parameters\n");
@ -6300,17 +6299,15 @@ int ipa3_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs)
cmd_buf.iovec_buf = virt_to_phys((void *)ipa_tz_unlock_vec); cmd_buf.iovec_buf = virt_to_phys((void *)ipa_tz_unlock_vec);
cmd_buf.size_bytes = size; cmd_buf.size_bytes = size;
desc.args[0] = virt_to_phys((void *)ipa_tz_unlock_vec); ret = qcom_scm_mem_protect_region_id(
desc.args[1] = size; virt_to_phys((void *)ipa_tz_unlock_vec),
desc.arginfo = SCM_ARGS(2); size);
ret = scm_call2(SCM_SIP_FNID(SCM_SVC_MP,
TZ_MEM_PROTECT_REGION_ID), &desc);
if (ret) { if (ret) {
IPAERR("scm call SCM_SVC_MP failed: %d\n", ret); IPAERR("scm call SCM_SVC_MP failed: %d\n", ret);
kfree(ipa_tz_unlock_vec); kfree(ipa_tz_unlock_vec);
return -EFAULT; return -EFAULT;
} }
kfree(ipa_tz_unlock_vec); kfree(ipa_tz_unlock_vec);
return 0; return 0;
} }
@ -6368,24 +6365,19 @@ static int ipa3_alloc_pkt_init(void)
* Returns true in secure dump allowed. * Returns true in secure dump allowed.
* Return false when secure dump not allowed. * Return false when secure dump not allowed.
*/ */
#define TZ_UTIL_GET_SEC_DUMP_STATE 0x10
static bool ipa_is_mem_dump_allowed(void) static bool ipa_is_mem_dump_allowed(void)
{ {
struct scm_desc desc = {0}; int ret;
int ret = 0; u32 dump_state;
desc.args[0] = 0; ret = qcom_scm_get_sec_dump_state(&dump_state);
desc.arginfo = 0;
ret = scm_call2(
SCM_SIP_FNID(SCM_SVC_UTIL, TZ_UTIL_GET_SEC_DUMP_STATE),
&desc);
if (ret) { if (ret) {
IPAERR("SCM DUMP_STATE call failed\n"); IPAERR("SCM DUMP_STATE call failed\n");
return false; return false;
} }
return (desc.ret[0] == 1); return (dump_state == 1);
} }
static int ipa3_lan_poll(struct napi_struct *napi, int budget) static int ipa3_lan_poll(struct napi_struct *napi, int budget)

1
drivers/platform/msm/ipa/ipa_v3/ipa_i.h
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@ -426,7 +426,6 @@ enum {
#endif /* #ifdef CONFIG_COMPAT */ #endif /* #ifdef CONFIG_COMPAT */
#define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311 #define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311
#define TZ_MEM_PROTECT_REGION_ID 0x10
#define MBOX_TOUT_MS 100 #define MBOX_TOUT_MS 100

6
include/linux/qcom_scm.h
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@ -47,6 +47,7 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
phys_addr_t size); phys_addr_t size);
extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
extern int qcom_scm_pas_shutdown(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral);
extern int qcom_scm_get_sec_dump_state(u32 *dump_state);
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
extern int qcom_scm_get_jtag_etm_feat_id(u64 *version); extern int qcom_scm_get_jtag_etm_feat_id(u64 *version);
@ -54,6 +55,7 @@ extern void qcom_scm_mmu_sync(bool sync);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
extern int qcom_scm_mem_protect_region_id(phys_addr_t paddr, size_t size);
extern int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr, size_t num_sg, extern int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr, size_t num_sg,
size_t sg_block_size, u64 sec_id, int cbndx, size_t sg_block_size, u64 sec_id, int cbndx,
unsigned long iova, size_t total_len); unsigned long iova, size_t total_len);
@ -91,6 +93,8 @@ static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
static inline int qcom_scm_pas_auth_and_reset(u32 peripheral) static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
{ return -ENODEV; } { return -ENODEV; }
static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; } static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
static inline int qcom_scm_get_sec_dump_state(u32 *dump_state)
{return -ENODEV; }
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
{ return -ENODEV; } { return -ENODEV; }
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
@ -104,6 +108,8 @@ static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
{ return -ENODEV; } { return -ENODEV; }
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
{ return -ENODEV; } { return -ENODEV; }
static inline int qcom_scm_mem_protect_region_id(phys_addr_t paddr, size_t size)
{ return -ENODEV; }
static inline int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr, static inline int qcom_scm_iommu_secure_map(phys_addr_t sg_list_addr,
size_t num_sg, size_t sg_block_size, u64 sec_id, int cbndx, size_t num_sg, size_t sg_block_size, u64 sec_id, int cbndx,
unsigned long iova, size_t total_len) { return -ENODEV; } unsigned long iova, size_t total_len) { return -ENODEV; }