From 11c9fc4e9207b745f0d6d7e55f1d9801ac61e442 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Fri, 12 Apr 2019 11:41:56 -0700 Subject: [PATCH] disp: avoid encoder-connector checks with cont-splash When continuous splash is enabled, connector states are not properly updated with the encoder associated with it. This is by design, so avoid all making such request there by avoiding unnecessary errors during the bootup. Fix a handful of warnings in the PLL definition files Change-Id: I7f08c5ff80ea2a2bfb4b19f2ea13c8f9cbb833e8 Signed-off-by: Narendra Muppalla --- msm/sde/sde_crtc.c | 5 +++-- pll/dp_pll_7nm_util.c | 2 +- pll/hdmi_pll_28lpm.c | 8 ++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/msm/sde/sde_crtc.c b/msm/sde/sde_crtc.c index 93a1f0b6cf8db..21e6698b5b169 100644 --- a/msm/sde/sde_crtc.c +++ b/msm/sde/sde_crtc.c @@ -2288,7 +2288,8 @@ u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc) } drm_for_each_encoder(encoder, crtc->dev) - if (encoder->crtc == crtc) + if ((encoder->crtc == crtc) + && !sde_encoder_in_cont_splash(encoder)) return sde_encoder_get_fps(encoder); return 0; @@ -3341,7 +3342,7 @@ static void sde_crtc_destroy_state(struct drm_crtc *crtc, SDE_DEBUG("crtc%d\n", crtc->base.id); - if (sde_kms && enc) + if (sde_kms && enc && !sde_encoder_in_cont_splash(enc)) sde_rm_release(&sde_kms->rm, enc, true); __drm_atomic_helper_crtc_destroy_state(state); diff --git a/pll/dp_pll_7nm_util.c b/pll/dp_pll_7nm_util.c index d3171253e9929..5c565c8599a7b 100644 --- a/pll/dp_pll_7nm_util.c +++ b/pll/dp_pll_7nm_util.c @@ -694,7 +694,7 @@ unsigned long dp_vco_recalc_rate_7nm(struct clk_hw *hw, vco_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000; } - pr_debug("hsclk: sel=0x%x, div=0x%x; lclk: sel=%lu, div=%lu, rate=%lu\n", + pr_debug("hsclk: sel=0x%x, div=0x%x; lclk: sel=%u, div=%u, rate=%lu\n", hsclk_sel, hsclk_div, link_clk_divsel, link_clk_div, vco_rate); mdss_pll_resource_enable(dp_res, false); diff --git a/pll/hdmi_pll_28lpm.c b/pll/hdmi_pll_28lpm.c index 790d7e655e834..a0fba39c2c236 100644 --- a/pll/hdmi_pll_28lpm.c +++ b/pll/hdmi_pll_28lpm.c @@ -276,8 +276,8 @@ static void hdmi_phy_pll_calculator_28lpm(unsigned long vco_rate, do_div(sdm_cfg2, int_ref_clk_freq); pr_debug("lf_cfg0 = 0x%x lf_cfg1 = 0x%x\n", lf_cfg0, lf_cfg1); - pr_debug("vco_cfg0 = 0x%x vco_cfg4 = 0x%x\n", vco_cfg0, vco_cfg4); - pr_debug("sdm_cfg0 = 0x%x sdm_cfg1 = 0x%x sdm_cfg2 = 0x%x\n", + pr_debug("vco_cfg0 = 0x%llx vco_cfg4 = 0x%llx\n", vco_cfg0, vco_cfg4); + pr_debug("sdm_cfg0 = 0x%llx sdm_cfg1 = 0x%llx sdm_cfg2 = 0x%llx\n", sdm_cfg0, sdm_cfg1, sdm_cfg2); refclk_cfg = MDSS_PLL_REG_R(pll_base, HDMI_PHY_PLL_REFCLK_CFG); @@ -500,7 +500,7 @@ unsigned long hdmi_vco_recalc_rate_28lpm(struct clk_hw *hw, if (hdmi_pll_res->vco_current_rate) { vco_rate = (unsigned long)hdmi_pll_res->vco_current_rate; - pr_debug("vco_rate=%ld\n", vco_rate); + pr_debug("vco_rate=%lld\n", vco_rate); return vco_rate; } @@ -521,7 +521,7 @@ unsigned long hdmi_vco_recalc_rate_28lpm(struct clk_hw *hw, mdss_pll_resource_enable(hdmi_pll_res, false); } - pr_debug("vco_rate = %ld\n", vco_rate); + pr_debug("vco_rate = %lld\n", vco_rate); return (unsigned long)vco_rate; }