msm: pcie: Dump PCIe registers for hang event
Dump limited set of pcie PARF, DBI and PHY registers for hang event. Change-Id: I626bb25abac19a9194669532cc8bc77dbfad119d Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
This commit is contained in:
Vivek Pernamitta
parent
f64d2bf563
commit
122c22e618
@ -75,6 +75,13 @@
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#define PCIE20_PARF_BDF_TO_SID_CFG (0x2C00)
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#define PCIE20_PARF_L1SUB_AHB_CLK_MAX_TIMER (0x180)
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#define PCIE20_PARF_DEBUG_INT_EN (0x190)
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#define PCIE20_PARF_PM_STTS_1 (0x28)
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#define PCIE20_PARF_INT_ALL_2_STATUS (0x500)
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#define PCIE20_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS (0x4D0)
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#define PCIE20_PARF_L1SS_SLEEP_MODE_HANDLER_CFG (0x4D4)
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#define PCIE20_PARF_CORE_ERRORS (0x3C0)
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#define PCIE20_LINK_DOWN_AXI_ECAM_BLOCK_STATUS (0x630)
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#define PCIE20_PARF_STATUS (0x230)
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#define PCIE20_PARF_CLKREQ_OVERRIDE (0x2b0)
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#define PCIE20_PARF_CLKREQ_IN_VALUE (BIT(3))
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@ -131,6 +138,12 @@
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#define PCIE20_AER_ROOT_ERR_STATUS_REG (0x130)
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#define PCIE20_AER_ERR_SRC_ID_REG (0x134)
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#define PCIE20_L1SUB_CONTROL1_REG (0x204)
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#define PCIE20_TX_P_FC_CREDIT_STATUS_OFF (0x730)
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#define PCIE20_TX_NP_FC_CREDIT_STATUS_OFF (0x734)
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#define PCIE20_TX_CPL_FC_CREDIT_STATUS_OFF (0x738)
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#define PCIE20_QUEUE_STATUS_OFF (0x73C)
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#define RD (0)
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#define WR (1)
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#define MSM_PCIE_ERROR (-1)
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@ -189,6 +202,56 @@
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#define ICC_AVG_BW (500)
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#define ICC_PEAK_BW (800)
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/* PCIE PHY status registers offset */
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#define QSERDES_COM_SYSCLK_DET_COMP_STATUS (0x68)
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#define GEN3X1_QSERDES_COM_CMN_STATUS (0x140)
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#define QSERDES_COM_RESET_SM_STATUS (0x144)
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#define QSERDES_COM_RESTRIM_CODE_STATUS (0x148)
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#define QSERDES_COM_PLLCAL_CODE1_STATUS (0x14C)
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#define QSERDES_COM_PLLCAL_CODE2_STATUS (0x150)
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#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS (0x160)
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#define QSERDES_COM_C_READY_STATUS (0x178)
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#define QSERDES_COM_MODE_OPERATION_STATUS (0x1C4)
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#define QSERDES_TX_BIST_STATUS (0xED0)
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#define QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 (0xEDC)
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#define QSERDES_TX_IDAC_STATUS_I (0xF34)
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#define QSERDES_TX_IDAC_STATUS_IBAR (0xF38)
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#define QSERDES_TX_IDAC_STATUS_Q (0xF3C)
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#define QSERDES_TX_IDAC_STATUS_QBAR (0xF40)
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#define QSERDES_TX_IDAC_STATUS_A (0xf44)
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#define QSERDES_TX_IDAC_STATUS_ABAR (0xF48)
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#define QSERDES_TX_IDAC_STATUS_SM_ON (0xF4C)
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#define QSERDES_TX_IDAC_STATUS_CAL_DONE (0xF50)
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#define QSERDES_TX_IDAC_STATUS_SIGNERROR (0xf54)
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#define QSERDES_TX_DCC_CAL_STATUS (0xF58)
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#define QSERDES_TX_DCC_READ_CODE_STATUS (0xF5C)
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#define QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 (0x11E8)
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#define PCIE_USB3_UNI_PCS_PCS_STATUS1 (0x214)
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#define PCIE_USB3_UNI_PCS_PCS_STATUS2 (0x218)
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#define PCIE_USB3_UNI_PCS_PCS_STATUS3 (0x21C)
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#define PCIE_USB3_UNI_PCS_PCS_STATUS4 (0x220)
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#define PCIE_USB3_UNI_PCS_PCS_STATUS5 (0x224)
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#define PCIE_USB3_UNI_PCS_PCS_STATUS6 (0x228)
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#define PCIE_USB3_UNI_PCS_PCS_STATUS7 (0x22C)
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#define PCIE_USB3_UNI_PCS_DEBUG_BUS_0_STATUS (0x230)
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#define PCIE_USB3_UNI_PCS_DEBUG_BUS_1_STATUS (0x234)
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#define PCIE_USB3_UNI_PCS_DEBUG_BUS_2_STATUS (0x238)
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#define PCIE_USB3_UNI_PCS_DEBUG_BUS_3_STATUS (0x23C)
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#define PCIE_USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS (0x600)
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#define PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS (0x604)
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#define PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS1 (0x800)
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#define PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS2 (0x804)
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#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS1 (0xA00)
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#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS2 (0xA04)
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#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR (0xA08)
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#define PCIE_USB3_UNI_PCS_LN_PCS_STATUS3 (0xA0C)
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#define PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS (0xA10)
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#define PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS (0xA14)
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#define PCIE_USB3_UNI_PCS_LN_BIST_CHK_STATUS (0xA18)
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#define PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS (0xC20)
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#define PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS (0x1204)
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#define PCIE_USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS (0x1210)
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/* Each tick is 19.2 MHz */
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#define L1SS_TIMEOUT_US_TO_TICKS(x) (x * 192 / 10)
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#define L1SS_TIMEOUT_US (100000)
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@ -1002,6 +1065,117 @@ static const struct msm_pcie_irq_info_t msm_pcie_irq_info[MSM_PCIE_MAX_IRQ] = {
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{"int_global_int", 0}
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};
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#define MSM_PCIE_PARF_REG_DUMP (11)
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#define MSM_PCIE_DBI_REG_DUMP (8)
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#define MSM_PCIE_PHY_REG_DUMP (48)
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struct msm_pcie_reg_dump_t {
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char *name;
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u32 offset;
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};
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static struct msm_pcie_reg_dump_t parf_reg_dump[MSM_PCIE_PARF_REG_DUMP + 1] = {
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{"PARF_LTSSM", PCIE20_PARF_LTSSM},
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{"PARF_PM_STTS", PCIE20_PARF_PM_STTS},
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{"PARF_PM_STTS_1", PCIE20_PARF_PM_STTS_1},
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{"PCIE_INT_ALL_STATUS", PCIE20_PARF_INT_ALL_STATUS},
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{"PCIE_INT_ALL_2_STATUS", PCIE20_PARF_INT_ALL_2_STATUS},
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{"L1SS_SLEEP_MODE_HANDLER_STATUS",
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PCIE20_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS},
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{"L1SS_SLEEP_MODE_HANDLER_CFG",
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PCIE20_PARF_L1SS_SLEEP_MODE_HANDLER_CFG},
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{"PCIE_PARF_CORE_ERRORS", PCIE20_PARF_CORE_ERRORS},
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{"LINK_DOWN_AXI_ECAM_BLOCK_STATUS",
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PCIE20_LINK_DOWN_AXI_ECAM_BLOCK_STATUS},
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{"PCIE_STATUS", PCIE20_PARF_STATUS},
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{"PARF_SYS_CTRL", PCIE20_PARF_SYS_CTRL},
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{NULL, 0}
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};
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static struct msm_pcie_reg_dump_t dbi_reg_dump[MSM_PCIE_DBI_REG_DUMP + 1] = {
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{"UNCORR_ERR_STATUS_OFF", PCIE20_AER_UNCORR_ERR_STATUS_REG},
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{"CORR_ERR_STATUS_OFF", PCIE20_AER_CORR_ERR_STATUS_REG},
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{"LINK_CONTROL_LINK_STATUS_REG", PCIE20_CAP_LINKCTRLSTATUS},
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{"L1SUB_CONTROL1_REG", PCIE20_L1SUB_CONTROL1_REG},
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{"TX_P_FC_CREDIT_STATUS_OFF", PCIE20_TX_P_FC_CREDIT_STATUS_OFF},
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{"TX_NP_FC_CREDIT_STATUS_OFF", PCIE20_TX_NP_FC_CREDIT_STATUS_OFF},
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{"TX_CPL_FC_CREDIT_STATUS_OFF", PCIE20_TX_CPL_FC_CREDIT_STATUS_OFF},
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{"QUEUE_STATUS_OFF", PCIE20_QUEUE_STATUS_OFF},
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{NULL, 0}
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};
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static struct msm_pcie_reg_dump_t phy_reg_dump[MSM_PCIE_PHY_REG_DUMP + 1] = {
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{"QSERDES_COM_SYSCLK_DET_COMP_STATUS",
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QSERDES_COM_SYSCLK_DET_COMP_STATUS},
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{"GEN3X1_QSERDES_COM_CMN_STATUS", GEN3X1_QSERDES_COM_CMN_STATUS},
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{"QSERDES_COM_RESET_SM_STATUS", QSERDES_COM_RESET_SM_STATUS},
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{"QSERDES_COM_RESTRIM_CODE_STATUS", QSERDES_COM_RESTRIM_CODE_STATUS},
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{"QSERDES_COM_PLLCAL_CODE1_STATUS", QSERDES_COM_PLLCAL_CODE1_STATUS},
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{"QSERDES_COM_PLLCAL_CODE2_STATUS", QSERDES_COM_PLLCAL_CODE2_STATUS},
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{"QSERDES_COM_INTEGLOOP_BINCODE_STATUS",
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QSERDES_COM_INTEGLOOP_BINCODE_STATUS},
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{"QSERDES_COM_C_READY_STATUS", QSERDES_COM_C_READY_STATUS},
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{"QSERDES_COM_MODE_OPERATION_STATUS",
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QSERDES_COM_MODE_OPERATION_STATUS},
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{"QSERDES_TX_BIST_STATUS", QSERDES_TX_BIST_STATUS},
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{"QSERDES_TX_ALOG_OBSV_BUS_STATUS_1",
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QSERDES_TX_ALOG_OBSV_BUS_STATUS_1},
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{"QSERDES_TX_IDAC_STATUS_I", QSERDES_TX_IDAC_STATUS_I},
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{"QSERDES_TX_IDAC_STATUS_IBAR", QSERDES_TX_IDAC_STATUS_IBAR},
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{"QSERDES_TX_IDAC_STATUS_Q", QSERDES_TX_IDAC_STATUS_Q},
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{"QSERDES_TX_IDAC_STATUS_QBAR", QSERDES_TX_IDAC_STATUS_QBAR},
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{"QSERDES_TX_IDAC_STATUS_A", QSERDES_TX_IDAC_STATUS_A},
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{"QSERDES_TX_IDAC_STATUS_ABAR", QSERDES_TX_IDAC_STATUS_ABAR},
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{"QSERDES_TX_IDAC_STATUS_SM_ON", QSERDES_TX_IDAC_STATUS_SM_ON},
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{"QSERDES_TX_IDAC_STATUS_CAL_DONE", QSERDES_TX_IDAC_STATUS_CAL_DONE},
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{"QSERDES_TX_IDAC_STATUS_SIGNERROR", QSERDES_TX_IDAC_STATUS_SIGNERROR},
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{"QSERDES_TX_DCC_CAL_STATUS", QSERDES_TX_DCC_CAL_STATUS},
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{"QSERDES_TX_DCC_READ_CODE_STATUS", QSERDES_TX_DCC_READ_CODE_STATUS},
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{"QSERDES_RX_ALOG_OBSV_BUS_STATUS_1",
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QSERDES_RX_ALOG_OBSV_BUS_STATUS_1},
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{"PCIE_USB3_UNI_PCS_PCS_STATUS1", PCIE_USB3_UNI_PCS_PCS_STATUS1},
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{"PCIE_USB3_UNI_PCS_PCS_STATUS2", PCIE_USB3_UNI_PCS_PCS_STATUS2},
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{"PCIE_USB3_UNI_PCS_PCS_STATUS3", PCIE_USB3_UNI_PCS_PCS_STATUS3},
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{"PCIE_USB3_UNI_PCS_PCS_STATUS4", PCIE_USB3_UNI_PCS_PCS_STATUS4},
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{"PCIE_USB3_UNI_PCS_PCS_STATUS5", PCIE_USB3_UNI_PCS_PCS_STATUS5},
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{"PCIE_USB3_UNI_PCS_PCS_STATUS6", PCIE_USB3_UNI_PCS_PCS_STATUS6},
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{"PCIE_USB3_UNI_PCS_PCS_STATUS7", PCIE_USB3_UNI_PCS_PCS_STATUS7},
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{"PCIE_USB3_UNI_PCS_DEBUG_BUS_0_STATUS",
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PCIE_USB3_UNI_PCS_DEBUG_BUS_0_STATUS},
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{"PCIE_USB3_UNI_PCS_DEBUG_BUS_1_STATUS",
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PCIE_USB3_UNI_PCS_DEBUG_BUS_1_STATUS},
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{"PCIE_USB3_UNI_PCS_DEBUG_BUS_2_STATUS",
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PCIE_USB3_UNI_PCS_DEBUG_BUS_2_STATUS},
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{"PCIE_USB3_UNI_PCS_DEBUG_BUS_3_STATUS",
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PCIE_USB3_UNI_PCS_DEBUG_BUS_3_STATUS},
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{"PCIE_USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS",
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PCIE_USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS},
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{"PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS",
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PCIE_USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS},
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{"PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS1",
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PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS1},
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{"PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS2",
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PCIE_USB3_UNI_PCS_INTGEN_INTGEN_STATUS2},
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{"PCIE_USB3_UNI_PCS_LN_PCS_STATUS1", PCIE_USB3_UNI_PCS_LN_PCS_STATUS1},
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{"PCIE_USB3_UNI_PCS_LN_PCS_STATUS2", PCIE_USB3_UNI_PCS_LN_PCS_STATUS2},
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{"PCIE_USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR",
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PCIE_USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR},
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{"PCIE_USB3_UNI_PCS_LN_PCS_STATUS3", PCIE_USB3_UNI_PCS_LN_PCS_STATUS3},
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{"PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS",
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PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS},
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{"PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS",
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PCIE_USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS},
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{"PCIE_USB3_UNI_PCS_LN_BIST_CHK_STATUS",
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PCIE_USB3_UNI_PCS_LN_BIST_CHK_STATUS},
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{"PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS",
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PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS},
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{"PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS",
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PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS},
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{"PCIE_USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS",
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PCIE_USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS},
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{NULL, 0}
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};
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static int msm_pcie_drv_send_rpmsg(struct msm_pcie_dev_t *pcie_dev,
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struct msm_pcie_drv_msg *msg);
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static void msm_pcie_config_sid(struct msm_pcie_dev_t *dev);
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@ -1019,6 +1193,83 @@ static void msm_pcie_check_l1ss_support_all(struct msm_pcie_dev_t *dev);
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static void msm_pcie_config_link_pm(struct msm_pcie_dev_t *dev, bool enable);
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static u32 msm_pcie_reg_copy(struct msm_pcie_dev_t *pcie_dev,
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u8 *buf, u32 size, void __iomem *base,
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struct msm_pcie_reg_dump_t *reg_list,
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u8 reg_len)
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{
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u32 ret = 0, val, i;
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PCIE_DUMP(pcie_dev, "RC%d buf=0x%x size=%u, reg_len=%u\n",
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pcie_dev->rc_idx, buf, size, reg_len);
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for (i = 0; (reg_list->name) && (i + reg_len <= size);
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i += reg_len) {
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val = readl_relaxed(base + reg_list->offset);
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memcpy(buf, &val, reg_len);
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reg_list++;
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buf += reg_len;
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ret += reg_len;
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}
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return ret;
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}
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int msm_pcie_reg_dump(struct pci_dev *pci_dev, u8 *buff, u32 len)
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{
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struct pci_dev *root_pci_dev;
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struct msm_pcie_dev_t *pcie_dev;
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u32 offset = 0;
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if (!pci_dev)
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return -EINVAL;
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root_pci_dev = pci_find_pcie_root_port(pci_dev);
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if (!root_pci_dev)
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return -ENODEV;
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pcie_dev = PCIE_BUS_PRIV_DATA(root_pci_dev->bus);
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if (!pcie_dev) {
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pr_err("PCIe: did not find RC for pci endpoint device.\n");
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return -ENODEV;
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}
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PCIE_DUMP(pcie_dev, "RC%d hang event dump buff=0x%x len=%u\n",
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pcie_dev->rc_idx, buff, len);
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offset = msm_pcie_reg_copy(pcie_dev, buff, len,
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pcie_dev->parf, parf_reg_dump, 4);
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buff += offset;
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len -= offset;
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/* check PHY status before dumping DBI registers */
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if (!(readl_relaxed(pcie_dev->phy + pcie_dev->phy_status_offset) &
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BIT(pcie_dev->phy_status_bit))) {
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PCIE_DUMP(pcie_dev, "RC%d Dump DBI registers\n",
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pcie_dev->rc_idx);
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offset = msm_pcie_reg_copy(pcie_dev, buff, len,
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pcie_dev->dm_core, dbi_reg_dump, 4);
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} else {
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/* PHY status bit is set to 1 so dump 0's in dbi buffer space */
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PCIE_DUMP(pcie_dev, "RC%d PHY is off, skip DBI\n",
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pcie_dev->rc_idx);
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memset(buff, 0, MSM_PCIE_DBI_REG_DUMP * 4);
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offset = MSM_PCIE_DBI_REG_DUMP * 4;
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}
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buff += offset;
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len -= offset;
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offset = msm_pcie_reg_copy(pcie_dev, buff, len,
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pcie_dev->phy, phy_reg_dump, 1);
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PCIE_DUMP(pcie_dev, "RC%d hang event Exit\n", pcie_dev->rc_idx);
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return 0;
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}
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EXPORT_SYMBOL(msm_pcie_reg_dump);
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static void msm_pcie_write_reg(void __iomem *base, u32 offset, u32 value)
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{
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writel_relaxed(value, base + offset);
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@ -214,6 +214,17 @@ int msm_pcie_shadow_control(struct pci_dev *dev, bool enable);
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int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base,
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u32 offset, u32 mask, u32 value);
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/*
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* msm_pcie_reg_dump - dump pcie regsters for debug
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* @pci_dev: pci device structure
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* @buffer: destination buffer address
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* @len: length of buffer
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*
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* This functions dumps PCIE registers for debug. Sould be used when
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* link is already enabled
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*/
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int msm_pcie_reg_dump(struct pci_dev *pci_dev, u8 *buff, u32 len);
|
||||
|
||||
#else /* !CONFIG_PCI_MSM */
|
||||
static inline int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr,
|
||||
void *user, void *data, u32 options)
|
||||
@ -270,6 +281,11 @@ static inline int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base,
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int msm_pcie_reg_dump(struct pci_dev *pci_dev, u8 *buff, u32 len)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif /* CONFIG_PCI_MSM */
|
||||
|
||||
#endif /* __MSM_PCIE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user