ASoC: wcd937x: Fix playback stop issue after SSR/PDR on special hs
If we start playback on special hs after record is done and perform SSR/PDR then playback gets paused. This happens because ANA_TX_DIV2_CLK which needs to be enabled for special hs gets disabled after record is stopped. Maintain a count for ANA_DIV2_CLK to enable/disable it as required. Change-Id: Ic73475c83cb16e3c014f35b8d46ee22d2e7a2efd Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
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@ -83,6 +83,8 @@ struct wcd937x_priv {
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struct snd_info_entry *entry;
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struct snd_info_entry *version_entry;
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int ear_rx_path;
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int ana_clk_count;
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struct mutex ana_tx_clk_lock;
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};
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struct wcd937x_micbias_setting {
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@ -1267,12 +1267,17 @@ static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
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struct snd_soc_component *component =
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snd_soc_dapm_to_component(w->dapm);
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struct wcd937x_priv *wcd937x =
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snd_soc_component_get_drvdata(component);
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dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
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w->name, event);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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mutex_lock(&wcd937x->ana_tx_clk_lock);
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wcd937x->ana_clk_count++;
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mutex_unlock(&wcd937x->ana_tx_clk_lock);
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
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snd_soc_component_update_bits(component,
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@ -1296,6 +1301,8 @@ static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
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{
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struct snd_soc_component *component =
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snd_soc_dapm_to_component(w->dapm);
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struct wcd937x_priv *wcd937x =
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snd_soc_component_get_drvdata(component);
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dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
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w->name, event);
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@ -1324,8 +1331,15 @@ static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
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WCD937X_ANA_TX_CH2, 0x80, 0x00);
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
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snd_soc_component_update_bits(component,
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mutex_lock(&wcd937x->ana_tx_clk_lock);
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wcd937x->ana_clk_count--;
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if (wcd937x->ana_clk_count <= 0) {
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
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wcd937x->ana_clk_count = 0;
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}
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mutex_unlock(&wcd937x->ana_tx_clk_lock);
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
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break;
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@ -1389,6 +1403,9 @@ int wcd937x_micbias_control(struct snd_soc_component *component,
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break;
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case MICB_ENABLE:
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wcd937x->micb_ref[micb_index]++;
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mutex_lock(&wcd937x->ana_tx_clk_lock);
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wcd937x->ana_clk_count++;
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mutex_unlock(&wcd937x->ana_tx_clk_lock);
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if (wcd937x->micb_ref[micb_index] == 1) {
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
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@ -1413,6 +1430,9 @@ int wcd937x_micbias_control(struct snd_soc_component *component,
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&wcd937x->mbhc->wcd_mbhc);
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break;
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case MICB_DISABLE:
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mutex_lock(&wcd937x->ana_tx_clk_lock);
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wcd937x->ana_clk_count--;
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mutex_unlock(&wcd937x->ana_tx_clk_lock);
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if (wcd937x->micb_ref[micb_index] > 0)
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wcd937x->micb_ref[micb_index]--;
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if ((wcd937x->micb_ref[micb_index] == 0) &&
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@ -1433,6 +1453,14 @@ int wcd937x_micbias_control(struct snd_soc_component *component,
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post_off_event,
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&wcd937x->mbhc->wcd_mbhc);
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}
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mutex_lock(&wcd937x->ana_tx_clk_lock);
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if (wcd937x->ana_clk_count <= 0) {
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snd_soc_component_update_bits(component,
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WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
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0x10, 0x00);
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wcd937x->ana_clk_count = 0;
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}
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mutex_unlock(&wcd937x->ana_tx_clk_lock);
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if (is_dapm && post_dapm_off && wcd937x->mbhc)
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blocking_notifier_call_chain(
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&wcd937x->mbhc->notifier, post_dapm_off,
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@ -2757,6 +2785,7 @@ static int wcd937x_bind(struct device *dev)
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}
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mutex_init(&wcd937x->micb_lock);
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mutex_init(&wcd937x->ana_tx_clk_lock);
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/* Request for watchdog interrupt */
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wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
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"HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
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@ -2793,6 +2822,7 @@ static void wcd937x_unbind(struct device *dev)
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snd_soc_unregister_component(dev);
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component_unbind_all(dev, wcd937x);
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mutex_destroy(&wcd937x->micb_lock);
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mutex_destroy(&wcd937x->ana_tx_clk_lock);
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}
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static const struct of_device_id wcd937x_dt_match[] = {
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