clk: add BCM63XX gated clock controller driver
Add a driver for the gated clock controller found on MIPS based BCM63XX SoCs. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [sboyd@kernel.org: Remove module.h include and associated things for a non-modular driver, add static on data tables, drop of_match_ptr() usage, fix spdx tag to be a C++ style comment] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jonas Gorski
Stephen Boyd
parent
dc1d9dac5c
commit
1c099779c1
@ -7,6 +7,14 @@ config CLK_BCM_63XX
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Enable common clock framework support for Broadcom BCM63xx DSL SoCs
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based on the ARM architecture
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config CLK_BCM_63XX_GATE
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bool "Broadcom BCM63xx gated clock support"
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depends on BMIPS_GENERIC || COMPILE_TEST
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default BMIPS_GENERIC
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help
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Enable common clock framework support for Broadcom BCM63xx DSL SoCs
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based on the MIPS architecture
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config CLK_BCM_KONA
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bool "Broadcom Kona CCU clock support"
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depends on ARCH_BCM_MOBILE || COMPILE_TEST
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
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obj-$(CONFIG_CLK_BCM_63XX_GATE) += clk-bcm63xx-gate.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
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238
drivers/clk/bcm/clk-bcm63xx-gate.c
Normal file
238
drivers/clk/bcm/clk-bcm63xx-gate.c
Normal file
@ -0,0 +1,238 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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struct clk_bcm63xx_table_entry {
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const char * const name;
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u8 bit;
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unsigned long flags;
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};
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struct clk_bcm63xx_hw {
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void __iomem *regs;
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spinlock_t lock;
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struct clk_hw_onecell_data data;
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};
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static const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
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{ .name = "mac", .bit = 3, },
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{ .name = "tc", .bit = 5, },
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{ .name = "us_top", .bit = 6, },
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{ .name = "ds_top", .bit = 7, },
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{ .name = "acm", .bit = 8, },
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{ .name = "spi", .bit = 9, },
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{ .name = "usbs", .bit = 10, },
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{ .name = "bmu", .bit = 11, },
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{ .name = "pcm", .bit = 12, },
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{ .name = "ntp", .bit = 13, },
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{ .name = "acp_b", .bit = 14, },
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{ .name = "acp_a", .bit = 15, },
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{ .name = "emusb", .bit = 17, },
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{ .name = "enet0", .bit = 18, },
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{ .name = "enet1", .bit = 19, },
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{ .name = "usbsu", .bit = 20, },
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{ .name = "ephy", .bit = 21, },
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{ },
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};
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static const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
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{ .name = "phy_mips", .bit = 0, },
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{ .name = "adsl_qproc", .bit = 1, },
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{ .name = "adsl_afe", .bit = 2, },
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{ .name = "adsl", .bit = 3, },
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{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
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{ .name = "sar", .bit = 5, },
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{ .name = "pcm", .bit = 6, },
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{ .name = "usbd", .bit = 7, },
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{ .name = "usbh", .bit = 8, },
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{ .name = "hsspi", .bit = 9, },
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{ .name = "pcie", .bit = 10, },
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{ .name = "robosw", .bit = 11, },
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{ },
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};
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static const struct clk_bcm63xx_table_entry bcm6358_clocks[] = {
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{ .name = "enet", .bit = 4, },
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{ .name = "adslphy", .bit = 5, },
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{ .name = "pcm", .bit = 8, },
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{ .name = "spi", .bit = 9, },
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{ .name = "usbs", .bit = 10, },
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{ .name = "sar", .bit = 11, },
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{ .name = "emusb", .bit = 17, },
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{ .name = "enet0", .bit = 18, },
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{ .name = "enet1", .bit = 19, },
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{ .name = "usbsu", .bit = 20, },
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{ .name = "ephy", .bit = 21, },
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{ },
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};
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static const struct clk_bcm63xx_table_entry bcm6362_clocks[] = {
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{ .name = "adsl_qproc", .bit = 1, },
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{ .name = "adsl_afe", .bit = 2, },
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{ .name = "adsl", .bit = 3, },
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{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
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{ .name = "wlan_ocp", .bit = 5, },
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{ .name = "swpkt_usb", .bit = 7, },
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{ .name = "swpkt_sar", .bit = 8, },
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{ .name = "sar", .bit = 9, },
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{ .name = "robosw", .bit = 10, },
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{ .name = "pcm", .bit = 11, },
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{ .name = "usbd", .bit = 12, },
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{ .name = "usbh", .bit = 13, },
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{ .name = "ipsec", .bit = 14, },
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{ .name = "spi", .bit = 15, },
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{ .name = "hsspi", .bit = 16, },
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{ .name = "pcie", .bit = 17, },
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{ .name = "fap", .bit = 18, },
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{ .name = "phymips", .bit = 19, },
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{ .name = "nand", .bit = 20, },
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{ },
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};
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static const struct clk_bcm63xx_table_entry bcm6368_clocks[] = {
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{ .name = "vdsl_qproc", .bit = 2, },
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{ .name = "vdsl_afe", .bit = 3, },
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{ .name = "vdsl_bonding", .bit = 4, },
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{ .name = "vdsl", .bit = 5, },
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{ .name = "phymips", .bit = 6, },
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{ .name = "swpkt_usb", .bit = 7, },
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{ .name = "swpkt_sar", .bit = 8, },
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{ .name = "spi", .bit = 9, },
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{ .name = "usbd", .bit = 10, },
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{ .name = "sar", .bit = 11, },
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{ .name = "robosw", .bit = 12, },
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{ .name = "utopia", .bit = 13, },
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{ .name = "pcm", .bit = 14, },
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{ .name = "usbh", .bit = 15, },
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{ .name = "disable_gless", .bit = 16, },
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{ .name = "nand", .bit = 17, },
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{ .name = "ipsec", .bit = 18, },
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{ },
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};
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static const struct clk_bcm63xx_table_entry bcm63268_clocks[] = {
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{ .name = "disable_gless", .bit = 0, },
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{ .name = "vdsl_qproc", .bit = 1, },
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{ .name = "vdsl_afe", .bit = 2, },
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{ .name = "vdsl", .bit = 3, },
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{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
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{ .name = "wlan_ocp", .bit = 5, },
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{ .name = "dect", .bit = 6, },
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{ .name = "fap0", .bit = 7, },
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{ .name = "fap1", .bit = 8, },
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{ .name = "sar", .bit = 9, },
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{ .name = "robosw", .bit = 10, },
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{ .name = "pcm", .bit = 11, },
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{ .name = "usbd", .bit = 12, },
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{ .name = "usbh", .bit = 13, },
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{ .name = "ipsec", .bit = 14, },
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{ .name = "spi", .bit = 15, },
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{ .name = "hsspi", .bit = 16, },
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{ .name = "pcie", .bit = 17, },
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{ .name = "phymips", .bit = 18, },
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{ .name = "gmac", .bit = 19, },
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{ .name = "nand", .bit = 20, },
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{ .name = "tbus", .bit = 27, },
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{ .name = "robosw250", .bit = 31, },
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{ },
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};
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static int clk_bcm63xx_probe(struct platform_device *pdev)
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{
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const struct clk_bcm63xx_table_entry *entry, *table;
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struct clk_bcm63xx_hw *hw;
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struct resource *r;
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u8 maxbit = 0;
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int i, ret;
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table = of_device_get_match_data(&pdev->dev);
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if (!table)
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return -EINVAL;
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for (entry = table; entry->name; entry++)
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maxbit = max_t(u8, maxbit, entry->bit);
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hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
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GFP_KERNEL);
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if (!hw)
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return -ENOMEM;
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platform_set_drvdata(pdev, hw);
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spin_lock_init(&hw->lock);
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hw->data.num = maxbit;
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for (i = 0; i < maxbit; i++)
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hw->data.hws[i] = ERR_PTR(-ENODEV);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hw->regs = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(hw->regs))
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return PTR_ERR(hw->regs);
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for (entry = table; entry->name; entry++) {
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struct clk_hw *clk;
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clk = clk_hw_register_gate(&pdev->dev, entry->name, NULL,
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entry->flags, hw->regs, entry->bit,
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CLK_GATE_BIG_ENDIAN, &hw->lock);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto out_err;
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}
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hw->data.hws[entry->bit] = clk;
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}
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ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
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&hw->data);
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if (!ret)
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return 0;
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out_err:
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for (i = 0; i < hw->data.num; i++) {
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if (!IS_ERR(hw->data.hws[i]))
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clk_hw_unregister_gate(hw->data.hws[i]);
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}
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return ret;
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}
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static int clk_bcm63xx_remove(struct platform_device *pdev)
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{
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struct clk_bcm63xx_hw *hw = platform_get_drvdata(pdev);
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int i;
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of_clk_del_provider(pdev->dev.of_node);
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for (i = 0; i < hw->data.num; i++) {
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if (!IS_ERR(hw->data.hws[i]))
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clk_hw_unregister_gate(hw->data.hws[i]);
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}
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return 0;
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}
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static const struct of_device_id clk_bcm63xx_dt_ids[] = {
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{ .compatible = "brcm,bcm3368-clocks", .data = &bcm3368_clocks, },
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{ .compatible = "brcm,bcm6328-clocks", .data = &bcm6328_clocks, },
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{ .compatible = "brcm,bcm6358-clocks", .data = &bcm6358_clocks, },
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{ .compatible = "brcm,bcm6362-clocks", .data = &bcm6362_clocks, },
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{ .compatible = "brcm,bcm6368-clocks", .data = &bcm6368_clocks, },
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{ .compatible = "brcm,bcm63268-clocks", .data = &bcm63268_clocks, },
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{ }
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};
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static struct platform_driver clk_bcm63xx = {
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.probe = clk_bcm63xx_probe,
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.remove = clk_bcm63xx_remove,
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.driver = {
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.name = "bcm63xx-clock",
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.of_match_table = clk_bcm63xx_dt_ids,
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},
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};
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builtin_platform_driver(clk_bcm63xx);
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