diff --git a/drivers/clk/qcom/gpucc-blair.c b/drivers/clk/qcom/gpucc-blair.c
index c92a8c7bc6f23..51ce96715ca72 100644
--- a/drivers/clk/qcom/gpucc-blair.c
+++ b/drivers/clk/qcom/gpucc-blair.c
@@ -23,12 +23,10 @@
 
 static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);
 static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);
-static DEFINE_VDD_REGULATORS(vdd_gx, VDD_HIGH_L1 + 1, 1, vdd_corner);
+static DEFINE_VDD_REGULATORS(vdd_gx, VDD_NUM, 2, vdd_gx_corner);
 
 static struct clk_vdd_class *gpu_cc_blair_regulators[] = {
-	&vdd_cx,
 	&vdd_mx,
-	&vdd_gx,
 };
 
 enum {
@@ -468,6 +466,22 @@ static int gpu_cc_blair_probe(struct platform_device *pdev)
 	struct regmap *regmap;
 	int ret;
 
+	vdd_gx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gx");
+	if (IS_ERR(vdd_gx.regulator[0])) {
+		if (!(PTR_ERR(vdd_gx.regulator[0]) == -EPROBE_DEFER))
+			dev_err(&pdev->dev, "Unable to get vdd_gx regulator\n");
+		return PTR_ERR(vdd_gx.regulator[0]);
+	}
+
+	vdd_gx.regulator[1] = devm_regulator_get(&pdev->dev, "vdd_cx");
+	if (IS_ERR(vdd_gx.regulator[1])) {
+		if (!(PTR_ERR(vdd_gx.regulator[1]) == -EPROBE_DEFER))
+			dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
+			return PTR_ERR(vdd_gx.regulator[1]);
+	}
+
+	vdd_cx.regulator[0] = vdd_gx.regulator[1];
+
 	regmap = qcom_cc_map(pdev, &gpu_cc_blair_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
diff --git a/drivers/clk/qcom/vdd-level-holi.h b/drivers/clk/qcom/vdd-level-holi.h
index d37d307e45a11..356c6eaee4278 100644
--- a/drivers/clk/qcom/vdd-level-holi.h
+++ b/drivers/clk/qcom/vdd-level-holi.h
@@ -32,4 +32,17 @@ static int vdd_corner[] = {
 	[VDD_HIGH_L1]     = RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
 };
 
+
+static int vdd_gx_corner[] = {
+	0, 0,
+	RPM_SMD_REGULATOR_LEVEL_MIN_SVS, RPM_SMD_REGULATOR_LEVEL_MIN_SVS,
+	RPM_SMD_REGULATOR_LEVEL_LOW_SVS, RPM_SMD_REGULATOR_LEVEL_LOW_SVS,
+	RPM_SMD_REGULATOR_LEVEL_SVS, RPM_SMD_REGULATOR_LEVEL_SVS,
+	RPM_SMD_REGULATOR_LEVEL_SVS_PLUS, RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,
+	RPM_SMD_REGULATOR_LEVEL_NOM, RPM_SMD_REGULATOR_LEVEL_NOM,
+	RPM_SMD_REGULATOR_LEVEL_NOM_PLUS, RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,
+	RPM_SMD_REGULATOR_LEVEL_TURBO, RPM_SMD_REGULATOR_LEVEL_TURBO,
+	RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR, RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
+};
+
 #endif