diff --git a/arch/arm64/boot/dts/vendor/qcom/display/bindings/sde-dp.txt b/arch/arm64/boot/dts/vendor/qcom/display/bindings/sde-dp.txt index 5f0c5fc4fba9..14cfd1cf131f 100644 --- a/arch/arm64/boot/dts/vendor/qcom/display/bindings/sde-dp.txt +++ b/arch/arm64/boot/dts/vendor/qcom/display/bindings/sde-dp.txt @@ -1,7 +1,9 @@ Qualcomm Technologies, Inc. sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. DP Controller: Required properties: -- compatible: Should be "qcom,dp-display". +- compatible: one of the following + "qcom,edp-display" + "qcom,dp-display" - reg: Base address and length of DP hardware's memory mapped regions. - reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. "dp_ahb" - AHB memory region. @@ -117,6 +119,7 @@ Optional properties: device node. Refer to pinctrl-bindings.txt - qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. - qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one +- qcom,display-type: A property to make the edp or dp display as primary. [Optional child nodes]: These nodes are for devices which are dependent on msm_ext_disp. If msm_ext_disp is disabled then diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-4k-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-4k-video.dtsi new file mode 100644 index 000000000000..03eb7681920d --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-4k-video.dtsi @@ -0,0 +1,45 @@ +&mdss_mdp { + dsi_ext_bridge_4k_vid: qcom,mdss_dsi_ext_bridge_4k_video { + qcom,mdss-dsi-panel-name = "ext 4k video mode dsi bridge"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-t-clk-post = <0x1e>; + qcom,mdss-dsi-t-clk-pre = <0x2e>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,mdss-dsi-ext-bridge-mode; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <400>; + qcom,mdss-dsi-h-pulse-width = <88>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <72>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi index aa612e99cbb1..5d515d2ef3c9 100644 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi @@ -11,6 +11,7 @@ #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ext-bridge-4k-video.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-sim-dsc375-cmd.dtsi" @@ -275,6 +276,18 @@ }; }; +&dsi_ext_bridge_4k_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0f 2e 2b 0f + 10 0b 02 04 00 2e 1e]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-common.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-common.dtsi index dc79e9e90769..75c2696af682 100644 --- a/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-common.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-common.dtsi @@ -10,6 +10,8 @@ #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi" #include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ili9881p-720-video.dtsi" #include &soc { @@ -349,3 +351,34 @@ }; }; }; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; +}; + +&dsi_ili9881p_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio-always-on; + + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x12>; + qcom,dsi-display-active; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { + + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1F 05 + 05 06 02 04 00 12 0A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-iot-pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-iot-pm7250b.dtsi new file mode 100644 index 000000000000..e889360c1c35 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-iot-pm7250b.dtsi @@ -0,0 +1,36 @@ +#include "yupik-sde-display.dtsi" + +&pm7250b_gpios { + disp_lcd_bias_en { + disp_lcd_bias_en_default: disp_lcd_bias_en_default { + pins = "gpio2"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&pm8350c_gpios { + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio8"; + function = "func1"; + input-disable; + output-low; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde.dtsi index 5b36e34752a2..c5e834a18938 100644 --- a/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/display/yupik-sde.dtsi @@ -1,5 +1,9 @@ #include "yupik-sde-common.dtsi" +#include #include +#include +#include +#include &soc { disp_rdump_memory: disp_rdump_region@e1000000 { @@ -19,6 +23,144 @@ compatible = "qcom,msm-hdcp"; }; + sde_edp: qcom,edp_display@aea0000 { + status = "disabled"; + cell-index = <1>; + qcom,intf-index = <1>; + compatible = "qcom,edp-display"; + label = "drm_edp"; + + reg = <0xaea0000 0x0fc>, + <0xaea0200 0x0c0>, + <0xaea0400 0x770>, + <0xaea1000 0x098>, + <0xaec2a00 0x200>, + <0xaec2200 0x200>, + <0xaec2600 0x200>, + <0xaf01188 0x1f>, + <0xaec2000 0x200>, + <0xaee4000 0x034>, + <0xaf01004 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", + "hdcp_physical", "gdsc"; + + qcom,pixel-base-off = <0>; + interrupt-parent = <&mdss_mdp>; + interrupts = <14 0>; + + qcom,dp-aux-switch = <&sde_edp>; + qcom,dp-low-power-hw-hpd; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&sde_edp 0>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>, + <&sde_edp 1>, + <&rpmhcc RPMH_CXO_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_edp_refclk", + "link_clk", "link_clk_src", "link_iface_clk", + "link_parent", + "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", + "strm0_pixel_clk"; + + qcom,pll-revision = "edp-7nm"; + qcom,phy-version = <0x500>; + qcom,phy-mode = "edp"; + qcom,aux-cfg0-settings = [24 00]; + qcom,aux-cfg1-settings = [28 13]; + qcom,aux-cfg2-settings = [2c 24]; + qcom,aux-cfg3-settings = [30 00]; + qcom,aux-cfg4-settings = [34 0a]; + qcom,aux-cfg5-settings = [38 26]; + qcom,aux-cfg6-settings = [3c 0a]; + qcom,aux-cfg7-settings = [40 03]; + qcom,aux-cfg8-settings = [44 37]; + qcom,aux-cfg9-settings = [4c 03]; + + qcom,max-pclk-frequency-khz = <675000>; + qcom,display-type = "primary"; + + qcom,widebus-enable; + qcom,ssc-feature-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L10C>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + refgen-supply = <&refgen>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <30100>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + sde_dp: qcom,dp_display@ae90000 { cell-index = <0>; compatible = "qcom,dp-display";