From d817cdc29eda83a48f41b473786201d4d3d6ed0d Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Sat, 4 Apr 2020 01:57:33 -0400 Subject: [PATCH 001/327] ARM: dts: msm: specify reg bus scaling vectors for SDE on Lahaina Provide bus scaling vectors for the SDE AHB path. These values are now moved to the device-tree for scalability. Change-Id: Ic23aa5534ab0ccb1838355d6c0f9d10e9d76489c --- bindings/sde.txt | 91 ++++++++++++---------------------------- display/lahaina-sde.dtsi | 4 ++ 2 files changed, 31 insertions(+), 64 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index f61db98acd97..831e30b476b1 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -507,31 +507,25 @@ Optional properties: -- qcom,sde-limit-ids: respective ids for the above usecases -- qcom,sde-limit-values: usecase and value for different combinations -Bus Scaling Subnodes: -- qcom,sde-reg-bus: Property to provide Bus scaling for register access for - mdss blocks. -- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for - mdss blocks. -- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for - mnoc to llcc. -- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for - llcc to ebi. - +Bus Scaling: +- interconnects An array of 4 cell properties with the format of + (src-noc master-id dst-noc slave-id) as described in: + Documentation/devicetree/bindings/interconnect/interconnect.txt + One entry for each interconnect path available. + Master/Slave ID bindings can be found at: + include/dt-bindings/interconnect/ +- interconnect-names An array of string properties associated with "interconnects" + each with a unique name used to lookup the respective path. + The following paths are currently supported: qcom,sde-reg-bus, + qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, + qcom,sde-ebi-bus +- qcom,sde-reg-bus,vectors-KBps:A series of 2 cell properties with a format of + (ab, ib) specified in kilobytes-per-second. + Used when applying reg-bus votes and must be + given whenever "qcom,sde-reg-bus" is used. - qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle, instance id), of inline rotator device. -Bus Scaling Data: -- qcom,msm-bus,name: String property describing client name. -- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases - defined in the vectors property. -- qcom,msm-bus,num-paths: This represents the number of paths in each - Bus Scaling Usecase. -- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt - * Current values of src & dst are defined at - include/linux/msm-bus-board.h - SMMU Subnodes: - smmu_sde_****: Child nodes representing sde smmu virtual devices @@ -898,48 +892,17 @@ Example: }; }; - qcom,sde-data-bus { - qcom,msm-bus,name = "mdss_sde"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <3>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, <25 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <25 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>, - <25 512 0 6400000>; - }; - qcom,sde-llcc-bus { - qcom,msm-bus,name = "mdss_sde_llcc"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <132 770 0 0>, - <132 770 0 6400000>, - <132 770 0 6400000>; - }; - qcom,sde-ebi-bus { - qcom,msm-bus,name = "mdss_sde_ebi"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <129 512 0 0>, - <129 512 0 6400000>, - <129 512 0 6400000>; - }; - - qcom,sde-reg-bus { - /* Reg Bus Scale Settings */ - qcom,msm-bus,name = "mdss_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,active-only; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 160000>, - <1 590 0 320000>; - }; + interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> + <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, + <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; smmu_kms_unsec: qcom,smmu_kms_unsec_cb { compatible = "qcom,smmu_sde_unsec"; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6675eb604202..45f323e9c4fd 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -249,6 +249,10 @@ &config_noc SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; From 649282ac3bfed67fb7bf8b127ca7f99ddc227c58 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Thu, 12 Mar 2020 15:02:02 -0400 Subject: [PATCH 002/327] ARM: dts: msm: Add LUTBUS support for VIG Gamut on Lahaina On Lahaina based targets the DB LUTDMA engine now supports the new LUTBUS DMA operation. Update VIG Gamut version to indicate the LUTBUS operation is now used for DMA programming. Change-Id: I0979be7aaaec6b8a45fd44d40523bc459dbe948e --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d4607746dc98..b388dc1d7d8d 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -252,7 +252,7 @@ qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; From 123c5331545a021465ce8e365eeb8c9a01ab7e87 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 9 Apr 2020 06:26:10 -0700 Subject: [PATCH 003/327] ARM: dts: msm: update Sharp qsync panel DSI phy timings for lahaina Change updates PHY timings of Sharp QSYNC CMD and VID mode panels as per latest HW recommendation. Change-Id: Iaf4b886b04fcc527df3986f70cf47538eea463ab --- display/lahaina-sde-display.dtsi | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 5d64f743a336..23771547699f 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -329,8 +329,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 + 03 02 02 04 00 0b 07]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -338,15 +338,15 @@ }; timing@1 { /* WQHD 60FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; timing@2 { /* FHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02 - 02 00 02 04 00 0a 12]; + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -354,8 +354,8 @@ }; timing@3 { /* WQHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0f 04 04 07 07 04 - 05 02 02 04 00 0d 09]; + qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 + 04 03 02 04 00 0e 08]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -363,8 +363,8 @@ }; timing@4 { /* WQHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 26 0b 0a 11 0f 0b - 0b 07 02 04 00 1f 0f]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -372,15 +372,15 @@ }; timing@5 { /* WQHD 120FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; timing@6 { /* FHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 - 04 02 02 04 00 0e 13]; + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03 + 03 02 02 04 00 0c 08]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -388,8 +388,8 @@ }; timing@7 { /* FHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 02 01 02 04 00 0c 12]; + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -408,8 +408,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 08 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; From a113deac212fc4f6c21e16495bf12496297a2cb4 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 10 Mar 2020 19:22:41 -0700 Subject: [PATCH 004/327] ARM: dts: msm: enable secondary DSI display for lahaina Change enables secondary DSI display for lahaina target. Change-Id: I77869965a807ef2189ac4c5a822d45288c635bfa --- display/dsi-panel-r66451-dsc-qhd-cmd.dtsi | 3 ++ display/lahaina-sde-display-cdp.dtsi | 19 ++++++++- display/lahaina-sde-display-mtp.dtsi | 11 ++++++ display/lahaina-sde-display.dtsi | 47 ++++++++++++++++++++++- 4 files changed, 78 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi index 1d9d3e26f7cf..f5bb6a05fea2 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi @@ -14,6 +14,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-lane-map = "lane_map_0123"; qcom,mdss-dsi-bllp-eof-power-mode; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 5e6288b7d302..909a24d435b7 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -21,12 +21,15 @@ &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_r66451_amoled_video { @@ -114,11 +117,14 @@ &dsi_nt35695b_truly_fhd_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_sim_cmd { @@ -163,7 +169,18 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; +}; + + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; - diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 8643ec14d181..1670754abfd0 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -61,6 +61,17 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 5d64f743a336..8816b03298ea 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -154,6 +154,34 @@ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; + + qcom,mdp = <&mdss_mdp>; + }; + sde_wb: qcom,wb-display@0 { compatible = "qcom,wb-display"; cell-index = <0>; @@ -162,7 +190,7 @@ }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_rscc>; + connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; /* PHY TIMINGS REVISION YB */ @@ -230,6 +258,7 @@ &dsi_r66451_amoled_cmd { qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 08 07 0c 0b 07 @@ -489,6 +518,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 @@ -791,3 +821,18 @@ }; }; }; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; From 4fe1547298f51fa5f9e7ed3cfa3d084d02c63f28 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 1 Apr 2020 14:28:47 +0800 Subject: [PATCH 005/327] ARM: dts: msm: set 60hz cmd mode as default mode for qrd lahaina Set 60hz cmd mode as default display panel mode, and enable ESD check for cmd mode. Changed the PHY timing settings according to the new PHY timing excel version. Change-Id: Ib026bb19595a7f30bc7b2a36ac5eeb02749b043e --- display/dsi-panel-r66451-dsc-qhd-cmd.dtsi | 262 +++++++++++----------- display/lahaina-sde-display-qrd.dtsi | 2 +- display/lahaina-sde-display.dtsi | 34 ++- 3 files changed, 148 insertions(+), 150 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi index f5bb6a05fea2..c1caaf5afd7a 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi @@ -37,6 +37,138 @@ qcom,mdss-dsi-te-using-te-pin; qcom,mdss-dsi-display-timings { timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-height = <2340>; @@ -132,136 +264,6 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; - - timing@1 { - qcom,mdss-dsi-panel-framerate = <90>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <95>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <1>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 0c 03 14 00 09 3c 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 19 cf 64 0b 00 00 00 - 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 02 f7 01 - 39 01 00 00 00 00 03 df 50 40 - 39 01 00 00 00 00 06 f3 50 00 00 00 00 - 39 01 00 00 00 00 02 f2 11 - 39 01 00 00 00 00 06 f3 01 00 00 00 01 - 39 01 00 00 00 00 03 f4 00 02 - 39 01 00 00 00 00 02 f2 19 - 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 2a 00 00 04 37 - 39 01 00 00 00 00 05 2b 00 00 09 23 - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 - ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <20>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2340>; - qcom,mdss-dsi-h-front-porch = <95>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <1>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 1a c2 09 24 0c 00 00 - 0c 09 3c 00 09 3c 00 00 00 00 00 00 - 00 00 00 00 00 30 00 6c - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 13 d8 00 00 00 00 00 - 00 00 00 00 5b 00 5b 00 5b 00 5b 00 - 5b - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 - 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 19 cf 64 0b 00 00 00 - 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 - 39 01 00 00 00 00 02 f7 01 - 39 01 00 00 00 00 03 df 50 40 - 39 01 00 00 00 00 06 f3 50 00 00 00 00 - 39 01 00 00 00 00 02 f2 11 - 39 01 00 00 00 00 06 f3 01 00 00 00 01 - 39 01 00 00 00 00 03 f4 00 02 - 39 01 00 00 00 00 02 f2 19 - 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 2a 00 00 04 37 - 39 01 00 00 00 00 05 2b 00 00 09 23 - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 - ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <20>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; }; }; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 50a41f2753b0..b28072692f4e 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -62,5 +62,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 7bfc29dc3452..0d0bb48d2298 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -239,16 +239,9 @@ &dsi_r66451_amoled_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { - /* - * CDP could not display using the old HFP(96) and HSYNC(32). - * Modified HFP to 95 and HSYNC to 1, but using the new porch - * to caculator the PHY timing based on version YB, 90hz could - * not display, need to keep the PHY timing(which based on - * HFP=96, HSYNC=32). - */ timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 - 06 04 02 04 00 12 0b]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; @@ -257,29 +250,32 @@ &dsi_r66451_amoled_cmd { qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 19 08 07 0c 0b 07 - 07 05 02 04 00 16 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 13 06 05 09 1f 06 - 06 03 02 04 00 11 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; - /* - * Using PHY Timings version YB 60hz could not display, - * refer to version W, changed T_HS_ZERO from 0x06 to 0x1e. - */ + timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 0d 04 04 07 1e 04 - 04 02 02 04 00 0c 09]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From bf2227f3af8eaa0dba2a924ed11aa86dc6242383 Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Wed, 25 Mar 2020 14:31:22 -0700 Subject: [PATCH 006/327] ARM: dts: msm: enable VDC sim panel on lahaina This change adds missing dtsi entry to enable VDC simulation panel for lahaina target. Change-Id: I4f99fc520831ea6828fd5542972b6155757ae0e0 --- display/lahaina-sde-display-cdp.dtsi | 12 ++++++++++++ display/lahaina-sde-display-mtp.dtsi | 12 ++++++++++++ display/lahaina-sde-display.dtsi | 24 ++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 909a24d435b7..876780b10608 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -163,6 +163,18 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sim_vdc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vdc_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_dual_sim_dsc_375_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 1670754abfd0..522e827866b2 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -72,6 +72,18 @@ qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; +&dsi_sim_vdc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vdc_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 0d0bb48d2298..b3b1589841c9 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -593,6 +593,30 @@ }; }; +&dsi_sim_vdc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vdc_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_dsc_375_cmd { qcom,ulps-enabled; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; From c79cc7da3e7e65904ae7fbdf31afa4004086d5f4 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 13 Apr 2020 11:52:41 -0700 Subject: [PATCH 007/327] ARM: dts: msm: add supported panels for lahaina MTP and QRD Change adds all the supported DSI panels to the Lahaina MTP and QRD platform devicetree. These panels can be chosen on these platforms to run in simulation mode. Change-Id: Idd73668c09b2f3c12e785aad7fe6f20e7cbdde79 --- display/lahaina-sde-display-mtp.dtsi | 102 +++++++++++++++++++++++++++ display/lahaina-sde-display-qrd.dtsi | 102 +++++++++++++++++++++++++++ 2 files changed, 204 insertions(+) diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 522e827866b2..8594b9d3d0b5 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -19,6 +19,108 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index b28072692f4e..cee3ab009b04 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -19,6 +19,108 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 13 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From b6f0d25b3251679746d9aa8fad7b86fcf892e8e4 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Mon, 6 Apr 2020 10:19:24 -0700 Subject: [PATCH 008/327] bindings: Documentation: add pm_qos cpu mask for performance This change adds documentation for pm_qos mask for performance use case. Change-Id: I8ca41b578accbe6cc67041a5abb91b0d63fbd07d Signed-off-by: Narendra Muppalla --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 831e30b476b1..f5b8e898e45d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -463,6 +463,9 @@ Optional properties: for cdp use cases in order of , and . - qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask. +- qcom,sde-qos-cpu-mask-performance: Each bit represents a CPU mask. For example + 0xf represents 4 cpu cores. These cores can be + silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. @@ -734,6 +737,7 @@ Example: qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-vbif-off = <0 0>; From fa1b0e858d5020a0a0f5fbce85d22c51f4d2ec4b Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Fri, 17 Apr 2020 13:12:09 -0700 Subject: [PATCH 009/327] ARM: dts: msm: update DSI PHY timings for panels on Lahaina Change updates PHY timings of DSI panels as per latest HW recommendation for lahaina target. Change-Id: I7c029a11542be4a449212b35afb81a1bc8796d2e --- display/lahaina-sde-display.dtsi | 43 ++++++++++++++++---------------- 1 file changed, 22 insertions(+), 21 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index b3b1589841c9..47efdcc7d8e4 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -193,7 +193,7 @@ connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; -/* PHY TIMINGS REVISION YB */ +/* PHY TIMINGS REVISION YC with reduced margins*/ &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; @@ -206,8 +206,8 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 + 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; @@ -228,8 +228,8 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 + 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; @@ -294,8 +294,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 05 04 08 07 05 - 05 03 02 04 00 0f 09]; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; @@ -314,8 +314,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 - 05 03 02 04 00 10 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 + 06 07 02 04 00 15 0b]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; @@ -334,8 +334,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 00 1a 0c]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; qcom,mdss-dsi-panel-clockrate = <900000000>; @@ -445,8 +445,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 15 06 - 06 04 02 04 00 14 0b]; + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; @@ -466,12 +466,10 @@ qcom,mdss-dsi-display-timings { timing@0 { /* - * Using PHY Timings version W as a - * temporary solution for PHY timing issue that causes - * corruption. + * DPHY regular margins */ qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06 - 06 04 02 04 00 15 16]; + 06 07 02 04 00 17 16 ]; qcom,display-topology = <2 0 2>, <1 0 2>; qcom,default-topology-index = <0>; @@ -495,8 +493,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 19 07 07 0c 0a 07 - 07 05 02 04 00 15 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; qcom,display-topology = <2 0 2>, <1 0 2>; qcom,default-topology-index = <0>; @@ -517,8 +515,11 @@ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; + /* + * DPHY regular margins + */ + qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07 + 07 07 02 04 00 18 16]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; }; From de595b987ef032e495cc34797f3c76b69b5c3af8 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Fri, 24 Apr 2020 02:48:26 -0400 Subject: [PATCH 010/327] Revert: "dt-bindings: add documentation for sde-limit" This reverts commit 658f1491b962fceccb622a9ba78e74af3c1fc0f0 from msm-4.19 which was ported as part of the display device tree techpack. Support for sde-limits has been removed from the driver as it's no longer needed. BW limits have moved to per target based XML files in user-space and linewidth limits already have other properties for specifying. Change-Id: Idcbe8e10e94785bc5774a94e2326d2f77ce4b5ac --- bindings/sde.txt | 38 -------------------------------------- 1 file changed, 38 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 831e30b476b1..bf8e09927a86 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -497,15 +497,6 @@ Optional properties: ordering block 0: lower priority pipe has to be on the left for a given pair of pipes. 1: priority have to be explicitly configured for a given pair of pipes. -- qcom,sde-limits: A node that lists the limits for different properties. This node - can have multiple child nodes. Each child node represents a - specific usecase limit. The usecase can be defined for properties like - sspp linewidth, bw limit etc. - e.g. qcom,sde-limits - -- qcom,sde-limit-name: name of the usecase - -- qcom,sde-limit-cases: different usecases to be considered - -- qcom,sde-limit-ids: respective ids for the above usecases - -- qcom,sde-limit-values: usecase and value for different combinations Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -833,35 +824,6 @@ Example: qcom,sde-dspp-vlut = <0x0 0x00010000>; }; - qcom,sde-limits { - qcom,sde-linewidth-limits{ - qcom,sde-limit-cases = "vig", "dma", "scaling", "inline_rot"; - qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>; - /* the qcom,sde-limit-values property consist of two values: - one for the usecase and the other for the value. The usecase can be - any combination of the values mentioned in qcom,sde-limit-ids. - For eg: <0x5 2560> means usecase is 0x5 and value is 2560. - 0x5 = (0x1 | 0x4) = vig + scaling. Thus the linewidth for usecase - vig + scaling = 2560 */ - qcom,sde-limit-values = <0x1 4096>, - <0x5 2560>, - <0xd 1088>, - <0x2 4096>; - }; - qcom,sde-bw-limits{ - qcom,sde-limit-cases = "per_pipe", "total_bw", "vfe_on", "cwb_on"; - qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; - qcom,sde-limit-values = <0x1 2600000>, - <0x9 2600000>, - <0x5 2600000>, - <0xd 2600000>, - <0x2 5800000>, - <0xa 5500000>, - <0x6 4400000>, - <0xe 3900000>; - }; - }; - qcom,sde-mixer-blocks { qcom,sde-mixer-gc = <0x3c0 0x00010000>; }; From 3b7c3885bca54d06f2dceab82ddf428bb4df289d Mon Sep 17 00:00:00 2001 From: Steven Cohen Date: Wed, 22 Apr 2020 13:33:04 -0400 Subject: [PATCH 011/327] ARM: dts: msm: add scaling linewidth information Add documentation for scaling linewidth property which defines the maximum linewidth supported for scaling use cases. Change-Id: Ib02ab7cf1281b4e50bcc063ac5f45112caab2576 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index bf8e09927a86..409cae1bb374 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -114,6 +114,8 @@ Optional properties: each interface. - qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. - qcom,sde-vig-sspp-linewidth: A u32 value indicates the max vig sspp line width. +- qcom,sde-scaling-linewidth: A u32 value indicates the max vig source pipe line width + for scaling purposes. - qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. - qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. - qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. @@ -648,6 +650,7 @@ Example: <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, <0x3b0 16>; + qcom,sde-scaling-linewidth = <2560>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2560>; qcom,sde-mixer-blendstages = <0x7>; From 919c1ce671b6e7fb74942ff78acd9ea28790e501 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 15 Apr 2020 20:56:30 -0700 Subject: [PATCH 012/327] bindings: Documentation: update VDC-m revision in bindings Update the VDC-m revision in bindings as per the latest programming guidelines. Change-Id: I5400b8cc5dac2c549a0697e42cedaca4b06d7e79 --- bindings/mdss-dsi-panel.txt | 4 ++-- bindings/sde.txt | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 45ed1d08ec9b..3810bb221e3a 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -540,7 +540,7 @@ Optional properties: instead of standard dcs type 0x0A. - qcom,vdc-version: An 8 bit value indicates the VDC version supported by panel. Bits[0.3] provides information about minor version while Bits[4.7] provides - major version information. It supports only VDC rev 1(Major).1(Minor) + major version information. It supports only VDC rev 1(Major).2(Minor) right now. - qcom,vdc-version-release: An 8 bit value indicated VDC version release. This has to be set to 0. - qcom,vdc-slice-height: An u32 value which indicates slice height. This should be atleast 16 lines. @@ -839,7 +839,7 @@ Example: qcom,display-topology = <1 1 1>, <2 2 1>; qcom,default-topology-index = <0>; - qcom,vdc-version = <0x11>; + qcom,vdc-version = <0x12>; qcom,vdc-version-release = <0>; qcom,vdc-slice-height = <256>; qcom,vdc-slice-width = <720>; diff --git a/bindings/sde.txt b/bindings/sde.txt index ffa9d7f8d04e..3b3945ecfacc 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -616,7 +616,7 @@ Example: qcom,sde-dsc-off = <0x00081000 0x00081400>; qcom,sde-vdc-off = <0x7C000>; qcom,sde-vdc-size = <0xf10>; - qcom,sde-vdc-hw-rev = "vdc_1_1"; + qcom,sde-vdc-hw-rev = "vdc_1_2"; qcom,sde-vdc-enc = <0x200>; qcom,sde-vdc-ctl = <0xf00>; qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; From 8aad9b6ff30b50d66fa8a375b8c4f8f2ebbe5514 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 15 Apr 2020 21:00:03 -0700 Subject: [PATCH 013/327] ARM: dts: msm: update VDC-m revision for display Update the VDC-m revision for the simulation panels and SDE as per latest programming guidelines. Change-Id: If8c1d9646aac96e06b5a3afab97dc8d7469bdcfc --- display/dsi-panel-sim-vdc-cmd.dtsi | 2 +- display/dsi-panel-sim-vdc-vid.dtsi | 2 +- display/lahaina-sde.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/dsi-panel-sim-vdc-cmd.dtsi b/display/dsi-panel-sim-vdc-cmd.dtsi index 61a47f94dcb9..32f4850ac3c6 100644 --- a/display/dsi-panel-sim-vdc-cmd.dtsi +++ b/display/dsi-panel-sim-vdc-cmd.dtsi @@ -222,7 +222,7 @@ qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "vdc"; - qcom,vdc-version = <0x11>; + qcom,vdc-version = <0x12>; qcom,vdc-version-release = <0>; qcom,vdc-slice-height = <256>; qcom,vdc-slice-width = <720>; diff --git a/display/dsi-panel-sim-vdc-vid.dtsi b/display/dsi-panel-sim-vdc-vid.dtsi index 2162e72cef4c..35cc01f1cdc2 100644 --- a/display/dsi-panel-sim-vdc-vid.dtsi +++ b/display/dsi-panel-sim-vdc-vid.dtsi @@ -215,7 +215,7 @@ qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "vdc"; - qcom,vdc-version = <0x11>; + qcom,vdc-version = <0x12>; qcom,vdc-version-release = <0>; qcom,vdc-slice-height = <256>; qcom,vdc-slice-width = <720>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d1d64720a59a..a132a3a8e1a1 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -115,7 +115,7 @@ qcom,sde-vdc-off = <0x7C000>; qcom,sde-vdc-size = <0x10>; - qcom,sde-vdc-hw-rev = "vdc_1_1"; + qcom,sde-vdc-hw-rev = "vdc_1_2"; qcom,sde-vdc-enc = <0x200>; qcom,sde-vdc-enc-size = <0x1C8>; qcom,sde-vdc-ctl = <0xf00>; From aca4f10953c528685a3f17ad4a2ca0b37e7defc7 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Sun, 5 Apr 2020 22:42:35 -0400 Subject: [PATCH 014/327] ARM: dts: msm: increase max number of DSCs available for DP use case Increase the maximum number of DSCs available for DP usage to 4. This will allow 4LM topologies requiring more than 2 DSCs to be supported. Change-Id: I9b5c3c9b460a537ccdb84dd7a72d6b7218a4cae0 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d1d64720a59a..801fd5f247dc 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -396,7 +396,7 @@ qcom,widebus-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-blks = <4>; qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; From f57a05b5ba36427013fefeb40f46966dfef52969 Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Thu, 9 Apr 2020 16:09:37 -0700 Subject: [PATCH 015/327] bindings: Documentation: update DisplayPort node Update the documentation for the DisplayPort node on Lahaina. Change-Id: I22e8751db2f9b47fbdc433a2687aee41e4e746af --- bindings/sde-dp.txt | 244 ++++++++++++++++++++++++-------------------- 1 file changed, 136 insertions(+), 108 deletions(-) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index 78812304b887..75bd9a52355f 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -4,28 +4,30 @@ DP Controller: Required properties: - compatible: Should be "qcom,dp-display". - reg: Base address and length of DP hardware's memory mapped regions. - reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. - "dp_phy" - DP PHY memory region. + "dp_ahb" - AHB memory region. + "dp_aux" - AUX memory region. + "dp_link" - LINK memory region. + "dp_p0" - PCLK0 memory region. + "dp_phy" - PHY memory region. "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. "dp_mmss_cc" - Display Clock Control memory region. - "qfprom_physical" - QFPROM Phys memory region. "dp_pll" - USB3 DP combo PLL memory region. "usb3_dp_com" - USB3 DP PHY combo memory region. "hdcp_physical" - DP HDCP memory region. + "dp_p1" - DP PCLK1 memory region. + "gdsc" - DISPCC GDSC memory region. - cell-index: Specifies the controller instance. +- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs) - clocks: Clocks required for Display Port operation. - clock-names: Names of the clocks corresponding to handles. Following clocks are required: - "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", - "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", - "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". -- gdsc-supply: phandle to gdsc regulator node. + "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "strm0_pixel_clk", "strm1_pixel_clk". - vdda-1p2-supply: phandle to vdda 1.2V regulator node. - vdda-0p9-supply: phandle to vdda 0.9V regulator node. - interrupt-parent phandle to the interrupt parent device node. - interrupts: The interrupt signal from the DSI block. -- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. -- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. -- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. - qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first entry in this array corresponds to the register offset within DP AUX, while the remaining entries indicate the @@ -72,12 +74,14 @@ DP Controller: Required properties: - qcom,fec-feature-enable: FEC feature enable control node. - qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port. - qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block. -- qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection. +- qcom,altmode-dev: Phandle for the AltMode GLink driver. +- usb-controller: Phandle for the USB controller. +- qcom,pll-revision: PLL hardware revision. - qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. - qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. - qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. -- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types" - can be "core", "ctrl", and "phy". Within the same type, +- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types" + can be "core", "ctrl", "pll" and "phy". Within the same type, there can be more than one instance of this binding, in which case the entry would be appended with the supply entry index. @@ -96,6 +100,10 @@ msm_ext_disp is a device which manages the interaction between external display interfaces, e.g. Display Port, and the audio subsystem. Optional properties: +- vdd_mx-supply: phandle to vdda MX regulator node +- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. +- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. +- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. - qcom,ext-disp: phandle for msm-ext-display module - compatible: Must be "qcom,msm-ext-disp" - qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node @@ -117,121 +125,141 @@ these devices will be disabled as well. Ex. Audio Codec device. - compatible : "qcom,msm-ext-disp-audio-codec-rx"; Example: - ext_disp: qcom,msm-ext-disp { - compatible = "qcom,msm-ext-disp"; - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; + +ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; }; +}; - sde_dp: qcom,dp_display@0{ - cell-index = <0>; - compatible = "qcom,dp-display"; +sde_dp: qcom,dp_display@0 { + cell-index = <0>; + compatible = "qcom,dp-display"; - gdsc-supply = <&mdss_core_gdsc>; - vdda-1p2-supply = <&pm8998_l26>; - vdda-0p9-supply = <&pm8998_l1>; + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; - reg = <0xae90000 0xa84>, + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, <0xaf02000 0x1a0>, - <0x780000 0x621c>, - <0x88ea030 0x10>, - <0x88e8000 0x621c>, - <0x0aee1000 0x034>; - reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "qfprom_physical", "dp_pll", - "usb3_dp_com", "hdcp_physical"; + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>; - clock-names = "core_aux_clk", "core_usb_ref_clk_src", - "core_usb_ref_clk", "core_usb_cfg_ahb_clk", - "core_usb_pipe_clk", "ctrl_link_clk", - "ctrl_link_iface_clk", "ctrl_crypto_clk", - "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent"; + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "strm0_pixel_clk", "strm1_pixel_clk"; - qcom,dp-usbpd-detection = <&pm8150b_pdphy>; - qcom,ext-disp = <&ext_disp>; - qcom,phy-version = <0x420>; - qcom,dp-aux-switch = <&fsa4480>; + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,dp-aux-switch = <&fsa4480>; - qcom,aux-cfg0-settings = [1c 00]; - qcom,aux-cfg1-settings = [20 13 23 1d]; - qcom,aux-cfg2-settings = [24 00]; - qcom,aux-cfg3-settings = [28 00]; - qcom,aux-cfg4-settings = [2c 0a]; - qcom,aux-cfg5-settings = [30 26]; - qcom,aux-cfg6-settings = [34 0a]; - qcom,aux-cfg7-settings = [38 03]; - qcom,aux-cfg8-settings = [3c bb]; - qcom,aux-cfg9-settings = [40 03]; - qcom,max-pclk-frequency-khz = <593470>; - qcom,mst-enable; - qcom,dsc-feature-enable; - qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; - pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; - pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; - qcom,aux-en-gpio = <&tlmm 43 0>; - qcom,aux-sel-gpio = <&tlmm 51 0>; - qcom,usbplug-cc-gpio = <&tlmm 38 0>; - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + qcom,aux-cfg0-settings = [1c 00]; + qcom,aux-cfg1-settings = [20 13 23 1d]; + qcom,aux-cfg2-settings = [24 00]; + qcom,aux-cfg3-settings = [28 00]; + qcom,aux-cfg4-settings = [2c 0a]; + qcom,aux-cfg5-settings = [30 26]; + qcom,aux-cfg6-settings = [34 0a]; + qcom,aux-cfg7-settings = [38 03]; + qcom,aux-cfg8-settings = [3c bb]; + qcom,aux-cfg9-settings = [40 03]; + qcom,max-pclk-frequency-khz = <593470>; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; }; + }; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <21800>; - qcom,supply-disable-load = <4>; - }; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; }; + }; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <36000>; - qcom,supply-disable-load = <32>; - }; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; }; }; From 364429b18814c001f6a5fba6b17534ecf09f244a Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Wed, 8 Apr 2020 12:57:10 -0700 Subject: [PATCH 016/327] ARM: dts: msm: add device node for MSM HDCP driver on Lahaina Add device node for the MSM HDCP driver which manages communication between HLOS and TZ for HDCP related operations. Change-Id: I7b37814f1ade7f62cf73e196c834da400abba5fe --- display/lahaina-sde.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index a132a3a8e1a1..c1aa1506d31b 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -332,6 +332,10 @@ }; }; + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + sde_dp: qcom,dp_display@ae90000 { cell-index = <0>; compatible = "qcom,dp-display"; From be9737700295cf7e5cad2fbc9fcf8ac230913ae8 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 29 Apr 2020 18:53:45 -0700 Subject: [PATCH 017/327] ARM: dts: msm: add 144FPS configuration for sim panel on lahaina Change adds 144 FPS configuration for FHD resolution DSI simulation panel on lahaina target. Change-Id: I1cc3032fa432940af854d0990f18250a16cfb38e --- .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 52 +++++++++++++++++++ display/lahaina-sde-display.dtsi | 7 +++ 2 files changed, 59 insertions(+) diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index 118d1e935460..0d48d49b21ca 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -1433,6 +1433,58 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@17 { + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index b3b1589841c9..8e9cc9977dc2 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -839,6 +839,13 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; + + timing@17 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; }; }; From 31dba7775519192d0930599a751e0571bfe49fd5 Mon Sep 17 00:00:00 2001 From: Rajkumar Subbiah Date: Wed, 6 May 2020 18:59:22 -0400 Subject: [PATCH 018/327] ARM: dts: msm: enable DP MST support on Lahaina This change enables DP MST support on Lahaina. Change-Id: Ifae606ae3b3a5402a703b147aa0701f6b13713a1 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index d1d64720a59a..a995d3ab04c2 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -394,6 +394,7 @@ qcom,max-pclk-frequency-khz = <675000>; qcom,widebus-enable; + qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; qcom,max-dp-dsc-blks = <2>; From 68e61f431c21d33b6ca04efa43a291cc7a372e59 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 5 May 2020 11:26:32 -0700 Subject: [PATCH 019/327] ARM: dts: msm: remove load for lab/ibb supplies for lahaina While voting for LAB/IBB supplies there is no need for setting a load value. The change updates enable load property to zero so that no load value is set on these regulators for lahaina target. Change-Id: Ifb6a69b337e2e5eb8dcef853daf122db67c2059e --- display/lahaina-sde-display.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 47efdcc7d8e4..a12a242456f8 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -72,8 +72,8 @@ qcom,supply-name = "lab"; qcom,supply-min-voltage = <4600000>; qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <363000>; - qcom,supply-disable-load = <100>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; qcom,panel-supply-entry@3 { @@ -81,8 +81,8 @@ qcom,supply-name = "ibb"; qcom,supply-min-voltage = <4600000>; qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <363000>; - qcom,supply-disable-load = <100>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <20>; }; }; From fa770c0ca1a1a8ef2dfb0603d105932a5f5bbd3d Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Tue, 7 Apr 2020 13:51:10 -0700 Subject: [PATCH 020/327] ARM: dts: msm: add altmode device for DisplayPort client on Lahaina Add a reference to the altmode device for use in the DisplayPort driver. This update is necessitated by a change in the API for altmode client registration. Change-Id: Idaef5fab963b4c280873d30bb424cbe3e26c7419 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index f05698696aee..8960a50c342a 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -342,7 +342,7 @@ qcom,dp-aux-switch = <&fsa4480>; qcom,ext-disp = <&ext_disp>; - qcom,altmode-parent = "altmode_0"; + qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; reg = <0xae90000 0x0dc>, From 64d66d86566a4b325aeecec2f23cd2258be24a35 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 15:41:26 +0800 Subject: [PATCH 021/327] ARM: dts: msm: update clock entries to support CPHY for Lahaina Add cphy specific clock entries for both the DSI controller nodes. Change-Id: I9694595cc079249ad2e4ed58d353f0cc8e3692e4 --- display/lahaina-sde-display.dtsi | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 47efdcc7d8e4..0008a22e9303 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -132,10 +132,16 @@ clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -163,10 +169,16 @@ clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; From 932e556bf17e95922fff659698e0f78370a31e4d Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 15:48:10 +0800 Subject: [PATCH 022/327] dt-bindings: add new property to specify PHY type Add new boolean property that specifies whether the panel is using DSI CPHY. If this property is not set, default PHY type i.e. DPHY will be used. Change-Id: I82e1738e64027e74a7752996c28b10ebdfdf3e15 --- bindings/mdss-dsi-panel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 3810bb221e3a..73cf79d6611e 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -504,7 +504,7 @@ Optional properties: - qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel for any commands that we send. - qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. - +- qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. - qcom,compression-mode: Select compression mode for panel. "fbc" - frame buffer compression "dsc" - display stream compression. From 4b64e529ee5d2c0982f44530fa8cb80d43cecba4 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 21:37:11 +0800 Subject: [PATCH 023/327] ARM: dts: msm: add r66451 cphy panel support for lahaina Add DDIC R66451 Visionox panel CPHY cmd and video mode support. Change-Id: I1952f26dd0437816a5f367f09c4664fb6420966c --- ...si-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi | 100 ++++++++++++++++++ ...-panel-r66451-dsc-fhd-plus-video-cphy.dtsi | 83 +++++++++++++++ display/lahaina-sde-display-cdp.dtsi | 19 ++++ display/lahaina-sde-display-mtp.dtsi | 19 ++++ display/lahaina-sde-display-qrd.dtsi | 19 ++++ display/lahaina-sde-display.dtsi | 28 +++++ 6 files changed, 268 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi new file mode 100644 index 000000000000..8b540370ae41 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi @@ -0,0 +1,100 @@ +&mdss_mdp { + dsi_r66451_amoled_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-mdp-transfer-time-us = <15300>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 03 eb 00 00 + 39 01 00 00 00 00 02 f7 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 02 B4 20 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi new file mode 100644 index 000000000000..4e898a61b030 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi @@ -0,0 +1,83 @@ +&mdss_mdp { + dsi_r66451_amoled_video_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_vid { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 02 B4 20 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 876780b10608..3597392d094b 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -41,6 +41,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sharp_4k_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 8594b9d3d0b5..67eab860d2d8 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -38,6 +38,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sharp_4k_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index cee3ab009b04..913eb806336b 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -19,6 +19,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sw43404_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 0008a22e9303..a2a1caf972ab 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -13,6 +13,8 @@ #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" #include "dsi-panel-r66451-dsc-qhd-cmd.dtsi" #include "dsi-panel-r66451-dsc-qhd-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" @@ -294,6 +296,32 @@ }; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; From 10b21b1a1bdb1f9a012696df9cdc0b2f0ad2a7a5 Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Mon, 20 Apr 2020 17:43:45 -0700 Subject: [PATCH 024/327] ARM: dts: msm: reduce the minimum vote on ahb bus This change ensures that voltage on CNOC does not scale to a higher voltage corner than intended. Display driver only intends to enable the CNOC on power collapse restore. When display really needs higher performance i.e. at first commit it votes for the real bandwidth required. Change-Id: Ib9d9786aed0315fe0457ccb6dbcb73a5a8ad2917 --- display/lahaina-sde.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8960a50c342a..499c0aeb019d 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -250,9 +250,9 @@ interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", "qcom,sde-reg-bus"; qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 76800>, - <0 150000>, - <0 300000>; + <0 74000>, + <0 148000>, + <0 265000>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; From f70cd86f5b91f1fac9d0a2391cd9bdc6c4c21211 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Mon, 11 May 2020 16:06:46 -0700 Subject: [PATCH 025/327] ARM: dts: msm: ensure display GPIO regulator is on during boot Change adds regulator-boot-on property to the GPIO controlled regulator so that the GPIO doesn't get toggeled during boot from UEFI to kernel. Change-Id: Ib0600ff5177de467e27f9efd09da623dc1c238a4 --- display/lahaina-sde-display.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 47efdcc7d8e4..d04261009f13 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -119,6 +119,7 @@ regulator-enable-ramp-delay = <233>; gpio = <&tlmm 12 0>; enable-active-high; + regulator-boot-on; pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; From a8165dbde8cfc8ecd9409b9063b1cffb37f77332 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 13 May 2020 13:45:07 -0700 Subject: [PATCH 026/327] bindings: Documentation: add MDSS HW version Add documentation for the MDSS HW version parameter. Change-Id: I573c885057f98843037d06278600e3b07683872e --- bindings/sde.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index a2b2fba88cb7..1aeb4b45759d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -98,6 +98,7 @@ Optional properties: -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off +- qcom,sde-hw-version: A u32 value indicates the MDSS hw version - qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. - qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. - qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. @@ -578,6 +579,7 @@ Example: iommus = <&mdp_smmu 0>; #power-domain-cells = <0>; + qcom,sde-hw-version = <0x70000000>; qcom,sde-off = <0x1000>; qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 0x00002600 0x00002800>; From 3f015c57a2a9f8208726780cf7d9e382814a6d15 Mon Sep 17 00:00:00 2001 From: Abhijit Kulkarni Date: Fri, 15 May 2020 08:10:47 -0700 Subject: [PATCH 027/327] ARM: dts: msm: make smmu devices as separated device on lahaina This change adds smmu devices as separate devices so that driver waits for these devices to bind before using any smmu operation. This fixes recent stability issues where devices were not probed during the dpu hw initialization. Change-Id: If605ae258b0fc4a314e142b185d6d4553ed30b07 --- display/lahaina-sde-display.dtsi | 3 ++- display/lahaina-sde.dtsi | 32 ++++++++++++++++---------------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index c67153317aec..2f92a01650bf 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -205,7 +205,8 @@ }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi + &sde_dsi1 &sde_rscc>; }; /* PHY TIMINGS REVISION YC with reduced margins*/ diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8960a50c342a..688a1454baef 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -306,22 +306,6 @@ }; }; - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&apps_smmu 0x820 0x402>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-earlymap; /* for cont-splash */ - }; - - smmu_sde_sec: qcom,smmu_sde_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x400>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-vmid = <0xa>; - }; - }; ext_disp: qcom,msm-ext-disp { @@ -669,4 +653,20 @@ }; }; + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + }; From e6bcf34812253c2aefbf2e3c45ece8215bb17a7a Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Sat, 9 May 2020 15:13:02 +0800 Subject: [PATCH 028/327] ARM: dts: msm: add memory region for pll_codes on Lahaina Add memory region for pll_codes on Lahaina, and the pll_codes are used as trim_codes for RFI. Change-Id: Ib1f8d59cc0c3e17a4c9f21894504e1be897a0480 Signed-off-by: Bruce Hoo --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8960a50c342a..237bf948b08a 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -605,6 +605,7 @@ vdda-0p9-supply = <&L5B>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; qcom,platform-strength-ctrl = [55 03 55 03 55 03 From 1f7eae5101a9a0716a5abc21075d1cfd1fe1626e Mon Sep 17 00:00:00 2001 From: Manoj Kumar Amara Date: Wed, 6 May 2020 19:53:51 +0800 Subject: [PATCH 029/327] ARM: dts: msm: enable RFI on lahaina Add clock settings to enable RFI on lahaina. Change-Id: I40f1e89d3e6d40691c58ab25a0278808ec70506a --- display/lahaina-sde-display.dtsi | 34 ++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index c67153317aec..515b2ae44c91 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -134,17 +134,29 @@ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1"; + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -218,6 +230,8 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; qcom,mdss-dsi-display-timings { timing@0 { @@ -239,7 +253,11 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-qsync-min-refresh-rate = <55>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; qcom,mdss-dsi-display-timings { timing@0 { From 697617672a89c69b30114083c42a727039549c7f Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 21 May 2020 14:13:39 -0700 Subject: [PATCH 030/327] ARM: dts: msm: fix compilation error for lahaina Change fixes compilation error introduced by merging commit 1f7eae5101a9 ("ARM: dts: msm: enable RFI on lahaina"). Change-Id: I1cbf7f3069228d3af1ae56ea05043819ac472814 --- display/lahaina-sde-display.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 05492eeeaf7b..616b9d2347d0 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -144,7 +144,7 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, @@ -154,7 +154,7 @@ "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", "shadow_byte_clk1", "shadow_pixel_clk1"; From 97913e764e1b31fa2126d28272e97a38d5485121 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 7 May 2020 12:38:55 -0700 Subject: [PATCH 031/327] ARM: dts: msm: remove qsync property for BOE command mode panel for lahaina QSYNC is not supported by the BOE WQHD command mode panel. The change removes the property from the panel device tree. Change-Id: I8f771f3547aabd4b516f17cf2506ebef901ea3d4 --- display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi index a46f4e80548b..5c1f1e284eea 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi @@ -36,7 +36,6 @@ 17000 15500 30000 8000 3000>; qcom,mdss-dsi-panel-peak-brightness = <4200000>; qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-qsync-min-refresh-rate = <55>; qcom,mdss-dsi-display-timings { timing@0 { @@ -98,14 +97,6 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 5a 01]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 5a 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_lp_mode"; qcom,mdss-dsi-lp1-command = [ 05 01 00 00 00 00 02 39 00 ]; From f4b5e23bcd5d850cbd2a24fe536a8661334552c4 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 14 May 2020 10:36:11 -0700 Subject: [PATCH 032/327] ARM: dts: msm: add 60 FPS for Sharp qhd plus panel for lahaina Change adds 60 FPS timing node and switch command for Sharp QHD plus command mode panel for lahaina target. Change-Id: I1bd7720a9d6be4f66418886dd7efeb7236e86a19 --- display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi | 183 ++++++++++++++++++ display/lahaina-sde-display.dtsi | 9 +- 2 files changed, 191 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi index 06c9b92e86d6..90fb731fbb88 100644 --- a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi +++ b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -38,6 +38,14 @@ qcom,mdss-dsi-v-front-porch = <39>; qcom,mdss-dsi-v-pulse-width = <2>; qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + ]; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 04 df 97 51 e8 39 01 00 00 00 00 02 de 00 @@ -194,6 +202,181 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@1 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 34 c6 00 12 8a 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + ]; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 8a 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 4f5920b47a68..9ca4fb4a028a 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -504,12 +504,19 @@ &dsi_sharp_qhd_plus_dsc_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { - timing@0 { + timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 06 06 02 04 00 13 0a]; qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; + + timing@1 { /* 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; }; }; From 613384e2bc645875009a6295ddcce1b029f55741 Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Tue, 19 May 2020 13:55:29 -0700 Subject: [PATCH 033/327] bindings: Documentation: add documentation for wb linear line width This change adds documentation for device tree entry to specify writeback maximum supported line width in case of linear formats. Change-Id: I7c68404cd066eec55b6114d84cc4fefdda94c03c --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 1aeb4b45759d..18e8bc6b76b5 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -119,6 +119,8 @@ Optional properties: for scaling purposes. - qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. - qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. +- qcom,sde-wb-linewidth-linear: A u32 value indicates the max line width + supported by WB for linear color formats. - qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. - qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for alpha blending. @@ -683,6 +685,7 @@ Example: qcom,sde-dest-scaler-size = <0x800>; qcom,sde-len = <0x100>; qcom,sde-wb-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-sspp-scale-size = <0x100>; qcom,sde-mixer-blendstages = <0x8>; qcom,sde-qseed-type = "qseedv2"; From c1bbbfa4fded5d2cccf62ba6f5e5ef5e818c9f54 Mon Sep 17 00:00:00 2001 From: Prabhanjan Kandula Date: Tue, 19 May 2020 13:49:27 -0700 Subject: [PATCH 034/327] ARM: dts: msm: add wb max width for linear formats on lahaina This change adds maximum line width supported by WB for linear color formats on lahaina target. Change-Id: I0ef7a2a725053d69205f42744e2e732de4c1f257 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6f122c8748c6..81d823581b43 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -161,6 +161,7 @@ qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <4096>; qcom,sde-wb-linewidth = <4096>; + qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-mixer-blendstages = <0xb>; qcom,sde-highest-bank-bit = <0x3>; qcom,sde-ubwc-version = <0x400>; From cd1a8070798983bfe494214c36121249084df6b8 Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Tue, 26 May 2020 14:30:43 -0700 Subject: [PATCH 035/327] bindings: Documentation: add USB PHY device for DisplayPort client Add a reference to the usb_qmp_dp_phy device for use in the DisplayPort driver. This will be used to register for USB cable connect and disconnect events. Change-Id: I7d15dc04bde4e54c1007ee078d56c623b3453339 --- bindings/sde-dp.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index 75bd9a52355f..fe55491f448d 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -77,6 +77,7 @@ DP Controller: Required properties: - qcom,altmode-dev: Phandle for the AltMode GLink driver. - usb-controller: Phandle for the USB controller. - qcom,pll-revision: PLL hardware revision. +- usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events. - qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. - qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. - qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. From eaf5516a875814aaa38f5c7fc55fcbea69addb6c Mon Sep 17 00:00:00 2001 From: Tatenda Chipeperekwa Date: Fri, 22 May 2020 12:41:34 -0700 Subject: [PATCH 036/327] ARM: dts: msm: add USB PHY device for DisplayPort client on Lahaina Add a reference to the usb_qmp_dp_phy device for use in the DisplayPort driver. This will be used to register for USB cable connect and disconnect events. Change-Id: I0bb05815ccf17eca4f5148a48af20bac5b91e5fb --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 6f122c8748c6..3e32041de76a 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -324,6 +324,7 @@ cell-index = <0>; compatible = "qcom,dp-display"; + usb-phy = <&usb_qmp_dp_phy>; qcom,dp-aux-switch = <&fsa4480>; qcom,ext-disp = <&ext_disp>; qcom,altmode-dev = <&altmode 0>; From 912ae67e60aaee8a0283c20a01cb02778f0de0a8 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Fri, 29 May 2020 14:22:38 -0700 Subject: [PATCH 037/327] ARM: dts: msm: add proxy supply property to GPIO controlled regulator The change adds proxy supply entries to the GPIO controlled regulator display_panel_avdd. It is necessary to add the regulator to the proxy consumer list along with the regulator-boot-on property as this is the only way to ensure that the vote on the regulator stays on till the display driver is probed. Change-Id: I955834dcd0ee93646c5700f7d174931d1b0f5ba7 --- display/lahaina-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 9ca4fb4a028a..11a2d8ef4db6 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -122,6 +122,8 @@ gpio = <&tlmm 12 0>; enable-active-high; regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; From 584dd5e6453cabd8511bfc50daf8ea1dfa19b6e7 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 30 Apr 2020 15:50:12 +0800 Subject: [PATCH 038/327] ARM: dts: msm: update brightness setting for panels on Lahaina In general brightness value, the first parameter is low byte and the second is high byte, but some DDIC invert, so add brightness setting for inverted display brightness value for r66451 display panel. Change-Id: I2662e449b8902fce8e696661e1400893ab532b9a --- display/lahaina-sde-display-cdp.dtsi | 2 ++ display/lahaina-sde-display-mtp.dtsi | 2 ++ display/lahaina-sde-display-qrd.dtsi | 2 ++ 3 files changed, 6 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 3597392d094b..2061e5db40b0 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -27,6 +27,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-sec-reset-gpio = <&tlmm 25 0>; @@ -38,6 +39,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 67eab860d2d8..dfae6039ca0f 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -25,6 +25,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -35,6 +36,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 913eb806336b..bb711e419e3c 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -6,6 +6,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -16,6 +17,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; From c54990dae1101d01914424dc1e36f1daf2706a79 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 30 Apr 2020 15:54:22 +0800 Subject: [PATCH 039/327] dt-bindings: Add documentation for display brightness property setting Add a boolean to specify whether to invert the display brightness value. Change-Id: I28de475db2be036c441a6af5f9becc425eba991f --- bindings/mdss-dsi-panel.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 73cf79d6611e..9fee318fbeb2 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -199,6 +199,8 @@ Optional properties: 0 = default value. - qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel. 255 = default value. +- qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. + When this boolean is set, will inverted display brightness value. - qcom,mdss-brightness-max-level: Specifies the max brightness level supported. 255 = default value. - qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. From 8614170877105951a1d32d566f075be7f7be0e94 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Mon, 11 May 2020 16:22:03 +0800 Subject: [PATCH 040/327] ARM: dts: msm: rename the panel dtsi file for qrd lahaina This panel is a FHD+, not a QHD, so rename the file name. Change-Id: Ied238ffadb9c454510f773bf4a8cab873151056c --- ...sc-qhd-cmd.dtsi => dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi} | 2 +- ...hd-video.dtsi => dsi-panel-r66451-dsc-fhd-plus-video.dtsi} | 2 +- display/lahaina-sde-display.dtsi | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) rename display/{dsi-panel-r66451-dsc-qhd-cmd.dtsi => dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi} (99%) rename display/{dsi-panel-r66451-dsc-qhd-video.dtsi => dsi-panel-r66451-dsc-fhd-plus-video.dtsi} (97%) diff --git a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi similarity index 99% rename from display/dsi-panel-r66451-dsc-qhd-cmd.dtsi rename to display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index c1caaf5afd7a..fd53d15d6390 100644 --- a/display/dsi-panel-r66451-dsc-qhd-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_cmd: qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd { qcom,mdss-dsi-panel-name = - "r66451 amoled cmd mode dsi visionx panel with DSC"; + "r66451 amoled cmd mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,mdss-dsi-virtual-channel-id = <0>; diff --git a/display/dsi-panel-r66451-dsc-qhd-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi similarity index 97% rename from display/dsi-panel-r66451-dsc-qhd-video.dtsi rename to display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 9b86cfa0323c..2201ce22808e 100644 --- a/display/dsi-panel-r66451-dsc-qhd-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_video { qcom,mdss-dsi-panel-name = - "r66451 amoled video mode dsi visionx panel with DSC"; + "r66451 amoled video mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 9ca4fb4a028a..e02e4c5167e0 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -11,10 +11,10 @@ #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" -#include "dsi-panel-r66451-dsc-qhd-cmd.dtsi" -#include "dsi-panel-r66451-dsc-qhd-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" From 9cc23ddd91896a810f55287fcbdd1298794a8fd5 Mon Sep 17 00:00:00 2001 From: Rajkumar Subbiah Date: Tue, 2 Jun 2020 18:48:51 -0400 Subject: [PATCH 041/327] ARM: dts: msm: reduce dsc count to 2 for DP DP driver currently uses this value for number of DSCs available for external displays without allowing for DSI concurrency. This causes mode validation failures if DSI also needs to use DSCs. Limiting the DSC count to 2 for external display to allow for concurrencies. Change-Id: If760c609c1f304af77f825e211343277ff8d3fe2 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 24e47646458b..8d61e93d2d65 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -387,7 +387,7 @@ qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <4>; + qcom,max-dp-dsc-blks = <2>; qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; From 823497df904c43dc0bbb8385417066bee461eaa8 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Tue, 24 Mar 2020 17:52:21 -0400 Subject: [PATCH 042/327] ARM: dts: msm: Uprev DSPP IGC to version 4.0 on Lahaina target Update the DSPP IGC version to 4.0 for Lahaina family Change-Id: I13ba4b9a9160a6ff4b5f64d1fcaf8f33c16a1328 --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 24e47646458b..e2114c3078f1 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -281,7 +281,7 @@ }; qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x1260 0x00030002>; + qcom,sde-dspp-igc = <0x1260 0x00040000>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; From cdb6907875a43d06d0ad17d39ffb2e68b44733b8 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Thu, 4 Jun 2020 10:17:16 -0700 Subject: [PATCH 043/327] ARM: dts: msm: enable io coherency on unsecure cb for Lahaina Enable io coherency for non-secure context bank for lahaina target. This support is not needed for secure context bank because secure cb only maps secure buffers which are not cpu accessible. Change-Id: If693842c68fa714c6eee5c62437432ffbe80f749 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 24e47646458b..5204abeb9c49 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -662,6 +662,7 @@ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent-hint-cached; }; smmu_sde_sec: qcom,smmu_sde_sec_cb { From bcc269cfa0f9fcf178c4ddf23f9664d6e4e3fac4 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Mon, 1 Jun 2020 15:02:31 +0800 Subject: [PATCH 044/327] ARM: dts: msm: change init sequence for r66451 panel DDIC R66451 cmd mode dynamic fps switch only can work based on 120hz initial parameters. Changed 60hz and 90hz initial parameters based on 120hz, so that DFPS can work on all the FPS. Change-Id: I94c377c605c2eb50fb9ec494f5987272297e6a1e --- .../dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 90 ++++++++++++++++--- 1 file changed, 80 insertions(+), 10 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index fd53d15d6390..dc7a7f908ba1 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -62,17 +62,46 @@ qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 13 d8 00 00 00 00 00 - 00 00 00 00 5b 00 5b 00 5b 00 5b 00 - 5b + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 @@ -83,6 +112,10 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; @@ -129,14 +162,47 @@ ]; qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 @@ -147,6 +213,10 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; From 9b61cc832a8284b18845a6aec4cf2600c4966e4c Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Mon, 8 Jun 2020 12:08:52 -0700 Subject: [PATCH 045/327] ARM: dts: msm: set nom MDP clock during cont-splash Set nominal MDP clock during cont-splash usecase to support higher FPS usecases. Change-Id: Iabcb5ab01a2cd3b227cee2d80ef6fee14b257c2d --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8d61e93d2d65..e162628d6adb 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -29,7 +29,7 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>; + clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>; clock-max-rate = <0 0 0 0 460000000 19200000 460000000 460000000>; From 83b937427ef76c2ccb338e8ff13020f7ebdefa2b Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Wed, 27 May 2020 09:45:45 -0400 Subject: [PATCH 046/327] dt-bindings: Move documentation for DSC line width to SDE node Add an u32 value to specify the DSC maximum linewidth hardware restriction in SDE node and remove unused DSC nodes from DP driver. Change-Id: I7439efba350c6a70c371f9aaec7cf61b9c15b3c8 --- bindings/sde-dp.txt | 4 ---- bindings/sde.txt | 2 ++ 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index fe55491f448d..567cbd7dd81b 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -72,8 +72,6 @@ DP Controller: Required properties: - qcom,mst-enable: MST feature enable control node. - qcom,dsc-feature-enable: DSC feature enable control node. - qcom,fec-feature-enable: FEC feature enable control node. -- qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port. -- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block. - qcom,altmode-dev: Phandle for the AltMode GLink driver. - usb-controller: Phandle for the USB controller. - qcom,pll-revision: PLL hardware revision. @@ -199,8 +197,6 @@ sde_dp: qcom,dp_display@0 { qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; diff --git a/bindings/sde.txt b/bindings/sde.txt index 18e8bc6b76b5..cf824c15d47d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -236,6 +236,7 @@ Optional properties: - qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc block can support native 422 and native 420 encoding. +- qcom,sde-dsc-linewidth: A u32 value indicates the max dsc line width. - qcom,sde-vdc-off: A u32 offset address for the available vdc blocks. This offset is calculated from register "mdp_phys" defined in reg property. @@ -661,6 +662,7 @@ Example: qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2560>; qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-dsc-linewidth = <2048>; qcom,sde-highest-bank-bit = <0x2>; qcom,sde-ubwc-version = <0x100>; qcom,sde-ubwc-static = <0x100>; From b02bb447adb29df81584234d3d009c621fa5522b Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Thu, 28 May 2020 12:58:52 -0400 Subject: [PATCH 047/327] ARM: dts: msm: Move DSC hardware properties to SDE node Move DSC related hardware properties to SDE node since DSC block is managed by SDE driver. Change-Id: I4d923bdc6fa8f53e5f2eeb49657ef03b8ef8c352 --- display/lahaina-sde.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 8d61e93d2d65..dde5951caedb 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -107,6 +107,7 @@ qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; qcom,sde-dsc-ctl-size = <0x10>; qcom,sde-dsc-native422-supp = <0 0 1 1>; + qcom,sde-dsc-linewidth = <2048>; qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; @@ -387,8 +388,6 @@ qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; From 834c56acb2faf4a5f49beef832130bfdab895105 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Thu, 11 Jun 2020 14:37:41 -0700 Subject: [PATCH 048/327] bindings: Documentation: rename qseed_type binding Rename sde-qseed-type property to sde-qseed-sw-lib-rev to indicate that it represents the sw library version supporting the qseed hw. Change-Id: I0f29c6e99d9e7f0dc322dddb516cdc6938b33eb2 --- bindings/sde.txt | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index cf824c15d47d..dc5649953226 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -124,10 +124,11 @@ Optional properties: - qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. - qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for alpha blending. -- qcom,sde-qseed-type: A string entry indiates qseed support on sspp and wb. - It supports "qssedv3" and "qseedv2" entries for qseed - type. By default "qseedv2" is used if this optional property - is not defined. +- qcom,sde-qseed-sw-lib-rev: A string entry indicates qseed sw library revision + supporting the qseed HW block. It supports + "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed + revision. By default "qseedv2" is used if this + optional property is not defined. - qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. It supports "csc" and "csc-10bit" entries for csc type. @@ -690,7 +691,7 @@ Example: qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-sspp-scale-size = <0x100>; qcom,sde-mixer-blendstages = <0x8>; - qcom,sde-qseed-type = "qseedv2"; + qcom,sde-qseed-sw-lib-rev = "qseedv2"; qcom,sde-csc-type = "csc-10bit"; qcom,sde-highest-bank-bit = <15>; qcom,sde-has-mixer-gc; From 6095e73ad131f6cc93530201da8a3136a195632d Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 2 Jun 2020 12:22:27 -0700 Subject: [PATCH 049/327] ARM: dts: msm: rename qseed type property Rename sde-qseed-type property to sde-qseed-sw-lib-rev to indicate that it represents the sw library version supporting the qseed hw. Change-Id: Ie5dfd00714381d2ccdc319932562b5e25f4b781c --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 80451ce012c8..523452d24cfa 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -157,7 +157,7 @@ <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <4096>; From 299dbe802a4433cd9186c8cd5a2943d83ff34682 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 2 Jun 2020 13:17:34 -0700 Subject: [PATCH 050/327] bindings: Documentation: add a property for QSEED HW revision Add a SDE property for QSEED HW block revision. Change-Id: I1380c76a9f631267a9726f3b4d86fe3b2560c04c --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index dc5649953226..8c1ec8cf4bcf 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -129,6 +129,8 @@ Optional properties: "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed revision. By default "qseedv2" is used if this optional property is not defined. +- qcom,sde-qseed-scalar-version: A u32 value indicating the HW version of the + QSEED hardware block - qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. It supports "csc" and "csc-10bit" entries for csc type. @@ -692,6 +694,7 @@ Example: qcom,sde-sspp-scale-size = <0x100>; qcom,sde-mixer-blendstages = <0x8>; qcom,sde-qseed-sw-lib-rev = "qseedv2"; + qcom,sde-qseed-scalar-version = <0x3000>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-highest-bank-bit = <15>; qcom,sde-has-mixer-gc; From 330e0bdd963074e28e541bf452ef4fdda814eec7 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Thu, 11 Jun 2020 14:42:42 -0700 Subject: [PATCH 051/327] ARM: dts: msm: add a property for QSEED HW revision Add a SDE property for QSEED HW block revision for lahaina. Change-Id: Ie8623d013a623427a2318c537097c2a109f73768 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 523452d24cfa..e222e35f2b30 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -158,6 +158,7 @@ qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <4096>; From b34cf56a835ddfdba7bc343b28f873cea129ff0f Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Mon, 15 Jun 2020 10:14:50 -0700 Subject: [PATCH 052/327] ARM: dts: msm: update irq latency for mdss irq on lahaina target Update irq latency node for lahaina target in SDE driver for mdss irq. Change-Id: Id19d3abd34454d1a8d1e43a7a0bc62daa750011c --- bindings/sde.txt | 2 ++ display/lahaina-sde.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index cf824c15d47d..423532d1ac04 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -473,6 +473,7 @@ Optional properties: 0xf represents 4 cpu cores. These cores can be silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. +- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -740,6 +741,7 @@ Example: qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index a48726e69e2f..66286ea86fee 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -232,6 +232,7 @@ qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; /* offsets are relative to "mdp_phys + qcom,sde-off */ From 904c02f2a5d1837affd21c40bb24386bd311827f Mon Sep 17 00:00:00 2001 From: Gopikrishnaiah Anandan Date: Mon, 15 Jun 2020 16:38:28 -0700 Subject: [PATCH 053/327] ARM: dts: msm: Add hdr capabilities to r66451 panel Add hdr capabilities to the panel dtsi so that DPU can support the tone mapping for HDR video playback use-cases. Change-Id: I3a121b54861e882bb93a1735a9f39cdafe5144f6 --- display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index dc7a7f908ba1..9f31efd5478f 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -35,6 +35,9 @@ qcom,mdss-dsi-te-dcs-command = <1>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-framerate = <60>; From 26185625a2565cfb212491d2205f8d4542b9b9f1 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Wed, 17 Jun 2020 15:48:15 -0700 Subject: [PATCH 054/327] ARM: dts: msm: add clk status register for lahaina target Add sspp and wb2 clock active status register and bit offset index for lahaina target. This is required to check hw blocks' idle vs busy status. Change-Id: I0834a267e8c4f007a92da0852e33b1e0e02de226 --- bindings/sde.txt | 12 ++++++++++-- display/lahaina-sde.dtsi | 4 ++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index a29dc87f2b61..93e968a01ab9 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -178,10 +178,10 @@ Optional properties: match the number of offsets defined in property: qcom,sde-sspp-off - qcom,sde-sspp-clk-status: Array of offsets describing clk status - offsets for dynamic clock gating. 1st value + offsets for clock active state. 1st value in the array represents offset of the status register. 2nd value represents bit offset within - control register. Number of offsets defined should + status register. Number of offsets defined should match the number of offsets defined in property: qcom,sde-sspp-off. - qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle @@ -359,6 +359,13 @@ Optional properties: control register. Number of offsets defined should match the number of offsets defined in property: qcom,sde-wb-off +- qcom,sde-wb-clk-status: Array of 2 cell property describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off - qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, relative to "regdma_phys" defined in reg property. - qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the @@ -724,6 +731,7 @@ Example: qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 90de1c6c2365..e7d0bc65d019 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -79,6 +79,7 @@ qcom,sde-wb-xin-id = <6>; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; @@ -155,6 +156,9 @@ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>, + <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>; qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; From 8cfaeff2086aaf4c195faecfcc18781811649b55 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Fri, 19 Jun 2020 23:59:29 -0700 Subject: [PATCH 055/327] ARM: dts: msm: create sde-common device tree on lahaina target Separate and maintain common SDE bindings in sde-common dt file(s). It avoids unwanted duplications between VM variants of the SDE files. It also helps developers with single-dt update for bindings applicable to all the VM's for Lahaina target. For easy maintenance, the recommendation would be to add any VM specific bindings in VM DT files instead of adding them to common DT and use "delete-property" operator to update the VM DT file. Change-Id: I8eaae7355b1c44138d6e032e3cf26f44069bc843 --- display/lahaina-sde-common.dtsi | 370 +++++++++++ display/lahaina-sde-display-common.dtsi | 718 +++++++++++++++++++++ display/lahaina-sde-display.dtsi | 787 +++--------------------- display/lahaina-sde.dtsi | 627 +++++-------------- 4 files changed, 1305 insertions(+), 1197 deletions(-) create mode 100644 display/lahaina-sde-common.dtsi create mode 100644 display/lahaina-sde-display-common.dtsi diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi new file mode 100644 index 000000000000..8dd8954df0c3 --- /dev/null +++ b/display/lahaina-sde-common.dtsi @@ -0,0 +1,370 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000 + 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000 0x1b000>; + qcom,sde-ctl-size = <0x1e8>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "cwb", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x35000 0x36000 + 0x37000 0x38000>; + qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 + 0x6c000 0x6d000 0x6e000 0x6f000>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>; + qcom,sde-merge-3d-size = <0x10>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>; + qcom,sde-dsc-size = <0x10>; + qcom,sde-dsc-pair-mask = <2 1 4 3>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; + qcom,sde-dsc-ctl-size = <0x10>; + qcom,sde-dsc-native422-supp = <0 0 1 1>; + qcom,sde-dsc-linewidth = <2048>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 + 0xe0 0xe0 0xe0>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0x10>; + qcom,sde-vdc-hw-rev = "vdc_1_2"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-enc-size = <0x1C8>; + qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-vdc-ctl-size = <0x10>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 4 8 12 + 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000 + 3900000 3900000 + 3900000 3900000 + 3900000 3900000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000 + 5200000 5200000 + 5200000 5200000 + 5200000 5200000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>, + <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-wb-linewidth-linear = <5120>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x3>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <11800000>; + qcom,sde-max-bw-high-kbps = <15500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>; + + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x4000821>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.5"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.5"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi new file mode 100644 index 000000000000..7059407c5de6 --- /dev/null +++ b/display/lahaina-sde-display-common.dtsi @@ -0,0 +1,718 @@ +#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" +#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" +#include "dsi-panel-sharp-1080p-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include +#include "dsi-panel-sim-vdc-vid.dtsi" +#include "dsi-panel-sim-vdc-cmd.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <182000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + qcom,mdp = <&mdss_mdp>; + }; +}; + +/* PHY TIMINGS REVISION YC with reduced margins*/ +&dsi_sw43404_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + }; +}; + +&dsi_sw43404_amoled_video { + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_1080_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 00 1a 0c]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-panel-clockrate = <900000000>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 + 03 02 02 04 00 0b 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* WQHD 60FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* FHD 60FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* WQHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 + 04 03 02 04 00 0e 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* WQHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* WQHD 120FPS VID */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 120FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* FHD 90FPS CMD */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qsync_wqhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + /* DPHY regular margins */ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06 + 06 07 02 04 00 17 16 ]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_video { + qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <53>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + /* DPHY regular margins */ + qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07 + 07 07 02 04 00 18 16]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 + 06 04 02 04 00 12 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 + 06 04 02 04 00 12 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 + 06 04 02 04 00 12 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 0d 0c 08 + 08 05 02 04 00 17 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@4 { /* HD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vdc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vdc_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 00 04 04 08 07 05 + 05 03 02 04 00 0e 09]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 + 02 01 02 04 00 08 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 1080 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 11 10 1b 17 11 + 11 0c 02 04 00 30 15]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 + 04 02 02 04 00 0c 08]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 03 03 05 05 03 + 03 01 02 04 00 0a 08]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 + 07 07 04 02 00 14 0b]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 + 05 03 02 04 00 10 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08 + 08 05 02 04 00 16 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4k 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01 + 01 01 02 04 00 05 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 + 02 01 02 04 00 08 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 + 04 02 02 04 00 0c 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02 + 01 00 02 04 00 06 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 + 03 01 02 04 00 09 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04 + 04 02 02 04 00 0c 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 + 05 03 02 04 00 0f 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 + 07 04 02 04 00 14 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01 + 01 00 02 04 00 04 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02 + 02 01 02 04 00 07 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03 + 03 01 02 04 00 08 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index b1408df87ce8..4e0465985d59 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -1,32 +1,4 @@ -#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" -#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" -#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" -#include "dsi-panel-sharp-dsc-4k-video.dtsi" -#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" -#include "dsi-panel-sharp-1080p-cmd.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" -#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" -#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-ext-bridge-1080p.dtsi" -#include "dsi-panel-sim-cmd.dtsi" -#include "dsi-panel-sim-video.dtsi" -#include "dsi-panel-sim-dsc375-cmd.dtsi" -#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" -#include "dsi-panel-sim-dualmipi-cmd.dtsi" -#include "dsi-panel-sim-dualmipi-video.dtsi" -#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" -#include "dsi-panel-sim-sec-hd-cmd.dtsi" -#include -#include "dsi-panel-sim-vdc-vid.dtsi" -#include "dsi-panel-sim-vdc-cmd.dtsi" +#include "lahaina-sde-display-common.dtsi" &tlmm { display_panel_avdd_default: display_panel_avdd_default { @@ -45,74 +17,6 @@ }; &soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <60700>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <10000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - - qcom,panel-supply-entry@3 { - reg = <3>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <182000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "avdd"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - }; - display_panel_avdd: display_gpio_regulator@1 { compatible = "regulator-fixed"; regulator-name = "display_panel_avdd"; @@ -128,89 +32,6 @@ pinctrl-0 = <&display_panel_avdd_default>; }; - sde_dsi: qcom,dsi-display-primary { - compatible = "qcom,dsi-display"; - label = "primary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1", - "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 82 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - avdd-supply = <&display_panel_avdd>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; - - qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; - }; - - sde_dsi1: qcom,dsi-display-secondary { - compatible = "qcom,dsi-display"; - label = "secondary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; - - qcom,platform-te-gpio = <&tlmm 83 0>; - qcom,panel-te-source = <1>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - avdd-supply = <&display_panel_avdd>; - - qcom,mdp = <&mdss_mdp>; - }; - sde_wb: qcom,wb-display@0 { compatible = "qcom,wb-display"; cell-index = <0>; @@ -218,30 +39,88 @@ }; }; +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + avdd-supply = <&display_panel_avdd>; +}; + &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; -/* PHY TIMINGS REVISION YC with reduced margins*/ &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + qcom,esd-check-enabled; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 - 05 06 02 04 00 12 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 180 180 180 1440 180>; }; @@ -249,236 +128,86 @@ }; &dsi_sw43404_amoled_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-qsync-min-refresh-rate = <55>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 - 05 06 02 04 00 12 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_r66451_amoled_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_r66451_amoled_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 - 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_r66451_amoled_cmd_cphy { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 - 19 03 02 04 00 00 00]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_r66451_amoled_video_cphy { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 - 19 03 02 04 00 00 00]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x77>; qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_4k_dsc_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x77>; qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 - 06 07 02 04 00 15 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_1080_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 - 08 08 02 04 00 1a 0c]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - qcom,mdss-dsi-panel-clockrate = <900000000>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sharp_qsync_wqhd_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,esd-check-enabled; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 - 03 02 02 04 00 0b 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 8 8 8 1440 8>; }; - - timing@1 { /* WQHD 60FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@2 { /* FHD 60FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 - 02 01 02 04 00 09 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 8 8 8 1080 8>; }; - timing@3 { /* WQHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 11 1e 04 - 04 03 02 04 00 0e 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 8 8 8 1440 8>; }; - timing@4 { /* WQHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 8 8 8 1440 8>; }; - - timing@5 { /* WQHD 120FPS VID */ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@6 { /* FHD 120FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 10 03 - 03 02 02 04 00 0c 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 8 8 8 1080 8>; }; - timing@7 { /* FHD 90FPS CMD */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 - 02 02 02 04 00 0a 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 8 8 8 1080 8>; }; @@ -486,448 +215,88 @@ }; &dsi_sharp_qsync_wqhd_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 - 05 06 02 04 00 12 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qhd_plus_dsc_cmd { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 - 06 06 02 04 00 13 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 - 07 07 02 04 00 17 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_dual_nt35597_truly_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - /* - * DPHY regular margins - */ - qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06 - 06 07 02 04 00 17 16 ]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_dual_nt35597_truly_video { - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <60 57 55>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-min-refresh-rate = <53>; - qcom,mdss-dsi-max-refresh-rate = <60>; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 - 07 08 02 04 00 18 0c]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_nt35695b_truly_fhd_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - /* - * DPHY regular margins - */ - qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07 - 07 07 02 04 00 18 16]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; + qcom,esd-check-enabled; }; &dsi_sim_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,poms-align-panel-vsync; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 - 06 04 02 04 00 12 0a]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <720 40 720 40 720 40>; qcom,partial-update-enabled = "single_roi"; }; - - timing@1 { /* WQHD 60FPS vid mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 15 06 05 0a 09 06 - 06 04 02 04 00 12 0a]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - }; - timing@2 { /* WQHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 15 06 06 0a 09 06 - 06 04 02 04 00 12 0b]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <720 40 720 40 720 40>; qcom,partial-update-enabled = "single_roi"; }; - timing@3 { /* FHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 0d 0c 08 - 08 05 02 04 00 17 0c]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <540 40 540 40 540 40>; qcom,partial-update-enabled = "single_roi"; }; - timing@4 { /* HD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 24 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; qcom,panel-roi-alignment = <360 40 360 40 360 40>; qcom,partial-update-enabled = "single_roi"; }; }; }; -&dsi_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <1 0 1>, - <2 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_vdc_cmd { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 1 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_vdc_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 1 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - &dsi_sim_dsc_375_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 1080p */ - qcom,mdss-dsi-panel-phy-timings = [00 00 04 04 08 07 05 - 05 03 02 04 00 0e 09]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* qhd */ - qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 - 02 01 02 04 00 08 07]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - }; }; &dsi_sim_dsc_10b_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* QHD 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 1080 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - - timing@2 { /* QHD 90fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_dual_sim_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,mdss-dsi-display-timings { - timing@0 { /* 5K 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 3d 11 10 1b 17 11 - 11 0c 02 04 00 30 15]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* FHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 - 04 02 02 04 00 0c 08]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* WQHD 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 0a 03 03 05 05 03 - 03 01 02 04 00 0a 08]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4K 60FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 13 05 05 09 08 05 - 05 03 02 04 00 10 0a]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 - 07 07 04 02 00 14 0b]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_dual_sim_dsc_375_cmd { qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { /* 4k 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 4k 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 - 05 03 02 04 00 10 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 4k 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08 - 08 05 02 04 00 16 0c]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4k 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@4 { /* 1080 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01 - 01 01 02 04 00 05 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@5 { /* 1080 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 - 02 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* 1080 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@7 { /* 1080 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 - 04 02 02 04 00 0c 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@8 { /* qhd 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02 - 01 00 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@9 { /* qhd 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@10 { /* qhd 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04 - 04 02 02 04 00 0c 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@11 { /* qhd 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@12 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 - 07 04 02 04 00 14 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@13 { /* 720p 30 FPS */ - qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01 - 01 00 02 04 00 04 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@14 { /* 720p 60 FPS */ - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@15 { /* 720p 90 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02 - 02 01 02 04 00 07 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@16 { /* 720 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03 - 03 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@17 { /* 1080 144FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 - 06 06 02 04 00 13 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_sim_sec_hd_cmd { qcom,ulps-enabled; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; qcom,panel-roi-alignment = <720 40 720 40 720 40>; qcom,partial-update-enabled = "single_roi"; }; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index f57ce9ddca21..4aa15c2d2e45 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -1,3 +1,4 @@ +#include "lahaina-sde-common.dtsi" #include &soc { @@ -6,316 +7,6 @@ label = "disp_rdump_region"; }; - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0x0ae00000 0x84000>, - <0x0aeb0000 0x2008>, - <0x0aeac000 0x800>, - <0x0af50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - - clocks = - <&clock_gcc GCC_DISP_AHB_CLK>, - <&clock_gcc GCC_DISP_HF_AXI_CLK>, - <&clock_gcc GCC_DISP_SF_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000 - 460000000>; - - mmcx-supply = <&VDD_MMCX_LEVEL>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x16000 0x17000 0x18000 - 0x19000 0x1a000 0x1b000>; - qcom,sde-ctl-size = <0x1e8>; - qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 - 0x48000 0x49000 0x4a000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none", "none", "none"; - - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", - "cwb", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dspp-rc-version = <0x00010000>; - qcom,sde-dspp-rc-off = <0x15800 0x14c00>; - qcom,sde-dspp-rc-size = <0x100>; - qcom,sde-dspp-rc-mem-size = <2720>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-intf-off = <0x35000 0x36000 - 0x37000 0x38000>; - qcom,sde-intf-size = <0x2c0>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; - - qcom,sde-pp-off = <0x6a000 0x6b000 - 0x6c000 0x6d000 0x6e000 0x6f000>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; - - qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>; - qcom,sde-merge-3d-size = <0x10>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>; - qcom,sde-dsc-size = <0x10>; - qcom,sde-dsc-pair-mask = <2 1 4 3>; - qcom,sde-dsc-hw-rev = "dsc_1_2"; - qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>; - qcom,sde-dsc-enc-size = <0x100>; - qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>; - qcom,sde-dsc-ctl-size = <0x10>; - qcom,sde-dsc-native422-supp = <0 0 1 1>; - qcom,sde-dsc-linewidth = <2048>; - - qcom,sde-dither-off = <0xe0 0xe0 0xe0 - 0xe0 0xe0 0xe0>; - qcom,sde-dither-version = <0x00020000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-vdc-off = <0x7C000>; - qcom,sde-vdc-size = <0x10>; - qcom,sde-vdc-hw-rev = "vdc_1_2"; - qcom,sde-vdc-enc = <0x200>; - qcom,sde-vdc-enc-size = <0x1C8>; - qcom,sde-vdc-ctl = <0xf00>; - qcom,sde-vdc-ctl-size = <0x10>; - - qcom,sde-sspp-type = "vig", "vig", "vig", "vig", - "dma", "dma", "dma", "dma"; - - qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 - 0x25000 0x27000 0x29000 0x2b000>; - qcom,sde-sspp-src-size = <0x1f8>; - - qcom,sde-sspp-xin-id = <0 4 8 12 - 1 5 9 13>; - qcom,sde-sspp-excl-rect = <1 1 1 1 - 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000 - 3900000 3900000 - 3900000 3900000 - 3900000 3900000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000 - 5200000 5200000 - 5200000 5200000 - 5200000 5200000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = - <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; - qcom,sde-sspp-clk-status = - <0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>, - <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <4096>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-wb-linewidth-linear = <5120>; - qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x3>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-has-idle-pc; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <11800000>; - qcom,sde-max-bw-high-kbps = <15500000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <800000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010001>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x15300 0x14300>; - - qcom,sde-dspp-spr-off = <0x15400 0x14400>; - qcom,sde-dspp-spr-size = <0x200>; - qcom,sde-dspp-spr-version = <0x00010000>; - - qcom,sde-dspp-demura-off = <0x15600 0x14800>; - qcom,sde-dspp-demura-size = <0x200>; - qcom,sde-dspp-demura-version = <0x00010000>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>; - - qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff - 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - - qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; - qcom,sde-qos-refresh-rates = <60 120>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0 0x400>; - qcom,sde-reg-dma-id = <0 1>; - qcom,sde-reg-dma-version = <0x00020000>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x4000821>; - - /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 74000>, - <0 148000>, - <0 265000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060001>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x1260 0x00040000>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040003>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "mmcx"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - }; - ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; @@ -483,184 +174,6 @@ "qcom,sde-ebi-bus"; }; - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.5"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <800>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.5"; - label = "dsi-ctrl-1"; - cell-index = <1>; - frame-threshold-time-us = <800>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L5B>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - memory-region = <&dfps_data_memory>; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-1"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96400 0x800>, - <0xae96900 0x27c>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L5B>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { compatible = "qcom,smmu_sde_unsec"; iommus = <&apps_smmu 0x820 0x402>; @@ -677,5 +190,143 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; +}; + +&mdss_mdp { + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + + mmcx-supply = <&VDD_MMCX_LEVEL>; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010001>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L5B>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L5B>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; From 95ee4a9fabb57e92a411560e065604d5b7e47191 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Tue, 7 Jul 2020 12:44:07 +0800 Subject: [PATCH 056/327] ARM: dts: msm: fix the ESD check error for r66451 panel 60hz could not display and took ESD check failed on some qrd devices. Changed the panel init sequence, doing 60hz and 90hz fps switch after ddic power on(29 command). Change-Id: I00316ab9dbecf7394cba309c33d10bec96e170d1 --- display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index 9f31efd5478f..64b941df0e09 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -115,12 +115,12 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 09 3c 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 ]; qcom,mdss-dsi-off-command = [ @@ -216,12 +216,12 @@ 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 1a c2 09 24 0c 00 00 0c 03 14 00 09 3c 00 00 00 00 00 00 00 00 00 00 00 30 00 6c - 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 ]; qcom,mdss-dsi-off-command = [ @@ -318,7 +318,7 @@ 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 05 01 00 00 78 00 01 11 - 05 01 00 00 00 00 01 29 + 05 01 00 00 14 00 01 29 ]; qcom,mdss-dsi-off-command = [ From 7e9927d6f3b8e5dc2dc6c4b48f60b7faeb1e5a96 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Wed, 27 May 2020 11:13:37 -0700 Subject: [PATCH 057/327] ARM: dts: msm: batch timing switch commands together for qsync panel Batch the timing switch commands, to be triggered all at once for Sharp qsync command mode panel for lahaina target. Change-Id: Ife397d3e73c2872b77ee5a44e843846747292c26 --- display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 168 ++++++++++---------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi index 215b3ab46dde..d553b8711a6c 100644 --- a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi +++ b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi @@ -53,21 +53,21 @@ qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 83 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 0a + 39 00 00 00 00 00 02 17 30 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 01 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -274,21 +274,21 @@ qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 85 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 0a + 39 00 00 00 00 00 02 17 30 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 01 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -383,21 +383,21 @@ qcom,mdss-dsi-panel-framerate = <90>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 83 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 02 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 03 + 39 00 00 00 00 00 02 17 70 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 02 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -491,21 +491,21 @@ qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 83 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 03 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 00 + 39 00 00 00 00 00 02 17 10 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 03 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -712,21 +712,21 @@ qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 85 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 00 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 00 + 39 00 00 00 00 00 02 17 10 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 00 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; @@ -821,21 +821,21 @@ qcom,mdss-dsi-panel-framerate = <90>; qcom,mdss-dsi-panel-jitter = <0x3 0x1>; qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 c0 85 + 39 00 00 00 00 00 11 c1 89 28 00 08 02 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 02 - 15 01 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 03 c2 10 f0 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 16 03 + 39 00 00 00 00 00 02 17 70 + 39 00 00 00 00 00 02 ff 26 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 60 00 + 39 00 00 00 00 00 02 62 02 + 15 00 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 28 05 01 00 00 00 00 01 29 ]; From 0c374a672e17f6835fd70dbbeaa9f76d567ac271 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Tue, 30 Jun 2020 17:18:22 +0800 Subject: [PATCH 058/327] ARM: dts: msm: Complement hdr capabilities to r66451 panel Complement hdr capabilities to the panel dtsi for both cmd and vid mode so that DPU can support the tone mapping for HDR video playback use-cases. Change-Id: I711311027d47be71f9625289d7f8b8f8c60c14f2 --- display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi | 2 ++ display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi index 9f31efd5478f..e407253e7f16 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi @@ -38,6 +38,8 @@ qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-framerate = <60>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 2201ce22808e..c67a33b57cc8 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -22,6 +22,11 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-width = <1080>; From 4ac5619525b75e474dac1d7b4707fd6c072cb415 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 10 Jul 2020 11:29:02 +0530 Subject: [PATCH 059/327] bindings: Documentation: modify documentation for hbb This changes modifies the documentation for highest bank bit used for UBWC configuration. Change-Id: I4a35bf2330402b3d6680aa74344ea088cd6b2866 --- bindings/sde.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 93e968a01ab9..367633a93d3a 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -134,8 +134,10 @@ Optional properties: - qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. It supports "csc" and "csc-10bit" entries for csc type. -- qcom,sde-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory - bank bit used for tile format buffers. +- qcom,sde-highest-bank-bit: Property to specify GPU/Camera/Video highest memory + bank bit used for tile format buffers. First value + in the array represents the ddr type and the second + value is the hbb value corresponding to the ddr type. - qcom,sde-ubwc-version: Property to specify the UBWC feature version. - qcom,sde-ubwc-static: Property to specify the default UBWC static configuration value. @@ -674,7 +676,7 @@ Example: qcom,sde-sspp-linewidth = <2560>; qcom,sde-mixer-blendstages = <0x7>; qcom,sde-dsc-linewidth = <2048>; - qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-highest-bank-bit = <0x7 0x2>; qcom,sde-ubwc-version = <0x100>; qcom,sde-ubwc-static = <0x100>; qcom,sde-ubwc-swizzle = <0>; From 51c35b35f529db9d8b93bcb9d798b7694cbfd5a8 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Mon, 13 Jul 2020 18:24:24 +0530 Subject: [PATCH 060/327] ARM: dts: msm: add ddr type and hbb for lahaina target Add supported ddr types and corresponding hbb values for lahaina target. Change-Id: Ib4dd7781ce9ac8f0a1e66ae2d7528d897e348cc3 --- display/lahaina-sde-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 8dd8954df0c3..56b7f71adbee 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -148,7 +148,8 @@ qcom,sde-wb-linewidth = <4096>; qcom,sde-wb-linewidth-linear = <5120>; qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x3>; + qcom,sde-highest-bank-bit = <0x8 0x3>, + <0x7 0x2>; qcom,sde-ubwc-version = <0x400>; qcom,sde-ubwc-swizzle = <0x6>; qcom,sde-ubwc-bw-calc-version = <0x1>; From e08d91fbba053195eebcb73447dcfe96aa9ca195 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 14:52:00 -0700 Subject: [PATCH 061/327] ARM: dts: msm: move dsi ctrl power nodes to common dt for Lahaina Move DSI ctrl power handles nodes from lahaina HLOS dt to common dt file as they are needed by all the vm's. Change-Id: Id59f51e1e9e821bb5b02dd26ec41aff71950c306 --- display/lahaina-sde-common.dtsi | 54 ++++++++++++++++++++++++++++++++ display/lahaina-sde.dtsi | 55 --------------------------------- 2 files changed, 54 insertions(+), 55 deletions(-) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 8dd8954df0c3..bd93fb5130b3 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -280,6 +280,33 @@ reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { @@ -292,6 +319,33 @@ reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 4aa15c2d2e45..870528fae30e 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -247,33 +247,6 @@ <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi1 { @@ -287,34 +260,6 @@ <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi_phy0 { From ef6fabda4a5b30097f4103b8080d990bcbab264d Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Sat, 20 Jun 2020 00:15:04 -0700 Subject: [PATCH 062/327] ARM: dts: msm: add trusted vm dtsi files for Lahaina target Add trusted VM device tree files for Lahaina. These files inherit common Lahaina target bindings and overrides with needed bindings with VM specific values. Change-Id: Icb3090d1dfa6afe7eb993064e4493140708b658e --- display/trustedvm-lahaina-sde-display.dtsi | 33 +++++++++++ display/trustedvm-lahaina-sde.dtsi | 68 ++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 display/trustedvm-lahaina-sde-display.dtsi create mode 100644 display/trustedvm-lahaina-sde.dtsi diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi new file mode 100644 index 000000000000..036205f97d18 --- /dev/null +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -0,0 +1,33 @@ +#include "lahaina-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_MUX_1_CLK>, + <&clock_cpucc PCLK_MUX_1_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_1_CLK>, + <&clock_cpucc BYTECLK_SRC_1_CLK>, + <&clock_cpucc PCLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + qcom,panel-te-source = <0>; +}; + +&mdss_mdp { + connectors = <&sde_dsi>; +}; diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi new file mode 100644 index 000000000000..005a82796a64 --- /dev/null +++ b/display/trustedvm-lahaina-sde.dtsi @@ -0,0 +1,68 @@ +#include "lahaina-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>, + <0x0ae8f000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-hw-version =<0x70000000>; + + clocks = + <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_cpucc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From 5bd4516c99157317ccd6977440c2bcded088e0b8 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 14:59:41 -0700 Subject: [PATCH 063/327] bindings: Documentation: add property to indicate trusted VM execution Add a property in SDE device to indicate the executing environment is the trusted VM. Change-Id: Id4650d60f582b2058b166e69c2b0c66cdfce36e0 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 93e968a01ab9..6bad2544b4c9 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -517,6 +517,8 @@ Optional properties: ordering block 0: lower priority pipe has to be on the left for a given pair of pipes. 1: priority have to be explicitly configured for a given pair of pipes. +- qcom,sde-trusted-vm-env: Boolean property to indicate if the device + driver is executing in a trusted VM Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -728,6 +730,7 @@ Example: qcom,sde-te2-off = <0x100>; qcom,sde-te-size = <0xffff>; qcom,sde-te2-size = <0xffff>; + qcom,sde-trusted-vm-env; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; From 0f35dca90be9f19a674eb344d812e8913732b024 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Mon, 1 Jun 2020 17:17:02 -0700 Subject: [PATCH 064/327] ARM: dts: msm: add property for trusted VM execution for Lahaina Add a property in the display device to indicate the executing environment being a trusted VM for Lahaina target. Change-Id: Iaeeba1b83b8167accfdcb6bbe4f3fd930b891e52 --- display/trustedvm-lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index 005a82796a64..8ee259e82f95 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -35,6 +35,7 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; + qcom,sde-trusted-vm-env; }; &mdss_dsi0 { From 21bb257fd5f8243ef8121e2b699139f1d6d7dfe3 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:07:29 -0700 Subject: [PATCH 065/327] bindings: Documentation: add property to specify max trusted vm displays Add documentation for the property to specify the maximum number of concurrent displays supported in the trusted vm environment. Change-Id: I84c0408686e816a6498931949b7391209c9f9640 --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 6bad2544b4c9..635cefcd2ad7 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -519,6 +519,9 @@ Optional properties: 1: priority have to be explicitly configured for a given pair of pipes. - qcom,sde-trusted-vm-env: Boolean property to indicate if the device driver is executing in a trusted VM +- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum + number of concurrent displays supported in the + trusted vm environment Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -711,6 +714,7 @@ Example: qcom,sde-has-idle-pc; qcom,fullsize-va-map; qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-dest-scaler-input-linewidth = <2048>; qcom,sde-max-dest-scaler-output-linewidth = <2560>; qcom,sde-sspp-max-rects = <1 1 1 1 From 555466b842307c7c84ec808352a5114370f504be Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:05:35 -0700 Subject: [PATCH 066/327] ARM: dts: msm: specify max trusted vm displays for Lahaina Specify maximum number of concurrent displays supported in trusted vm. This value will be used by both the vm's to validate the TUI start request. For Lahaina, we support one display in trusted vm. Change-Id: I643bacea09f1eead26c0165bf00590afeda67569 --- display/lahaina-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index bd93fb5130b3..fc2d7fa27bf7 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -161,6 +161,7 @@ qcom,sde-pipe-order-version = <0x1>; qcom,sde-has-dim-layer; qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-dest-scaler-input-linewidth = <2048>; qcom,sde-max-dest-scaler-output-linewidth = <2560>; From 51ce5ca9dfdd9e64a68cc1ab877e344c1b500f84 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:12:50 -0700 Subject: [PATCH 067/327] bindings: Documentation: add a property to exclude reg-names In trusted vm, register ranges that need to be mapped need to exactly be the same as that of HLOS vm. But the DT provided register ranges are used to validate the IO memory assign from HLOS vm. So this change introduces a separate property to specify the register names which need to be excluded from the IO memory validation list but still need to be mapped to the vm. Change-Id: I8c5c194254ae260f7a8878bb5492f5a039203fc9 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 635cefcd2ad7..d6cf76c02dd7 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -522,6 +522,9 @@ Optional properties: - qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum number of concurrent displays supported in the trusted vm environment +- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which + should be excluded from IO memory validation list + in trusted vm environment Bus Scaling: - interconnects An array of 4 cell properties with the format of From 044f1408aaa2604cb4abb22a13c18a8880968b00 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Mon, 13 Jul 2020 14:56:12 -0700 Subject: [PATCH 068/327] ARM: dts: msm: populate the property to exclude reg-names for validation Populate the property to exclude reg-names in trusted vm for Lahaina target while validating the IO memory assign from primary vm. Change-Id: I9dc92be7d11862f9af3c083939e82fa8a705b9e3 --- display/trustedvm-lahaina-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index 8ee259e82f95..dfebcb3a869f 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -21,6 +21,8 @@ "regdma_phys", "sid_phys"; + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version =<0x70000000>; clocks = From f460f4f8ab3c5efce28fd31887dd83c6c0794365 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 15 Jul 2020 13:53:45 +0800 Subject: [PATCH 069/327] ARM: dts: msm: Enable PWM backlight for sharp qhd plus panel Set the backlight control mode to PWM for this panel. Change-Id: I1ac9a35d775f38510aa9d5259aca940dc76ea40c --- display/lahaina-sde-display-cdp.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 2061e5db40b0..c393be6f19ee 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -111,7 +111,9 @@ &dsi_sharp_qhd_plus_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 82 0>; @@ -215,5 +217,7 @@ &sde_dsi { + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-2 = <&lcd_backlight_ctrl_default>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; }; From ac04e200df6d5188853abaaa9082ada9f748b3bb Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Mon, 13 Jul 2020 19:09:43 +0530 Subject: [PATCH 070/327] ARM: dts: msm: add display dt node for shima target Add display related dt nodes for shima target. Change-Id: I4726c57f338667183d50fe937c57767334fe1f21 --- display/shima-sde-display-idp.dtsi | 32 ++ display/shima-sde-display.dtsi | 204 ++++++++++++ display/shima-sde.dtsi | 491 +++++++++++++++++++++++++++++ 3 files changed, 727 insertions(+) create mode 100644 display/shima-sde-display-idp.dtsi create mode 100644 display/shima-sde-display.dtsi create mode 100644 display/shima-sde.dtsi diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi new file mode 100644 index 000000000000..7fd9d2bc172f --- /dev/null +++ b/display/shima-sde-display-idp.dtsi @@ -0,0 +1,32 @@ +#include "shima-sde-display.dtsi" + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; +}; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi new file mode 100644 index 000000000000..03e5cc9147a1 --- /dev/null +++ b/display/shima-sde-display.dtsi @@ -0,0 +1,204 @@ +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + + qcom,mdp = <&mdss_mdp>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi + &sde_dsi1>; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi new file mode 100644 index 000000000000..3a2e89c22c39 --- /dev/null +++ b/display/shima-sde.dtsi @@ -0,0 +1,491 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 460000000 19200000 460000000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, + <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x7 0x1>, + <0x8 0x2>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-has-idle-pc; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <5900000>; + qcom,sde-max-bw-high-kbps = <13500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + /* creq LUTs */ + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-id = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801 0xC01>; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + sde_rscc: qcom,sde_rscc { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + status = "disabled"; + reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <4>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mmss_noc MASTER_MDP1_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-ebi-bus"; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent-hint-cached; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>, + <&apps_smmu 0xC01 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; From c75bd0e197cbfe3402d492e8c05bec1297548c59 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Fri, 19 Jun 2020 15:36:55 -0700 Subject: [PATCH 071/327] ARM: dts: msm: add VRAM size to lahaina trusted vm Add the size of VRAM available in trusted vm. Change-Id: Ibe5cbc78b679fdce7293a6ae4ebd9b0947582023 --- bindings/sde.txt | 3 +++ display/trustedvm-lahaina-sde.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 3628b8a4ec55..69430faef8d1 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -527,6 +527,7 @@ Optional properties: - qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which should be excluded from IO memory validation list in trusted vm environment +- qcom,vram-size: A u32 value indicating the size of the VRAM in bytes Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -806,6 +807,8 @@ Example: qcom,sde-amortizable-threshold = <11>; qcom,sde-secure-sid-mask = <0x200801 0x200c01>; + qcom,vram-size = <0x200000>; + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index dfebcb3a869f..1a363cd7cb2f 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -38,6 +38,7 @@ "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; }; &mdss_dsi0 { From 1314f595be904203093a83f1f416a2f61e120f19 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Wed, 24 Jun 2020 17:57:17 +0530 Subject: [PATCH 072/327] ARM: dts: msm: add display DT node for Holi target Add all display related DT nodes for the Holi target. Change-Id: I30de0a892a8da34c7aa854e686a3dc1879d05a40 --- display/holi-sde-display-cdp.dtsi | 21 ++ display/holi-sde-display-mtp.dtsi | 21 ++ display/holi-sde-display.dtsi | 133 +++++++++++ display/holi-sde.dtsi | 376 ++++++++++++++++++++++++++++++ 4 files changed, 551 insertions(+) create mode 100644 display/holi-sde-display-cdp.dtsi create mode 100644 display/holi-sde-display-mtp.dtsi create mode 100644 display/holi-sde-display.dtsi create mode 100644 display/holi-sde.dtsi diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi new file mode 100644 index 000000000000..9fe8f90c81f4 --- /dev/null +++ b/display/holi-sde-display-cdp.dtsi @@ -0,0 +1,21 @@ +#include "holi-sde-display.dtsi" + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi new file mode 100644 index 000000000000..9fe8f90c81f4 --- /dev/null +++ b/display/holi-sde-display-mtp.dtsi @@ -0,0 +1,21 @@ +#include "holi-sde-display.dtsi" + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi new file mode 100644 index 000000000000..22d402536458 --- /dev/null +++ b/display/holi-sde-display.dtsi @@ -0,0 +1,133 @@ +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include + +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_te_active &disp_pins_default>; + pinctrl-1 = <&sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L1E>; + vdd-supply = <&L8A>; + + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dsi>; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi new file mode 100644 index 000000000000..a19a85b4781f --- /dev/null +++ b/display/holi-sde.dtsi @@ -0,0 +1,376 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@5e00000 { + compatible = "qcom,sde-kms"; + reg = <0x05e00000 0x8f030>, + <0x05eb0000 0x2008>, + <0x05e8f000 0x030>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "div_clk", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; + clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 + 560000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-type = "none", "dsi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800>; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dsc-off = <0x81000>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + qcom,sde-mixer-stage-base-layer; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-highest-bank-bit = <0x0 0x1>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1e>; + qcom,sde-macrotile-mode = <0x0>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + qcom,sde-max-bw-low-kbps = <5200000>; + qcom,sde-max-bw-high-kbps = <6200000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <1>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0xffff 0xffff 0x0 + 0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0 + 0x0 0x3ffff 0x3ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + + qcom,sde-secure-sid-mask = <0x821>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <32>; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_rotator: qcom,mdss_rotator { + status = "disabled"; + compatible = "qcom,sde_rotator"; + reg = <0x5e00000 0xac000>, + <0x5eb0000 0x2008>; + + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + qcom,mdss-rot-mode = <1>; + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>; + + /*Offline rotator RT setting */ + qcom,mdss-rot-parent = <&mdss_mdp 0>; + qcom,mdss-rot-xin-id = <10 11>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x83C 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x83D 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <1000>; + reg = <0x05e94000 0x400>, + <0x05f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L22A>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x05e94400 0x800>, + <0x05e94a00 0x1e0>, + <0x05f01004 0x8>, + <0x05e94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_10nm"; + vdda-0p9-supply = <&S5A_LEVEL>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 80]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + +}; From 3b050176d9fa33475d978e757ae280b74eba3daf Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 22 Jul 2020 14:40:26 +0530 Subject: [PATCH 073/327] ARM: dts: msm: add display node for Holi ATP platform This change adds display node for ATP platform of Holi. Change-Id: Ia52de9a1d24f40058636baf3139aa511f2a94c86 --- display/holi-sde-display-atp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 display/holi-sde-display-atp.dtsi diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi new file mode 100644 index 000000000000..9fe8f90c81f4 --- /dev/null +++ b/display/holi-sde-display-atp.dtsi @@ -0,0 +1,21 @@ +#include "holi-sde-display.dtsi" + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; From cc9c6c2900507a2b1caae22a98cdc9d03f38a1c8 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 11 Jun 2020 15:41:18 +0800 Subject: [PATCH 074/327] ARM: dts: msm: change r66451 video mode fps to 120hz for lahaina Set r66451 panel video mode default fps to 120hz, and enable DFPS. Change-Id: I52409209a379945ff70355cf93e8c1259324327b --- .../dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 33 ++++++++++++++++--- display/lahaina-sde-display-common.dtsi | 9 +++-- 2 files changed, 35 insertions(+), 7 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index c67a33b57cc8..182038f97fab 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -38,18 +38,41 @@ qcom,mdss-dsi-v-back-porch = <4>; qcom,mdss-dsi-v-front-porch = <25>; qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 00 39 01 00 00 00 00 02 b3 01 - 39 01 00 00 00 00 02 b0 80 - 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 - 01 04 04 04 04 04 05 - 39 01 00 00 00 00 02 b0 04 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 df 50 40 39 01 00 00 00 00 06 f3 50 00 00 00 00 39 01 00 00 00 00 02 f2 11 diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 7059407c5de6..f9efbd122ba9 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -156,10 +156,15 @@ &dsi_r66451_amoled_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <60>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From 0c12118672789c70587baafbc71ce10929ff210d Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 16 Jul 2020 06:19:06 -0700 Subject: [PATCH 075/327] ARM: dts: msm: add display device tree files for lahaina MTP v2.1 Add display device-tree support for Lahaina's MTP v2.1 platform. Change-Id: Ibc90d2e8109e38a120b61d8df800cf41fab3f00e --- display/lahaina-sde-display-mtp-v2.1.dtsi | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 display/lahaina-sde-display-mtp-v2.1.dtsi diff --git a/display/lahaina-sde-display-mtp-v2.1.dtsi b/display/lahaina-sde-display-mtp-v2.1.dtsi new file mode 100644 index 000000000000..e4b362c150f1 --- /dev/null +++ b/display/lahaina-sde-display-mtp-v2.1.dtsi @@ -0,0 +1,3 @@ +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From cbbe1e2a1251fc6f7fd6030a1b45025232838074 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 23 Jul 2020 22:19:29 -0700 Subject: [PATCH 076/327] ARM: dts: msm: add cmd to vid switch commands for qsync panel Add DCS commands that would be sent during a panel operating mode switch from command mode to video mode. The switch command sets the full frame width and height as the horizontal address and vertical address for the DDIC on switching to video mode. If this is not done and the switch occurs during a partial frame update corruption can be observed post switch. Change-Id: I0b12eb24e4fdac5b0e4bbf42493d8bc0081cc361 --- display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi index 215b3ab46dde..7d766b6bebc6 100644 --- a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi +++ b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi @@ -139,6 +139,10 @@ 05 01 00 00 32 00 01 10 ]; qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,cmd-to-video-mode-switch-commands = [ + 39 01 00 00 00 00 05 2a 00 00 02 cf + 39 01 00 00 00 00 05 2b 00 00 09 ff + ]; qcom,cmd-to-video-mode-post-switch-commands = [ 39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 @@ -569,6 +573,10 @@ 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29 ]; + qcom,cmd-to-video-mode-switch-commands = [ + 39 01 00 00 00 00 05 2a 00 00 02 cf + 39 01 00 00 00 00 05 2b 00 00 09 ff + ]; qcom,cmd-to-video-mode-post-switch-commands = [ 39 00 00 00 00 00 02 ff 10 39 00 00 00 00 00 02 fb 01 From cbfac06c5ac6882e75911e075361402ca2e915ed Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Fri, 24 Jul 2020 11:25:57 -0700 Subject: [PATCH 077/327] ARM: dts: msm: add 144FPS for WQHD resolution on sim panel Change adds 144FPS refresh rate timing node with WQHD resolution for simulation panel. Change-Id: I9dc7c7d0d255a12948082955632f6cf65d7178bf --- .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 52 +++++++++++++++++++ display/lahaina-sde-display-common.dtsi | 7 +++ 2 files changed, 59 insertions(+) diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index 0d48d49b21ca..6b5a5b7f04f9 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -1485,6 +1485,58 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@18 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index f9efbd122ba9..79bd533246cb 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -707,6 +707,13 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; + + timing@18 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a + 0a 07 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; }; }; From c312c98f5038fc1554df6ed9d5f9e98d02f36e56 Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Thu, 9 Jul 2020 13:47:16 +0530 Subject: [PATCH 078/327] ARM: dts: msm: add dp dt node for shima target Add the DP DT node for Shima target. DP SST POR resolution of 4K@60 can be supported without DSC and widebus support. So, the support for DSC, FEC and widebus is not required. Change-Id: Ife3e4806fd116fce3eb1709fd8c73f03446b074c --- display/shima-sde.dtsi | 142 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 3a2e89c22c39..0b991af1c804 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -269,6 +269,148 @@ }; }; + ext_disp: qcom,msm-ext-disp { + status = "disabled"; + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + status = "disabled"; + compatible = "qcom,msm-hdcp"; + }; + + sde_dp: qcom,dp_display@ae90000 { + status = "disabled"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + /* usb-phy = <&usb_qmp_dp_phy>; */ + /* qcom,dp-aux-switch = <&fsa4480>; */ + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02004 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,mst-enable; + + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + sde_rscc: qcom,sde_rscc { cell-index = <0>; compatible = "qcom,sde-rsc"; From 3d964593052889e031b55b6ab5b4e77714a76f65 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 28 Jul 2020 20:35:00 -0700 Subject: [PATCH 079/327] dt-bindings: update dma scheduling bindings for DSI panels Change updates qcom,mdss-dsi-dma-schedule-line and qcom,mdss-dsi-dma-schedule-window bindings which are used to specify parameters for scheduling DSI commands. Change-Id: Ic0c567475639e5db96fc314e9a717666a2b44b56 --- bindings/mdss-dsi-panel.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 9fee318fbeb2..47db5592f747 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -576,7 +576,10 @@ Optional properties: value 0. - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active - region, at which command DMA needs to be triggered. + region for video mode panels and line number after TE for command mode + panels, at which command DMA needs to be triggered. +- qcom,mdss-dsi-dma-schedule-window: An integer value indicates the width of the DMA window during which a + DCS command will be triggered for command mode panels Required properties for sub-nodes: None Optional properties: @@ -851,5 +854,6 @@ Example: qcom,src-color-space = <0>; qcom,src-chroma-format = <0>; qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,mdss-dsi-dma-schedule-window = <50>; }; }; From 5e21e097272b7e6d555b8fefd1b6e62000cd9796 Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Fri, 31 Jul 2020 18:37:07 +0530 Subject: [PATCH 080/327] ARM: dts: msm: update dp dt properties for shima Update the DP DT node properties for Shima target. Change-Id: I7eaea8148756d39f67491a418432173fa2f8b758 --- display/shima-sde.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 0b991af1c804..8705b8ab8a46 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -288,8 +288,8 @@ cell-index = <0>; compatible = "qcom,dp-display"; - /* usb-phy = <&usb_qmp_dp_phy>; */ - /* qcom,dp-aux-switch = <&fsa4480>; */ + usb-phy = <&usb_qmp_dp_phy>; + qcom,dp-aux-switch = <&fsa4480>; qcom,ext-disp = <&ext_disp>; qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; @@ -316,16 +316,16 @@ interrupts = <12 0>; #clock-cells = <1>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", From c72c7df9633208db6c8b54244bd5242382ed798d Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 26 May 2020 10:03:36 -0700 Subject: [PATCH 081/327] ARM: dts: msm: update transfer time for sharp qhd panel for lahaina This change updates transfer time fpr Sharp QHD plus panel for 120 FPS timing node to 7933us. Change-Id: I02b65370acf76c4905ad3e4c81cc25185667bf09 --- display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi index 90fb731fbb88..3263d8ff8c74 100644 --- a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi +++ b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -38,6 +38,7 @@ qcom,mdss-dsi-v-front-porch = <39>; qcom,mdss-dsi-v-pulse-width = <2>; qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-mdp-transfer-time-us = <7933>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 From 1780d111edd6b6d32d10382ad3bd141895b792ae Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 15:12:53 +0800 Subject: [PATCH 082/327] ARM: dts: msm: add display panel support for qrd holi Add qrd holi display initial changes. Change-Id: I4f55787ef5c37937004e749eb96561ebce8c5d96 --- display/holi-sde-display-qrd.dtsi | 31 +++++++++++++++++ display/holi-sde-display.dtsi | 57 +++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 display/holi-sde-display-qrd.dtsi diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi new file mode 100644 index 000000000000..de64faa435fc --- /dev/null +++ b/display/holi-sde-display-qrd.dtsi @@ -0,0 +1,31 @@ +#include "holi-sde-display.dtsi" + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 22d402536458..f68e8e82ab7a 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,5 +1,7 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include &pm6150l_gpios { @@ -131,3 +133,58 @@ }; }; +&dsi_r66451_amoled_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + From 523f2ecf5025ed2cb9af6a22508477643fbfd697 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Mon, 6 Apr 2020 10:27:37 -0700 Subject: [PATCH 083/327] ARM: dts: msm: add poms pm_qos cpu mask for silver cores on Lahaina target This change adds pm_qos cpu mask for all silver/performance cores. Change-Id: I628d0731b04b20049bb87ebf75d90197001c4263 --- display/lahaina-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 3bc51fc6b856..738a141a3dc2 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -214,6 +214,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From fbd9ab3a3572c057bfeac6a1d2bd1717f988b564 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 6 Aug 2020 18:23:40 +0530 Subject: [PATCH 084/327] ARM: dts: msm: add r66451 video mode 60hz panel support This change adds visionox r66451 amoled video mode 60Hz dsi panel for Shima target. Change-Id: Iaf673170b6930ea8c58b31474630473108f7bb67 --- ...-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 87 +++++++++++++++++++ display/shima-sde-display-idp.dtsi | 12 ++- display/shima-sde-display.dtsi | 13 +++ 3 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi new file mode 100644 index 000000000000..50e11b87af55 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -0,0 +1,87 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox 60Hz panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 7fd9d2bc172f..8049e9d4a014 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +} + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -28,5 +38,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_video>; }; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 03e5cc9147a1..d7bf5f96c7eb 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,4 +1,5 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -158,6 +159,18 @@ }; }; +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From 72dabe29f079fc6646c00b212c736d8ea6d262fe Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 12:22:51 +0800 Subject: [PATCH 085/327] ARM: dts: msm: enable LP mode DCS brightness setting for 5K sim panel Used LP mode for DCS brightness command transfer for this 5K sim panel. Change-Id: I1d2b9dfe212dc13e1a4403b56d8c72888df95750 --- display/lahaina-sde-display-cdp.dtsi | 1 + display/lahaina-sde-display-mtp.dtsi | 1 + display/lahaina-sde-display-qrd.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index c393be6f19ee..c53c7af3cac5 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -178,6 +178,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index dfae6039ca0f..167f6866c3f6 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -170,6 +170,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index bb711e419e3c..9080fd8022cd 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -170,6 +170,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { From 1326a6c9d32ae609a3a6ce553af09328c93fb729 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 12:20:30 +0800 Subject: [PATCH 086/327] bindings: Documentation: add documentation for DCS transfer mode/state Add a property for DCS brightness commands transfer mode selected. When set the property, will use LP mode for commands transfer, while the default mode is HS mode. Change-Id: I256812b2a3766d1bd31b0eb901ae02f2c0b15211 --- bindings/mdss-dsi-panel.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 47db5592f747..f6c67e5727cd 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -201,6 +201,10 @@ Optional properties: 255 = default value. - qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. When this boolean is set, will inverted display brightness value. +- qcom,bl-dsc-cmd-state: String that specifies the ctrl state for sending dcs brightness commands. + "dsi_hs_mode" = DSI high speed mode (default) + "dsi_lp_mode" = DSI low power mode + If the string was not set, dsi_hs_mode will be set as default mode. - qcom,mdss-brightness-max-level: Specifies the max brightness level supported. 255 = default value. - qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. From 547aca447f97f08ac66f7398b8bdee56873e6235 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Thu, 13 Aug 2020 16:52:53 +0800 Subject: [PATCH 087/327] ARM: dts: msm: add display panel support for qrd shima Add display panel support for qrd shima. Change-Id: I432ece75d018a29da22d26b6524d677a989dd01d --- display/shima-sde-display-qrd.dtsi | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 display/shima-sde-display-qrd.dtsi diff --git a/display/shima-sde-display-qrd.dtsi b/display/shima-sde-display-qrd.dtsi new file mode 100644 index 000000000000..72107b66065a --- /dev/null +++ b/display/shima-sde-display-qrd.dtsi @@ -0,0 +1,32 @@ +#include "shima-sde-display.dtsi" + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From 53d32d47d08300b9cc5d3a81182f8ee8ee5fdcf8 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 14:22:30 +0530 Subject: [PATCH 088/327] ARM: dts: msm: Fix compilation error for 60Hz panel on shima This change fixes compilation error with 60Hz panel support on shima idp platform. Change-Id: Ia70fde134829bdb8509d3b65fb471bae8fd6a902 --- display/shima-sde-display-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 8049e9d4a014..a19da7346b70 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -18,7 +18,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; -} +}; &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; From 89833c6f13b656607fbd4e2f9ece59bb92bdbb79 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 11 Aug 2020 15:10:33 -0700 Subject: [PATCH 089/327] ARM: dts: msm: add display related SPMI address Add SPMI reference node along with the display related SPMI address. This will be used during the trusted-ui usecase where the VMs uses SPMI api to get the physical address, which will be lent/validated during the usecase. Change-Id: Ic3173410790443e87c0584681ec1f0c160fc04a2 --- bindings/sde.txt | 3 +++ display/lahaina-sde-common.dtsi | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 69430faef8d1..9fa9bfc70aba 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -528,6 +528,8 @@ Optional properties: should be excluded from IO memory validation list in trusted vm environment - qcom,vram-size: A u32 value indicating the size of the VRAM in bytes +- qcom,pmic-arb-address: A u32 array of display related SPMI address + bit mask, which is a combination of SID and pheripheral id's. Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -808,6 +810,7 @@ Example: qcom,sde-secure-sid-mask = <0x200801 0x200c01>; qcom,vram-size = <0x200000>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 738a141a3dc2..3730cc8d6dd7 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -228,6 +228,10 @@ qcom,sde-secure-sid-mask = <0x4000821>; + /* SPMI address related to display */ + qcom,pmic-arb = <&spmi_bus>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 74000>, <0 148000>, From 8efc9164186b8bb24f438b742587b249b87e1b44 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 11 Aug 2020 15:10:40 -0700 Subject: [PATCH 090/327] ARM: dts: msm: add gpio pins/address used for BOE cmd panel Add the TLMM base address & size of each GPIO register space along with all the GPIO pins used to drive the DSI host and the BOE panel. Change-Id: Ifabc0713de8c893fdd8b8a0fc38898898ec3c571 --- bindings/mdss-dsi-panel.txt | 9 +++++++++ display/lahaina-sde-display-common.dtsi | 3 +++ 2 files changed, 12 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index f6c67e5727cd..69bdd72ee00e 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -578,6 +578,11 @@ Optional properties: to identify the default topology for the display. The first set is indexed by the value 0. +- qcom,dsi-panel-gpio-address: An u32 pair consisting of base address of the + TLMM register space and size of each GPIO pin. +- qcom,dsi-panel-gpio-pins: An u32 array consisting of all the GPIO pins used + for driving the DSI host and the panels + connected to the host. - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active region for video mode panels and line number after TE for command mode @@ -759,6 +764,10 @@ Example: qcom,mdss-dsi-force-clock-lane-hs; qcom,compression-mode = "dsc"; qcom,adjust-timer-wakeup-ms = <1>; + + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,mdss-dsi-display-timings { wqhd { qcom,mdss-dsi-cmd-mode; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 79bd533246cb..db0de1573d19 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -124,6 +124,9 @@ qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05 From 1e932816d2e4ce46411c1f909f84a65768327362 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 14 Aug 2020 18:03:21 +0530 Subject: [PATCH 091/327] ARM: dts: msm: add rm69299 cmd mode panel support on Holi This change adds visionox rm69299 amoled command mode 60Hz FHD+ dsi panel on Holi target. Change-Id: Iaeb030a7b9fd55dbce4f903223ad1029c63f6c67 --- ...i-panel-rm69299-visionox-fhd-plus-cmd.dtsi | 64 +++++++++++++++++++ display/holi-sde-display-atp.dtsi | 10 +++ display/holi-sde-display-cdp.dtsi | 11 ++++ display/holi-sde-display-mtp.dtsi | 10 +++ display/holi-sde-display.dtsi | 21 ++++++ 5 files changed, 116 insertions(+) create mode 100644 display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi diff --git a/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi b/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi new file mode 100644 index 000000000000..e898151080a6 --- /dev/null +++ b/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi @@ -0,0 +1,64 @@ +&mdss_mdp { + dsi_rm69299_visionox_amoled_cmd: + qcom,mdss_dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-panel-name = + "rm69299 amoled fhd+ cmd mode dsi visionox panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2248>; + qcom,mdss-dsi-h-front-porch = <26>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <56>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 02 C2 08 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 51 FF + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 9fe8f90c81f4..5efaab6d6cf2 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 9fe8f90c81f4..f3b4ef6925c2 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -10,6 +10,17 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 9fe8f90c81f4..5efaab6d6cf2 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index f68e8e82ab7a..33e94bd589da 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,5 +1,6 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include @@ -133,6 +134,26 @@ }; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; From 709b5894cc7877c07acbf7982fcc42fc572c10e4 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 19:12:28 +0530 Subject: [PATCH 092/327] ARM: dts: msm: enable esd check for visionox panel on Holi This change enables esd check for rm69299 visionox video and command mode panel in Holi target. Change-Id: I8cca8bccf1b8be46e45ab0379ddb629be7aac3cb --- display/holi-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 33e94bd589da..8c4e1c4c2ab6 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -115,6 +115,7 @@ }; &dsi_rm69299_visionox_amoled_video { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -135,6 +136,7 @@ }; &dsi_rm69299_visionox_amoled_cmd { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; From 3f144365282f81057bacbb5fb52f7edffc771763 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 19:16:53 +0530 Subject: [PATCH 093/327] ARM: dts: msm: enable dfps support for visionox panel on Holi This change enables dynamic fps support for rm6929 visionox video mode panel on Holi target. Change-Id: I3c22b2afa93242f0d224545bcca7452d8df3a7d4 --- display/holi-sde-display.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 8c4e1c4c2ab6..0c39119ce036 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -122,6 +122,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 55 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x31>; From 3d0694174995c4397ed8d5749e1dcd941ce2dabe Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Mon, 17 Aug 2020 13:44:51 +0800 Subject: [PATCH 094/327] bindings: Documentation: add documentation for display touch event Add the documentation for configuring the display input touch event feature. Change-Id: Id4236460219038fa644387e2fd8fe97f97554c5e --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 69430faef8d1..610cb0ca1e40 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -158,6 +158,9 @@ Optional properties: feature is available or not. - qcom,sde-has-idle-pc: Boolean property to indicate if target has idle power collapse feature available or not. +- qcom,sde-wakeup-with-touch: Boolean property to indicate if command mode display + will exit from power collapse based on display input + touch event or not. - qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction feature available or not. - qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler @@ -718,6 +721,7 @@ Example: qcom,sde-highest-bank-bit = <15>; qcom,sde-has-mixer-gc; qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; qcom,fullsize-va-map; qcom,sde-has-dest-scaler; qcom,sde-max-trusted-vm-displays = <1>; From 5e42d3884a7c43107e055dcc4d7485937c65beb7 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Thu, 16 Jul 2020 17:47:11 +0800 Subject: [PATCH 095/327] ARM: dts: msm: Remove unused property from panel nodes Remove unused property te-gpio from panel nodes, and this property is defined in dsi_display node. Change-Id: Ie6fd4c4f73dbf292bcc58757898fb91468d88ade --- display/lahaina-sde-display-cdp.dtsi | 9 --------- display/lahaina-sde-display-mtp.dtsi | 9 --------- display/lahaina-sde-display-qrd.dtsi | 9 --------- 3 files changed, 27 deletions(-) diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index c53c7af3cac5..23695a28dd3a 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -6,7 +6,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -28,7 +27,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; @@ -58,7 +56,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -67,7 +64,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -86,7 +82,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -95,7 +90,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -116,7 +110,6 @@ qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -126,7 +119,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -145,7 +137,6 @@ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 167f6866c3f6..804bb6a26c7d 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -6,7 +6,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -26,7 +25,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -46,7 +44,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -64,7 +61,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -83,7 +79,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -92,7 +87,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -111,7 +105,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -121,7 +114,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -138,7 +130,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 9080fd8022cd..365e13e7fa43 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -7,7 +7,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -27,7 +26,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -46,7 +44,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -64,7 +61,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -83,7 +79,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -92,7 +87,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -111,7 +105,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; qcom,platform-bklight-en-gpio = <&tlmm 13 0>; }; @@ -121,7 +114,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -138,7 +130,6 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; }; From 505c59fd1aaf9b9f65642db6350814f0ddcb9865 Mon Sep 17 00:00:00 2001 From: Vara Reddy Date: Tue, 18 Aug 2020 10:22:52 -0700 Subject: [PATCH 096/327] ARM: dts: msm: enable constant FPS with RFI for BOE panel on Lahaina Enable dynamic refresh with constant FPS feature for BOE video mode panel Change-Id: I1eac76b9d1936982b67fff9d6cd80fc209f1d3e8 --- display/lahaina-sde-display-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 7059407c5de6..6344481ea165 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -143,6 +143,7 @@ "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; qcom,mdss-dsi-display-timings { timing@0 { From 5023464cf6beb180754699ebada300ea970f475c Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 31 Jul 2020 15:12:53 +0800 Subject: [PATCH 097/327] ARM: dts: msm: add display panel support for qrd holi Add qrd holi display initial changes. Change-Id: I4f55787ef5c37937004e749eb96561ebce8c5d96 --- display/holi-sde-display-qrd.dtsi | 31 +++++++++++++++++ display/holi-sde-display.dtsi | 57 +++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 display/holi-sde-display-qrd.dtsi diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi new file mode 100644 index 000000000000..de64faa435fc --- /dev/null +++ b/display/holi-sde-display-qrd.dtsi @@ -0,0 +1,31 @@ +#include "holi-sde-display.dtsi" + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 22d402536458..f68e8e82ab7a 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,5 +1,7 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include &pm6150l_gpios { @@ -131,3 +133,58 @@ }; }; +&dsi_r66451_amoled_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + From 817b7b601b94b7d878da96db919008708f7a10a8 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 6 Aug 2020 18:23:40 +0530 Subject: [PATCH 098/327] ARM: dts: msm: add r66451 video mode 60hz panel support This change adds visionox r66451 amoled video mode 60Hz dsi panel for Shima target. Change-Id: Iaf673170b6930ea8c58b31474630473108f7bb67 --- ...-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 87 +++++++++++++++++++ display/shima-sde-display-idp.dtsi | 12 ++- display/shima-sde-display.dtsi | 13 +++ 3 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi new file mode 100644 index 000000000000..50e11b87af55 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -0,0 +1,87 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox 60Hz panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 7fd9d2bc172f..8049e9d4a014 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +} + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -28,5 +38,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_video>; }; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 03e5cc9147a1..d7bf5f96c7eb 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,4 +1,5 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -158,6 +159,18 @@ }; }; +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From 23aee8087fe34a1c41c88da79467fb43ed670dc8 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 14:22:30 +0530 Subject: [PATCH 099/327] ARM: dts: msm: Fix compilation error for 60Hz panel on shima This change fixes compilation error with 60Hz panel support on shima idp platform. Change-Id: Ia70fde134829bdb8509d3b65fb471bae8fd6a902 --- display/shima-sde-display-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 8049e9d4a014..a19da7346b70 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -18,7 +18,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; -} +}; &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; From 0cf4a4bb3b9b5def6284af0eafca00d6c1e57729 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 14 Aug 2020 18:03:21 +0530 Subject: [PATCH 100/327] ARM: dts: msm: add rm69299 cmd mode panel support on Holi This change adds visionox rm69299 amoled command mode 60Hz FHD+ dsi panel on Holi target. Change-Id: Iaeb030a7b9fd55dbce4f903223ad1029c63f6c67 --- ...i-panel-rm69299-visionox-fhd-plus-cmd.dtsi | 64 +++++++++++++++++++ display/holi-sde-display-atp.dtsi | 10 +++ display/holi-sde-display-cdp.dtsi | 11 ++++ display/holi-sde-display-mtp.dtsi | 10 +++ display/holi-sde-display.dtsi | 21 ++++++ 5 files changed, 116 insertions(+) create mode 100644 display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi diff --git a/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi b/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi new file mode 100644 index 000000000000..e898151080a6 --- /dev/null +++ b/display/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi @@ -0,0 +1,64 @@ +&mdss_mdp { + dsi_rm69299_visionox_amoled_cmd: + qcom,mdss_dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-panel-name = + "rm69299 amoled fhd+ cmd mode dsi visionox panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2248>; + qcom,mdss-dsi-h-front-porch = <26>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <56>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 02 C2 08 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 51 FF + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 9fe8f90c81f4..5efaab6d6cf2 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 9fe8f90c81f4..f3b4ef6925c2 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -10,6 +10,17 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 9fe8f90c81f4..5efaab6d6cf2 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index f68e8e82ab7a..33e94bd589da 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,5 +1,6 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include @@ -133,6 +134,26 @@ }; }; +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; From 6ca3ad310e1082ad9200f470d73d66e355940960 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 19:12:28 +0530 Subject: [PATCH 101/327] ARM: dts: msm: enable esd check for visionox panel on Holi This change enables esd check for rm69299 visionox video and command mode panel in Holi target. Change-Id: I8cca8bccf1b8be46e45ab0379ddb629be7aac3cb --- display/holi-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 33e94bd589da..8c4e1c4c2ab6 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -115,6 +115,7 @@ }; &dsi_rm69299_visionox_amoled_video { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -135,6 +136,7 @@ }; &dsi_rm69299_visionox_amoled_cmd { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; From 3f0f51abc226eb4c3e074afc107804b5204ad216 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 17 Aug 2020 19:16:53 +0530 Subject: [PATCH 102/327] ARM: dts: msm: enable dfps support for visionox panel on Holi This change enables dynamic fps support for rm6929 visionox video mode panel on Holi target. Change-Id: I3c22b2afa93242f0d224545bcca7452d8df3a7d4 --- display/holi-sde-display.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 8c4e1c4c2ab6..0c39119ce036 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -122,6 +122,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 55 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x31>; From bf1b8f2af3b3291e9e9f32f5d8bc97627d0e83d2 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Sun, 16 Aug 2020 17:30:27 +0530 Subject: [PATCH 103/327] ARM: dts: msm: enable offline rotator in Holi target This changes enables sde offline rotator in holi target. Change-Id: I54a947707466a7c561a825404d18bb53c8188e2f --- display/holi-sde.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index a19a85b4781f..4d932ada8d92 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -199,7 +199,6 @@ }; mdss_rotator: qcom,mdss_rotator { - status = "disabled"; compatible = "qcom,sde_rotator"; reg = <0x5e00000 0xac000>, <0x5eb0000 0x2008>; @@ -227,7 +226,7 @@ interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", + interconnect-names = "qcom,rot-data-bus0", "qcom,sde-reg-bus"; qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 76800>; From cfec398d2c3e806965972c0f70630084ddbd4f2a Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Sun, 23 Aug 2020 00:18:23 +0530 Subject: [PATCH 104/327] ARM: dts: msm: Extend DP and phy registers to correct size Extend DP and phy registers to correct size. Change-Id: Ia6304d9f4e097e0a7eb429446b87184b62830d7f --- display/shima-sde.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 8705b8ab8a46..e7a9fa86ef15 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -294,18 +294,18 @@ qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; - reg = <0xae90000 0x0dc>, + reg = <0xae90000 0x0f4>, <0xae90200 0x0c0>, - <0xae90400 0x508>, - <0xae91000 0x094>, - <0x88eaa00 0x200>, - <0x88ea200 0x200>, - <0x88ea600 0x200>, - <0xaf02004 0x1a0>, - <0x88ea000 0x200>, - <0x88e8000 0x20>, - <0x0aee1000 0x034>, - <0xae91400 0x094>, + <0xae90400 0x72c>, + <0xae91000 0x098>, + <0x88eaa00 0x198>, + <0x88ea200 0x160>, + <0x88ea600 0x160>, + <0xaf02004 0x1d4>, + <0x88ea000 0x1c8>, + <0x88e8000 0x3c>, + <0x0aee1000 0x02c>, + <0xae91400 0x098>, <0xaf03000 0x8>; reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", From 7ac09236461a7c1e9d0258e45ada5112232184ed Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 21 Aug 2020 19:49:48 +0530 Subject: [PATCH 105/327] ARM: dts: msm: change display supply enable load on Shima This change updates the vdd supply enable load to 30mA on Shima target. Minimum 30mA enable load is recommended to bring the regulator out of Low Power Mode. Change-Id: Ibead207dd44123add6858e3a0a1e9e4c67eda6f9 --- display/shima-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d7bf5f96c7eb..6a72d6a23c56 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -24,7 +24,7 @@ qcom,supply-name = "vdd"; qcom,supply-min-voltage = <3000000>; qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <10000>; + qcom,supply-enable-load = <30000>; qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; }; From 96ee083701196596c32242566df5bdf3ed2fd1f3 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Sat, 22 Aug 2020 14:49:52 +0530 Subject: [PATCH 106/327] ARM: dts: msm: create sde-display-common device tree on Holi Separate common SDE display bindings in sde-display-common dt file to avoid unwanted duplications between VM variants of the SDE display files on Holi target. Change-Id: Id86e414207a9874c6ddcc2855f01e774d49f1fff --- display/holi-sde-display-common.dtsi | 148 +++++++++++++++++++++++ display/holi-sde-display.dtsi | 174 +++------------------------ 2 files changed, 168 insertions(+), 154 deletions(-) create mode 100644 display/holi-sde-display-common.dtsi diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi new file mode 100644 index 000000000000..808738871503 --- /dev/null +++ b/display/holi-sde-display-common.dtsi @@ -0,0 +1,148 @@ +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" +#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,dsi-supported-dfps-list = <60 55 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 0c39119ce036..026318b53148 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,9 +1,4 @@ -#include "dsi-panel-sim-video.dtsi" -#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi" -#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" -#include +#include "holi-sde-display-common.dtsi" &pm6150l_gpios { disp_pins { @@ -18,102 +13,35 @@ }; }; -&soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <62000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_te_active &disp_pins_default>; + pinctrl-1 = <&sde_te_suspend>; - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <857000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,panel-te-source = <0>; - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; + vddio-supply = <&L1E>; + vdd-supply = <&L8A>; - qcom,panel-supply-entry@3 { - reg = <3>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - sde_dsi: qcom,dsi-display-primary { - compatible = "qcom,dsi-display"; - label = "primary"; - - qcom,dsi-ctrl = <&mdss_dsi0>; - qcom,dsi-phy = <&mdss_dsi_phy0>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_te_active &disp_pins_default>; - pinctrl-1 = <&sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 23 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L1E>; - vdd-supply = <&L8A>; - - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; - - qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; - }; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; }; &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dsi>; }; -&dsi_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - &dsi_rm69299_visionox_amoled_video { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -122,20 +50,6 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <60 55 48>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0E>; - qcom,mdss-dsi-t-clk-pre = <0x31>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 - 08 05 02 04 00]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_rm69299_visionox_amoled_cmd { @@ -146,17 +60,6 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0E>; - qcom,mdss-dsi-t-clk-pre = <0x31>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 - 08 05 02 04 00]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_cmd { @@ -167,31 +70,6 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0A>; - qcom,mdss-dsi-t-clk-pre = <0x1D>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 - 07 08 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_video { @@ -201,16 +79,4 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-t-clk-post = <0x0B>; - qcom,mdss-dsi-t-clk-pre = <0x27>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; }; - From 088da186f0951e1b238b8a3ea13e47fe35fe2ffa Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Tue, 26 May 2020 12:02:18 +0800 Subject: [PATCH 107/327] ARM: dts: msm: add 144hz panel support for lahaina Add DDIC R66451 144hz panel dtsi support for lahaina. Change-Id: Id3d39b94ab3d189d8a6703e4042f607256403dae --- ...i-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi | 134 ++++++++++++++++++ display/lahaina-sde-display-cdp.dtsi | 12 ++ display/lahaina-sde-display-common.dtsi | 14 ++ display/lahaina-sde-display-mtp.dtsi | 12 ++ display/lahaina-sde-display-qrd.dtsi | 12 ++ display/lahaina-sde-display.dtsi | 9 ++ 6 files changed, 193 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi new file mode 100644 index 000000000000..a959920b50ca --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi @@ -0,0 +1,134 @@ +&mdss_mdp { + dsi_r66451_amoled_144hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 B0 04 + 39 01 00 00 00 00 03 E8 00 02 + 39 01 00 00 00 00 03 E4 00 08 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 32 C4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0C 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 CF 64 0B 00 00 00 + 00 00 00 08 00 0B 77 01 01 01 01 01 + 01 02 02 02 02 02 03 00 00 00 00 00 + 00 00 00 00 00 00 00 02 C9 02 C9 02 + C9 03 FF 03 FF 03 FF 00 00 00 00 00 + 00 00 00 00 00 00 00 02 C9 02 C9 02 + C9 03 FF 03 FF 03 FF 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 0F F6 0F + F6 0F F6 0F F6 0F F6 19 + 39 01 00 00 00 00 0D D0 44 44 B2 28 00 + 28 5A 00 5A 0D 17 01 + 39 01 00 00 00 00 15 D3 49 00 00 01 1A + 15 00 15 07 0F 77 77 77 37 B2 11 00 + A0 3C 9A + 39 01 00 00 00 00 1A D7 00 B9 40 00 40 + 04 00 F0 0F 00 40 00 00 00 00 00 00 + 19 40 00 40 04 00 F0 0F + 39 01 00 00 00 00 34 D8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0F + 00 0F 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0F 00 2F 00 0F 00 20 + 39 01 00 00 00 00 2B DF 50 42 58 81 2D + 00 00 00 00 00 00 6B 00 00 00 00 00 + 00 00 00 01 0F FF D4 0E 00 00 00 00 + 00 00 0F 53 18 00 0F 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 F7 01 + 39 01 00 00 00 00 02 B0 80 + 39 01 00 00 00 00 0a E4 34 B4 00 00 00 + 30 04 0C E2 + 39 01 00 00 00 00 02 E6 00 + 39 01 00 00 00 00 02 B0 04 + 39 01 00 00 00 00 03 DF 50 40 + 39 01 00 00 00 00 06 F3 50 00 00 00 00 + 39 01 00 00 00 00 02 F2 11 + 39 01 00 00 00 00 06 F3 01 00 00 00 01 + 39 01 00 00 00 00 03 F4 00 02 + 39 01 00 00 00 00 02 F2 19 + 39 01 00 00 00 00 03 DF 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 23695a28dd3a..58ebc3bec606 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -47,6 +47,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -56,6 +57,17 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index e8d923ee4a08..923309e61b86 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -15,6 +15,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" @@ -228,6 +229,19 @@ }; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 804bb6a26c7d..ad1eb186123b 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -44,6 +44,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -53,6 +54,17 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 365e13e7fa43..6792ded59c5e 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -26,6 +26,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; @@ -35,6 +36,17 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 4e0465985d59..60e9663d7420 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -145,6 +145,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; qcom,esd-check-enabled; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; From 297068b26ab2041413642b88e3cbb8225f0d1ae6 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Tue, 25 Aug 2020 10:23:24 +0530 Subject: [PATCH 108/327] ARM: dts: msm: add display ramdump support for holi target This change adds dt support for display during ramdump in holi target. Change-Id: I3e5ff5d6be7813b8f06ba2213f67d98b65e16a66 --- display/holi-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index a19a85b4781f..79854a6e01de 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -1,6 +1,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@85200000 { + reg = <0x0 0x85200000 0x0 0x00c00000>; + label = "disp_rdump_region"; + }; + mdss_mdp: qcom,mdss_mdp@5e00000 { compatible = "qcom,sde-kms"; reg = <0x05e00000 0x8f030>, From 393997558179ec9c05566827fa1f1e039fa9d961 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Mon, 24 Aug 2020 16:14:45 +0800 Subject: [PATCH 109/327] ARM: dts: msm: modify VFP & VBP value for nt35597 panel Increase VFP and VBP value to get higer performance. Default prefill lines is 40 for lahaina, if VFP + VBP + VSYNC_PULSE is lower than 40, may lead to perf issues in some cases. Change-Id: I9d2a39cf9cbf14adc06eee03c7b79433bf498ef3 --- display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi index 090c75f8b90d..417d22e3c8b5 100644 --- a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -39,8 +39,8 @@ qcom,mdss-dsi-h-back-porch = <32>; qcom,mdss-dsi-h-pulse-width = <16>; qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-back-porch = <17>; + qcom,mdss-dsi-v-front-porch = <23>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-on-command = [ From 6115acd39e8e3ab9b5f30ac677167404585e7f97 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 27 Aug 2020 12:12:11 +0530 Subject: [PATCH 110/327] ARM: dts: msm: create sde-common device tree for holi target Separate common SDE bindings in sde-common-dt file to avoid unwanted duplications between VM variants of the SDE files for holi target. Change-Id: I45cab5017c296ec8669892b5edd0a742b59011f4 --- display/holi-sde-common.dtsi | 246 +++++++++++++++++++++++ display/holi-sde.dtsi | 375 +++++++---------------------------- 2 files changed, 317 insertions(+), 304 deletions(-) create mode 100644 display/holi-sde-common.dtsi diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi new file mode 100644 index 000000000000..95e9c2d00abf --- /dev/null +++ b/display/holi-sde-common.dtsi @@ -0,0 +1,246 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@5e00000 { + compatible = "qcom,sde-kms"; + reg = <0x05e00000 0x8f030>, + <0x05eb0000 0x2008>, + <0x05e8f000 0x030>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys"; + + clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; + clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 + 560000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-type = "none", "dsi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800>; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dsc-off = <0x81000>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + qcom,sde-mixer-stage-base-layer; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-highest-bank-bit = <0x0 0x1>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1e>; + qcom,sde-macrotile-mode = <0x0>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-dim-layer; + qcom,sde-max-bw-low-kbps = <5200000>; + qcom,sde-max-bw-high-kbps = <6200000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <1>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0xffff 0xffff 0x0 + 0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0 + 0x0 0x3ffff 0x3ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + + qcom,sde-secure-sid-mask = <0x821>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <32>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <1000>; + reg = <0x05e94000 0x400>, + <0x05f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x05e94400 0x800>, + <0x05e94a00 0x1e0>, + <0x05f01004 0x8>, + <0x05e94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_10nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 80]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + +}; diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 7c7a92e67ff9..2f9a7371774b 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -1,3 +1,4 @@ +#include "holi-sde-common.dtsi" #include &soc { @@ -6,201 +7,20 @@ label = "disp_rdump_region"; }; - mdss_mdp: qcom,mdss_mdp@5e00000 { - compatible = "qcom,sde-kms"; - reg = <0x05e00000 0x8f030>, - <0x05eb0000 0x2008>, - <0x05e8f000 0x030>; - reg-names = "mdp_phys", - "vbif_phys", - "sid_phys"; + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; - clocks = - <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_THROTTLE_CORE_CLK>, - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "throttle_clk", - "div_clk", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; - clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 - 560000000>; - - sde-vdd-supply = <&mdss_core_gdsc>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - #power-domain-cells = <0>; - - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary"; - - qcom,sde-mixer-off = <0x45000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-intf-off = <0x0 0x6b800>; - qcom,sde-intf-size = <0x2c0>; - qcom,sde-intf-type = "none", "dsi"; - qcom,sde-intf-tear-irq-off = <0 0x6e800>; - - qcom,sde-pp-off = <0x71000>; - qcom,sde-pp-size = <0xd4>; - - qcom,sde-dsc-off = <0x81000>; - qcom,sde-dsc-size = <0x140>; - - qcom,sde-dither-off = <0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "dma"; - - qcom,sde-sspp-off = <0x5000 0x25000>; - qcom,sde-sspp-src-size = <0x1f8>; - - qcom,sde-sspp-xin-id = <0 1>; - qcom,sde-sspp-excl-rect = <1 1>; - qcom,sde-sspp-smart-dma-priority = <2 1>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <0>; - qcom,sde-mixer-stage-base-layer; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; - qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-sspp-linewidth = <2160>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-mixer-linewidth = <2048>; - qcom,sde-mixer-blendstages = <0x4>; - qcom,sde-highest-bank-bit = <0x0 0x1>; - qcom,sde-ubwc-version = <0x200>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1e>; - qcom,sde-macrotile-mode = <0x0>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-dim-layer; - qcom,sde-has-idle-pc; - qcom,sde-max-bw-low-kbps = <5200000>; - qcom,sde-max-bw-high-kbps = <6200000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <1600000>; - qcom,sde-dram-channels = <1>; - qcom,sde-num-nrt-paths = <0>; - - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x2008>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - - qcom,sde-qos-refresh-rates = <60 120>; - qcom,sde-danger-lut = <0xffff 0xffff 0x0 - 0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0 - 0x0 0x3ffff 0x3ffff>; - - qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>; - - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - - qcom,sde-secure-sid-mask = <0x821>; - qcom,sde-num-mnoc-ports = <1>; - qcom,sde-axi-bus-width = <32>; - - /* data and reg bus scale settings */ - interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, - <&bimc MASTER_AMPSS_M0 - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 76800>, - <0 150000>, - <0 300000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "sde-vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; }; mdss_rotator: qcom,mdss_rotator { @@ -267,114 +87,61 @@ qcom,iommu-vmid = <0xa>; }; }; - - mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <1000>; - reg = <0x05e94000 0x400>, - <0x05f08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L22A>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <21800>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 { - compatible = "qcom,dsi-phy-v3.0"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0x05e94400 0x800>, - <0x05e94a00 0x1e0>, - <0x05f01004 0x8>, - <0x05e94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_10nm"; - vdda-0p9-supply = <&S5A_LEVEL>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 80]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = - ; - qcom,supply-max-voltage = - ; - qcom,supply-off-min-voltage = - ; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&apps_smmu 0x820 0x2>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-earlymap; /* for cont-splash */ - }; - - smmu_sde_sec: qcom,smmu_sde_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x0>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-vmid = <0xa>; - }; - +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "div_clk", "iface_clk", "core_clk", + "vsync_clk", "lut_clk", "rot_clk"; + sde-vdd-supply = <&mdss_core_gdsc>; + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-has-idle-pc; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L22A>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&S5A_LEVEL>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; }; From bc20148c32e5f843a1d1b20ad25f00e893e5de0b Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Sat, 22 Aug 2020 15:49:42 +0530 Subject: [PATCH 111/327] ARM: dts: msm: enable esd check for visionox panel on Shima This change enables esd check for r66451 visionox video and command mode panels on Shima target. Change-Id: I99b48f8f25241e6f6e8d8c9d9148e7caa9c83233 --- display/shima-sde-display.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 6a72d6a23c56..62c18c390559 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -143,6 +143,7 @@ }; &dsi_r66451_amoled_video { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -160,6 +161,12 @@ }; &dsi_r66451_amoled_60hz_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { @@ -172,6 +179,7 @@ }; &dsi_r66451_amoled_cmd { + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; From 35b1b526773970fddd664dd7a92fbc936f3c196d Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 27 Aug 2020 14:45:11 +0530 Subject: [PATCH 112/327] ARM: dts: msm: change max backlight level of visionox panel on Holi Change max backlight level of visionox rm69299 panel to 255 on Holi target. Change-Id: I8a28102119e65f446c16c2780dcf3d7e47adc332 --- display/holi-sde-display-atp.dtsi | 6 ++---- display/holi-sde-display-cdp.dtsi | 6 ++---- display/holi-sde-display-mtp.dtsi | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 5efaab6d6cf2..50e6d5d948d1 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -4,8 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; @@ -14,8 +13,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index f3b4ef6925c2..045a79255a76 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -4,8 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; @@ -14,8 +13,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 5efaab6d6cf2..50e6d5d948d1 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -4,8 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; @@ -14,8 +13,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <255>; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; From 61cbff0c97e74a93ee291b3611d35abcddd22223 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 26 Aug 2020 11:00:08 +0530 Subject: [PATCH 113/327] ARM: dts: msm: enable 120fps panel support on Shima This change enables 120fps support for r66451 visionox video mode panel on Shima target. Change-Id: Ic184dd9c2013f7ee9f149782f5b127e94cf0a0d5 --- display/shima-sde-display.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 6a72d6a23c56..71d4e35bad51 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -94,7 +94,6 @@ ibb-supply = <&ibb_vreg>; qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_video>; }; sde_dsi1: qcom,dsi-display-secondary { @@ -151,8 +150,8 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From 6b3949453ccd22e2a970eafd1fc4c520c9bc31d8 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Mon, 31 Aug 2020 15:21:07 -0400 Subject: [PATCH 114/327] ARM: dts: msm: Add Rounded Corner DTSI nodes to Holi target Add Rounded Corner feature DTSI nodes to Holi target. Change-Id: I355a14c0cf6d531ba5706c35a74c881746e4d8c9 --- display/holi-sde-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index 95e9c2d00abf..1fe879f007be 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -38,6 +38,11 @@ qcom,sde-dspp-off = <0x55000>; qcom,sde-dspp-size = <0x1800>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-intf-off = <0x0 0x6b800>; qcom,sde-intf-size = <0x2c0>; qcom,sde-intf-type = "none", "dsi"; From 931d3c40de958b9092ed5ddd314c6323e8174577 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 31 Aug 2020 20:06:18 +0530 Subject: [PATCH 115/327] ARM: dts: msm: Update default panel to 120Hz for shima Update default panel to 120Hz configuration for shima target. Change-Id: I1e5a50db0de9ff23579f6c2a2d821e158f55d623 --- display/shima-sde-display-idp.dtsi | 2 +- display/shima-sde-display.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index a19da7346b70..1f7dd6e22ca5 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -38,5 +38,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_video>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 915fcb443d56..72fa08d93e6d 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -12,8 +12,8 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; + qcom,supply-min-voltage = <1920000>; + qcom,supply-max-voltage = <1920000>; qcom,supply-enable-load = <60700>; qcom,supply-disable-load = <80>; qcom,supply-post-on-sleep = <20>; From d408887b2e1a41313a2d2f51bb0e1560d70f7dad Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Sat, 22 Aug 2020 15:44:08 +0530 Subject: [PATCH 116/327] ARM: dts: msm: enable dfps support for visionox panel on Shima This change enables dynamic fps support for r66451 visionox video mode panel on Shima target. Change-Id: I54d71bee57562ef920e58485abc42554e09536a9 --- display/shima-sde-display.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 72fa08d93e6d..a4d84a3f6033 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -148,6 +148,11 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <120 90 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { From fa987c0307265e5ea7f45334f137db6031f8a150 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 28 Aug 2020 16:22:47 +0530 Subject: [PATCH 117/327] ARM: dts: msm: create sde-display-common device tree on Shima Separate common SDE display bindings in sde-display-common dt file to avoid unwanted duplications between VM variants of the SDE display files on Shima target. Change-Id: Ibcb285e855a5474f9308f55032389c63d4725357 --- display/shima-sde-display-common.dtsi | 140 ++++++++++++++ display/shima-sde-display.dtsi | 255 +++++++------------------- 2 files changed, 206 insertions(+), 189 deletions(-) create mode 100644 display/shima-sde-display-common.dtsi diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi new file mode 100644 index 000000000000..6b1baacf6a4f --- /dev/null +++ b/display/shima-sde-display-common.dtsi @@ -0,0 +1,140 @@ +#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1920000>; + qcom,supply-max-voltage = <1920000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + qcom,mdp = <&mdss_mdp>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + qcom,mdp = <&mdss_mdp>; + }; +}; + +&dsi_r66451_amoled_video { + qcom,dsi-supported-dfps-list = <120 90 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index a4d84a3f6033..b2e706c34a36 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,134 +1,6 @@ -#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" -#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-sim-video.dtsi" -#include +#include "shima-sde-display-common.dtsi" &soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1920000>; - qcom,supply-max-voltage = <1920000>; - qcom,supply-enable-load = <60700>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <30000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - - qcom,panel-supply-entry@3 { - reg = <3>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - sde_dsi: qcom,dsi-display-primary { - compatible = "qcom,dsi-display"; - label = "primary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1", - "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 82 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; - - qcom,mdp = <&mdss_mdp>; - }; - - sde_dsi1: qcom,dsi-display-secondary { - compatible = "qcom,dsi-display"; - label = "secondary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; - - qcom,platform-te-gpio = <&tlmm 83 0>; - qcom,panel-te-source = <1>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - - qcom,mdp = <&mdss_mdp>; - }; - sde_wb: qcom,wb-display@0 { compatible = "qcom,wb-display"; cell-index = <0>; @@ -136,6 +8,71 @@ }; }; +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 83 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; +}; + + &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_dsi1>; @@ -148,20 +85,6 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <120 90 60 48>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-min-refresh-rate = <48>; - qcom,mdss-dsi-max-refresh-rate = <120>; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_60hz_video { @@ -171,15 +94,6 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; }; &dsi_r66451_amoled_cmd { @@ -189,41 +103,4 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 - 06 06 02 04 00 14 0a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 - 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <1 0 1>, - <2 0 1>; - qcom,default-topology-index = <0>; - }; - }; }; From a5284d9b5f66cd86a56ed3e85d6cecf020eec197 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 12:36:50 +0530 Subject: [PATCH 118/327] ARM: dts: msm: create sde-common device tree for shima target Separate common SDE bindings in sde-common dt file so that unwanted duplications between VM variants of SDE files can be avoided. Change-Id: I78563c64f1b505e42669e6680fed64f85d513f25 --- display/shima-sde-common.dtsi | 389 ++++++++++++++++++++++++++ display/shima-sde.dtsi | 513 +++++----------------------------- 2 files changed, 463 insertions(+), 439 deletions(-) create mode 100644 display/shima-sde-common.dtsi diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi new file mode 100644 index 000000000000..a3a5861c05e4 --- /dev/null +++ b/display/shima-sde-common.dtsi @@ -0,0 +1,389 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + clock-rate = <0 0 0 0 460000000 19200000 460000000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + + qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + qcom,sde-dsc-pair-mask = <2 1>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, + <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x7 0x1>, + <0x8 0x2>; + qcom,sde-ubwc-version = <0x400>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <5900000>; + qcom,sde-max-bw-high-kbps = <13500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff + 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; + + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, + <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; + + /* creq LUTs */ + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; + qcom,sde-qos-refresh-rates = <60 120>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-id = <0>; + qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801 0xC01>; + + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060000>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96400 0x800>, + <0xae96900 0x27c>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index e7a9fa86ef15..6e5e724c7e6e 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -1,274 +1,7 @@ +#include "shima-sde-common.dtsi" #include &soc { - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0xae00000 0x84208>, - <0xaeb0000 0x2008>, - <0xaeac000 0x214>, - <0xaf50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "swfuse_phys"; - clocks = - <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 0 0 460000000 19200000 460000000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - vdd-supply = <&disp_cc_mdss_core_gdsc>; - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none"; - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-intf-off = <0x6b000 0x6b800 - 0x6c000 0x6c800>; - qcom,sde-intf-size = <0x2b8>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; - - qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; - - qcom,sde-merge-3d-off = <0x84000 0x84100>; - qcom,sde-merge-3d-size = <0x100>; - - qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81400>; - qcom,sde-dsc-size = <0x140>; - qcom,sde-dsc-pair-mask = <2 1>; - - qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 - 0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "vig", - "dma", "dma", "dma"; - qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>; - qcom,sde-sspp-src-size = <0x1f8>; - qcom,sde-sspp-xin-id = <0 4 1 5 9>; - qcom,sde-sspp-excl-rect = <1 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0>; - - qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 - 4300000 4300000 - 4300000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; - qcom,sde-sspp-clk-status = - <0x2b0 0>, <0x2b8 0>, <0x2b0 12>, - <0x2b8 12>, <0x2c8 12>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2880>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-mixer-blendstages = <0x9>; - qcom,sde-highest-bank-bit = <0x7 0x1>, - <0x8 0x2>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-has-idle-pc; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <5900000>; - qcom,sde-max-bw-high-kbps = <13500000>; - qcom,sde-min-core-ib-kbps = <2500000>; - qcom,sde-min-llcc-ib-kbps = <0>; - qcom,sde-min-dram-ib-kbps = <1600000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010000>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - - /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff - 0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>; - - qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>, - <0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>; - - /* creq LUTs */ - qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>; - qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>; - qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>; - qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>; - qcom,sde-qos-refresh-rates = <60 120>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-id = <0>; - qcom,sde-reg-dma-version = <0x00010002>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x801 0xC01>; - - /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, - <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 74000>, - <0 148000>, - <0 265000>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - ext_disp: qcom,msm-ext-disp { status = "disabled"; compatible = "qcom,msm-ext-disp"; @@ -453,181 +186,83 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; +}; - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - frame-threshold-time-us = <800>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + vdd-supply = <&disp_cc_mdss_core_gdsc>; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-reg-bus"; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010000>; + /* offsets are based off dspp 0 and dspp 1 */ + qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-1"; - cell-index = <1>; - frame-threshold-time-us = <800>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - vdda-1p2-supply = <&L6B>; - refgen-supply = <&refgen>; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-0"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 { - compatible = "qcom,dsi-phy-v4.2"; - label = "dsi-phy-1"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96400 0x800>, - <0xae96900 0x27c>, - <0xaf03000 0x8>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; - pll-label = "dsi_pll_5nm"; - vdda-0p9-supply = <&L10C>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <37550>; - qcom,supply-disable-load = <0>; - }; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; }; }; }; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; From 76259444f1036fc97d02d9fd18c7fb7d4ff2d524 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 12:33:59 +0530 Subject: [PATCH 119/327] ARM: dts: msm: enable SDE RSC driver on shima Enable sde rscc v4 driver on shima target Change-Id: Ib0d930dfc6837f53edbff41970035ec0165586ae --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 16 ---------------- 2 files changed, 1 insertion(+), 17 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 915fcb443d56..27f33e0b435c 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -138,7 +138,7 @@ &mdss_mdp { connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi - &sde_dsi1>; + &sde_dsi1 &sde_rscc>; }; &dsi_r66451_amoled_video { diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6e5e724c7e6e..6cbbb353d36f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -147,7 +147,6 @@ sde_rscc: qcom,sde_rscc { cell-index = <0>; compatible = "qcom,sde-rsc"; - status = "disabled"; reg = <0xaf20000 0x4d68>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -200,7 +199,6 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, @@ -213,20 +211,6 @@ qcom,sde-dspp-ltm-version = <0x00010000>; /* offsets are based off dspp 0 and dspp 1 */ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi0 { From 5a00a4fda3a75b29ff1059d02d0748033f442bc2 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 3 Sep 2020 13:20:07 +0530 Subject: [PATCH 120/327] ARM: dts: msm: Enable Dynamic clock switch feature on Holi This change enables dynamic dsi clock switch feature for video and command mode visionox panel on Holi target. Change-Id: I6f79e6dfa14f21ca0647330cca3d581271559b9b --- display/holi-sde-display-common.dtsi | 11 ++++++++++- display/holi-sde.dtsi | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 808738871503..285cda97497c 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -78,7 +78,13 @@ qcom,dsi-supported-dfps-list = <60 55 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <952174080 948206688 956141472>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x31>; qcom,mdss-dsi-display-timings { @@ -93,6 +99,9 @@ &dsi_rm69299_visionox_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <929813440 925939216 922064992>; qcom,mdss-dsi-t-clk-post = <0x0E>; qcom,mdss-dsi-t-clk-pre = <0x31>; qcom,mdss-dsi-display-timings { diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 2f9a7371774b..fac819edfda5 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -144,4 +144,5 @@ vdda-0p9-supply = <&S5A_LEVEL>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; From 54f2fa30c41af22e04c5b63188f50ba65d5e2909 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Wed, 2 Sep 2020 15:07:40 +0530 Subject: [PATCH 121/327] ARM: dts: msm: Enable display port for shima Enable display port feature for shima target. Change-Id: Id62f46940f138ed97e7e0c9950c73b7964a7c763 --- display/shima-sde-display.dtsi | 2 +- display/shima-sde.dtsi | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 27f33e0b435c..4734603d6edf 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -137,7 +137,7 @@ }; &mdss_mdp { - connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; }; diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 6cbbb353d36f..7b2994593d5f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -3,7 +3,6 @@ &soc { ext_disp: qcom,msm-ext-disp { - status = "disabled"; compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { @@ -12,12 +11,10 @@ }; qcom_msmhdcp: qcom,msm_hdcp { - status = "disabled"; compatible = "qcom,msm-hdcp"; }; sde_dp: qcom,dp_display@ae90000 { - status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; From e49d587f53d5f42734a951783f27dc328bab0f80 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 18 Aug 2020 13:34:52 -0700 Subject: [PATCH 122/327] ARM: dts: msm: vote for higher VDDIO voltage for MTPv2.1 Change votes for higher VDDIO voltage, as unexpected high IR drops on MTPv2.1 are causing display instability. Change-Id: Ib06609fc2871f998829c0b6e75ba0aa527a8595b --- display/lahaina-sde-display-mtp-v2.1.dtsi | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/display/lahaina-sde-display-mtp-v2.1.dtsi b/display/lahaina-sde-display-mtp-v2.1.dtsi index e4b362c150f1..f7cd6321a220 100644 --- a/display/lahaina-sde-display-mtp-v2.1.dtsi +++ b/display/lahaina-sde-display-mtp-v2.1.dtsi @@ -1,3 +1,47 @@ +&dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <2000000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; From 078070d7f81789b0e1c0ce4f0c1dc0f073302e3b Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 4 Sep 2020 09:41:30 +0530 Subject: [PATCH 123/327] ARM: dts: msm: add trusted vm dtsi files for shima target Add trusted vm dt files for shima target. Common device tree bindings for shima are inherited in these files. Change-Id: I67e2191f964e5193c84652c8a2064ff64aadcdff --- display/trustedvm-shima-sde.dtsi | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 display/trustedvm-shima-sde.dtsi diff --git a/display/trustedvm-shima-sde.dtsi b/display/trustedvm-shima-sde.dtsi new file mode 100644 index 000000000000..86166909fcd5 --- /dev/null +++ b/display/trustedvm-shima-sde.dtsi @@ -0,0 +1,68 @@ +#include "shima-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>, + <0xaf50000 0x038>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "swfuse_phys"; + + qcom,sde-hw-version = <0x60070000>; + clocks = + <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From c90becc3ef11c12142a543efe7ca190d22f58d5f Mon Sep 17 00:00:00 2001 From: Naveen Kumar Date: Fri, 4 Sep 2020 21:52:22 +0530 Subject: [PATCH 124/327] Remove duplicate DT nodes entry Change-Id: Ifeb68e6a9f65eed6229ac161da3b03012ad2dd2c --- display/holi-sde-display-atp.dtsi | 10 ---------- display/holi-sde-display-mtp.dtsi | 10 ---------- display/shima-sde-display.dtsi | 12 ------------ 3 files changed, 32 deletions(-) diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 31b1d56673a8..50e6d5d948d1 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -18,16 +18,6 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; -&dsi_rm69299_visionox_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 23 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; -}; - &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 31b1d56673a8..50e6d5d948d1 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -18,16 +18,6 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; -&dsi_rm69299_visionox_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 23 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; -}; - &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index f0a18b62930c..a4d84a3f6033 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -182,18 +182,6 @@ }; }; -&dsi_r66451_amoled_60hz_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 - 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - &dsi_r66451_amoled_cmd { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From 9330658945100275483bf071a1ed838a0acfe1a6 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 8 Sep 2020 19:28:08 +0530 Subject: [PATCH 125/327] ARM: dts: msm: Add 60Hz command mode support on shima This change Add 60Hz command mode panel support on shima idp platform. Change-Id: I15a258debfee22c6a1eed29daf090ddedddd39d7 --- ...si-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi | 95 +++++++++++++++++++ display/shima-sde-display-common.dtsi | 13 +++ display/shima-sde-display-idp.dtsi | 11 +++ display/shima-sde-display.dtsi | 9 ++ 4 files changed, 128 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi new file mode 100644 index 000000000000..8bf39c27e5f5 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi @@ -0,0 +1,95 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_cmd: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox 60HZ panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 6b1baacf6a4f..17b6881b10e2 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -1,6 +1,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -99,6 +100,18 @@ }; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 + 03 03 02 04 00 0f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 1f7dd6e22ca5..3cb99c69fa0b 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -20,6 +20,17 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c9f2324b1aae..c13225ec0af7 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -96,6 +96,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_cmd { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From d77338dcddd85d6a6fa3344c036fb5667b2f0e92 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Wed, 9 Sep 2020 15:37:10 +0530 Subject: [PATCH 126/327] ARM: dts: msm: update default mdp clock value in holi This change updates default mdp clock to 448 MHZ for 120fps usecase to prevent underruns during continuous splash handoff. Change-Id: Ie0a4505699e8bb91b5f4d7ffa38a1257017eaa95 --- display/holi-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index 1fe879f007be..ca2ba7d915f7 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -10,7 +10,7 @@ "vbif_phys", "sid_phys"; - clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; + clock-rate = <0 0 0 0 0 448000000 19200000 448000000 200000000>; clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 560000000>; From d3c5a4e852a237583fc854e361ad0e8c95193a34 Mon Sep 17 00:00:00 2001 From: Vara Reddy Date: Wed, 9 Sep 2020 12:28:01 -0700 Subject: [PATCH 127/327] dt-bindings: update dynamic clock switch feature nodes Change adds dynamic clock switch feature enabling node "qcom,dsi-dyn-clk-enable", list of all dynamic clocks supported "qcom,dsi-dyn-clk-list" and node subtype with"qcom,dsi-dyn-clk-type". Change-Id: I1b6bc19e502e2d7019da5f569a830c3e05ac82a3 --- bindings/mdss-dsi-panel.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 69bdd72ee00e..01eb6805fb26 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -174,6 +174,22 @@ Optional properties: - qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh rate is not specified, then the frame rate of the panel in qcom,mdss-dsi-panel-framerate is used. +- qcom,dsi-dyn-clk-enable: Boolean to indicate dsi dynamic clock switch feature + is supported. +- qcom,dsi-dyn-clk-list: An u32 array which lists all the supported dsi bit clock + frequencies in Hz for the given panel. +- qcom,dsi-dyn-clk-type: A string that specifies the sub-type for the dynamic + clk feature. If dyn clk type is not specified, default + value "legacy" is used. + "legacy" = FPS is not maintained after dynamic clock switch. + "constant-fps-adjust-hfp" = FPS is maintained even after + dynamic clock switch by changing panel horizontal front + porch values. + "constant-fps-adjust-vfp" = FPS is maintained even after + dynamic clock switch by changing panel vertical front + porch values. + This dyn-clk-type entry is an optional binding which is + contingent on the enabling of dynamic clock switch. - qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight control for this panel. "bl_ctrl_pwm" = Backlight controlled by PWM gpio. From b00f333254a7282ddefbff062a3fd2a606ad160d Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Fri, 11 Sep 2020 20:05:04 +0530 Subject: [PATCH 128/327] ARM: dts: msm: update display ramdump node in holi Since the address & size cells for display ramdump's parent node(soc) is one, address & size should be defined in the 32-bit format instead of 64-bit. This change modifies them accordingly. Change-Id: I55b206126c2699cc3210a18295d5fa4dc22f145a --- display/holi-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index fac819edfda5..743eeb11844e 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -3,7 +3,7 @@ &soc { disp_rdump_memory: disp_rdump_region@85200000 { - reg = <0x0 0x85200000 0x0 0x00c00000>; + reg = <0x85200000 0x00c00000>; label = "disp_rdump_region"; }; From 34de1ed1ceec2678bbee9e9af55c682c30f0a7e0 Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 14 Sep 2020 11:58:33 -0700 Subject: [PATCH 129/327] ARM: dts: msm: update display_panel_avdd regulator type for Lahaina Change the compatible string for the display_panel_avdd regulator from "regulator-fixed" to "qti-regulator-fixed". This ensures that proxy-consumer properties of this regulator are properly handled at runtime. Change-Id: I5f58a0b72968df47503544950c55a785d1681d00 --- display/lahaina-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 60e9663d7420..3e3a389510da 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -18,7 +18,7 @@ &soc { display_panel_avdd: display_gpio_regulator@1 { - compatible = "regulator-fixed"; + compatible = "qti-regulator-fixed"; regulator-name = "display_panel_avdd"; regulator-min-microvolt = <5500000>; regulator-max-microvolt = <5500000>; From 66cf56895788d00b6c54a81fb68ebcea95013c81 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Thu, 10 Sep 2020 13:26:24 +0800 Subject: [PATCH 130/327] ARM: dts: msm: add 90hz video and cmd mode panel for holi Add 90hz video and cmd mode for r66451 panel. Change-Id: Ie80d6118e431687c7f10341c0d44a6120b349742 --- ...si-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi | 247 ++++++++++++++++++ ...-panel-r66451-dsc-fhd-plus-90hz-video.dtsi | 83 ++++++ display/holi-sde-display-common.dtsi | 37 +++ display/holi-sde-display-qrd.dtsi | 20 ++ display/holi-sde-display.dtsi | 19 ++ 5 files changed, 406 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi new file mode 100644 index 000000000000..3fedde23bf84 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi @@ -0,0 +1,247 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_90hz_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi new file mode 100644 index 000000000000..33adf7a3db27 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi @@ -0,0 +1,83 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_video: qcom,mdss_dsi_r66451_fhd_plus_90hz_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 285cda97497c..9d5201d29779 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -3,6 +3,8 @@ #include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi" #include &soc { @@ -155,3 +157,38 @@ }; }; }; + +&dsi_r66451_amoled_90hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index de64faa435fc..fcd4ddf34555 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -20,6 +20,26 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 026318b53148..a2da472f274f 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -80,3 +80,22 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_90hz_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From bb8b0f7335cbf2b1bc58dc69f1b725f733b4dc76 Mon Sep 17 00:00:00 2001 From: Raviteja Date: Wed, 16 Sep 2020 02:40:39 +0530 Subject: [PATCH 131/327] ARM: dts: msm: update display ramdump node in Lahaina Since the address & size cells for display ramdump's parent node(soc) is one, address & size should be defined in the 32-bit format instead of 64-bit. This change modifies them accordingly. Change-Id: Ib96fa68c494be73fd45049de530aeecd982fb8ef --- display/lahaina-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 870528fae30e..41286ac19ff8 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -3,7 +3,7 @@ &soc { disp_rdump_memory: disp_rdump_region@e1000000 { - reg = <0x0 0xe1000000 0x0 0x00800000>; + reg = <0xe1000000 0x00800000>; label = "disp_rdump_region"; }; From f35e32878f537508d2c114105c6050ae303edad3 Mon Sep 17 00:00:00 2001 From: Raviteja Date: Wed, 16 Sep 2020 02:25:16 +0530 Subject: [PATCH 132/327] ARM: dts: msm: add pm_qos cpu mask for silver cores on Shima target This change adds pm_qos cpu mask for all silver/performance cores which is applied for higher frame rates. Change-Id: Ie6f048af124d8738385e7bbc55f42b90621cff4f --- display/shima-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi index a3a5861c05e4..a03b19ed549a 100644 --- a/display/shima-sde-common.dtsi +++ b/display/shima-sde-common.dtsi @@ -174,6 +174,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From a4dcb49915dc0ed34f00dc486116aeb4ce7f6798 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 17 Sep 2020 10:33:38 +0530 Subject: [PATCH 133/327] ARM: dts: msm: define ramdump buffer reservation node This change defines ramdump buffer reservation node for shima target. Change-Id: Ib43f4690621524b8d55829e056b4cfdde79ef926 --- display/shima-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index 7b2994593d5f..d6f9872d200f 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -2,6 +2,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@e1000000 { + reg = <0xe1000000 0x02300000>; + label = "disp_rdump_region"; + }; + ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; From 1271e450970d4b4bb80ea9fd2d216d9bc636aaec Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Thu, 17 Sep 2020 13:09:56 +0530 Subject: [PATCH 134/327] ARM: dts: msm: define sid_phys for trusted vm in shima target Proper sid for trusted vm is selected via MDP_SID registers. Define sid_phys for trusted vm to support this. Change-Id: Ib2c924184adcf1f30a38f66c4ce6d42cdd79bd5f --- display/trustedvm-shima-sde.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-shima-sde.dtsi b/display/trustedvm-shima-sde.dtsi index 86166909fcd5..2f9f45c350e2 100644 --- a/display/trustedvm-shima-sde.dtsi +++ b/display/trustedvm-shima-sde.dtsi @@ -14,12 +14,15 @@ reg = <0xae00000 0x84208>, <0xaeb0000 0x2008>, <0xaeac000 0x214>, - <0xaf50000 0x038>; + <0xaf50000 0x038>, + <0xae8f000 0x02c>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "swfuse_phys"; + "swfuse_phys", + "sid_phys"; + qcom,sde-vm-exclude-reg-names = "sid_phys"; qcom,sde-hw-version = <0x60070000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 6fd9693080590b4e225dacac8d0e1ef7c9ded936 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 18 Sep 2020 09:34:51 +0530 Subject: [PATCH 135/327] ARM: dts: msm: add trusted vm display dtsi files for shima target Add trusted VM display device tree files for shima. Change-Id: I99cd70f232f941ecf084d225e4817b91b08a0253 --- display/trustedvm-shima-sde-display.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 display/trustedvm-shima-sde-display.dtsi diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi new file mode 100644 index 000000000000..dc497bf18f44 --- /dev/null +++ b/display/trustedvm-shima-sde-display.dtsi @@ -0,0 +1,35 @@ +#include "shima-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_MUX_1_CLK>, + <&clock_cpucc PCLK_MUX_1_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_1_CLK>, + <&clock_cpucc BYTECLK_SRC_1_CLK>, + <&clock_cpucc PCLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + + qcom,panel-te-source = <0>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; + +&mdss_mdp { + connectors = <&sde_dsi>; +}; From 451a7ebf06cde7014324090151af905ea78d3a96 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 18 Sep 2020 14:45:26 +0530 Subject: [PATCH 136/327] ARM: dts: msm: Add 60Hz cmd mode panel as default panel for trusted vm This change adds 60Hz command mode panel as the default panel for trusted vm in shima target. Change-Id: Ie66ea72eec7fcc8d966e4fd7846040fb8e990a51 --- display/trustedvm-shima-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi index dc497bf18f44..f70e3fc880cf 100644 --- a/display/trustedvm-shima-sde-display.dtsi +++ b/display/trustedvm-shima-sde-display.dtsi @@ -27,7 +27,7 @@ "shadow_byte_clk1", "shadow_pixel_clk1"; qcom,panel-te-source = <0>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; }; &mdss_mdp { From b8f4bad4fc40b3d1042e3a35efb0c112a118ca79 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sat, 12 Sep 2020 12:47:53 +0530 Subject: [PATCH 137/327] ARM: dts: msm: Enable dynamic clock switch on shima Enable Dynamic DSI clock switch feature for video and command mode panel on shima target. Change-Id: I858589096c938a8dbda857509ac2a3274dda283f --- display/shima-sde-display-common.dtsi | 11 ++++++++++- display/shima-sde.dtsi | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 17b6881b10e2..9a03e141c726 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -77,7 +77,13 @@ qcom,mdss-dsi-min-refresh-rate = <48>; qcom,mdss-dsi-max-refresh-rate = <120>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <846374400 842847840 844611120>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 @@ -102,6 +108,9 @@ &dsi_r66451_amoled_60hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <327096550 325733640 328459448>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi index d6f9872d200f..9f2455f8871a 100644 --- a/display/shima-sde.dtsi +++ b/display/shima-sde.dtsi @@ -245,6 +245,7 @@ vdda-0p9-supply = <&L10C>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; &mdss_dsi_phy1 { From 8ce917a7fff1ff129991a96e7c051a494dfce0f5 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Fri, 18 Sep 2020 14:06:45 +0530 Subject: [PATCH 138/327] ARM: dts: msm: Add LCD Video mode support on holi Add Qsync FHD Video mode support on holi lcd cdp. Change-Id: If4f44ab659dda1c9a755fe63c6b2f9aa849291ef --- display/holi-sde-display-cdp.dtsi | 8 ++ display/holi-sde-display-common.dtsi | 107 +++++++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 045a79255a76..eb0cf7a029f3 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -25,6 +25,14 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_sharp_qsync_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 9d5201d29779..73fbb4cc0efc 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -5,6 +5,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include &soc { @@ -52,6 +53,40 @@ }; }; + dsi_panel_pwr_supply_labibb: dsi_panel_pwr_supply_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; @@ -192,3 +227,75 @@ }; }; }; + +&dsi_sharp_qsync_fhd_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 07 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 05 be 00 10 00 10 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + }; +}; From 077d7a8314fb61aebbca7c937dacf4b48c1a5d86 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Fri, 11 Sep 2020 20:05:04 +0530 Subject: [PATCH 139/327] ARM: dts: msm: update display ramdump node in holi Since the address & size cells for display ramdump's parent node(soc) is one, address & size should be defined in the 32-bit format instead of 64-bit. This change modifies them accordingly. Change-Id: I55b206126c2699cc3210a18295d5fa4dc22f145a --- display/holi-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index fac819edfda5..743eeb11844e 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -3,7 +3,7 @@ &soc { disp_rdump_memory: disp_rdump_region@85200000 { - reg = <0x0 0x85200000 0x0 0x00c00000>; + reg = <0x85200000 0x00c00000>; label = "disp_rdump_region"; }; From c0ee6dede2aca2d8c3c6edbfd42019f23de4d805 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Thu, 10 Sep 2020 13:26:24 +0800 Subject: [PATCH 140/327] ARM: dts: msm: add 90hz video and cmd mode panel for holi Add 90hz video and cmd mode for r66451 panel. Change-Id: Ie80d6118e431687c7f10341c0d44a6120b349742 --- ...si-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi | 247 ++++++++++++++++++ ...-panel-r66451-dsc-fhd-plus-90hz-video.dtsi | 83 ++++++ display/holi-sde-display-common.dtsi | 37 +++ display/holi-sde-display-qrd.dtsi | 20 ++ display/holi-sde-display.dtsi | 19 ++ 5 files changed, 406 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi new file mode 100644 index 000000000000..3fedde23bf84 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi @@ -0,0 +1,247 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_90hz_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 11 c4 00 00 00 00 + 00 00 00 00 00 00 00 02 00 00 00 32 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 02 02 02 02 02 03 + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9c + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 a0 0a + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0a + 00 0a 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0a 00 32 00 0a 00 22 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 f1 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 39 04 09 34 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi new file mode 100644 index 000000000000..33adf7a3db27 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi @@ -0,0 +1,83 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_video: qcom,mdss_dsi_r66451_fhd_plus_90hz_video { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <95>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 285cda97497c..9d5201d29779 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -3,6 +3,8 @@ #include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi" #include &soc { @@ -155,3 +157,38 @@ }; }; }; + +&dsi_r66451_amoled_90hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x1D>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0B>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index de64faa435fc..fcd4ddf34555 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -20,6 +20,26 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 026318b53148..a2da472f274f 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -80,3 +80,22 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_90hz_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 6289e49f2b39f7c81531acba29b7b4904927f621 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Tue, 22 Sep 2020 11:49:52 +0530 Subject: [PATCH 141/327] ARM: dts: msm: define max trusted vm displays for shima Max trusted vm displays dt entry is used by both the vms to validate the TUI start request. Define this value for shima target. Change-Id: Ieef6e9cf184a58cebfcb1b4577c28215c6d28305 --- display/shima-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi index a03b19ed549a..8ed5332e3db4 100644 --- a/display/shima-sde-common.dtsi +++ b/display/shima-sde-common.dtsi @@ -140,6 +140,7 @@ qcom,sde-min-dram-ib-kbps = <1600000>; qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-uidle-off = <0x80000>; qcom,sde-uidle-size = <0x70>; From 6657a45746ea14d4f0abf79a1aba733c9cc304df Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Mon, 21 Sep 2020 13:33:47 +0530 Subject: [PATCH 142/327] ARM: dts: msm: remove regulator supply nodes in offline rotator SDE offline rotator uses mdss_mdp PM domain for regulator power supply. This change removes redundant regulator supply entries. Change-Id: Ia9e365af362b4a76c44faae621c2dfd972ad189b --- display/holi-sde.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 743eeb11844e..fa0b5a57eb8b 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -33,8 +33,6 @@ #list-cells = <1>; qcom,mdss-rot-mode = <1>; - rot-vdd-supply = <&mdss_core_gdsc>; - qcom,supply-names = "rot-vdd"; clocks = <&gcc GCC_DISP_AHB_CLK>, From 82b36f5105464d12e088ea7deac8d4171a488a67 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Mon, 14 Sep 2020 18:03:09 +0800 Subject: [PATCH 143/327] ARM: dts: msm: increase VFP value for video mode panel Low vbp+vfp may lead to perf issues in some cases, so increase vfp for video mode panel. Change-Id: I7f0daaf489fbf1320d0091b3094063daf9702ff0 --- display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 2 +- display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 2 +- display/lahaina-sde-display-common.dtsi | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 182038f97fab..995e4df38122 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -36,7 +36,7 @@ qcom,mdss-dsi-h-pulse-width = <1>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-front-porch = <75>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-on-command = [ diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi index ecac0d4bfc65..d7cd192a4fbd 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi @@ -37,7 +37,7 @@ qcom,mdss-dsi-h-pulse-width = <12>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-front-porch = <20>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-h-left-border = <0>; qcom,mdss-dsi-panel-framerate = <60>; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 923309e61b86..5e4afa5c83f2 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -151,7 +151,7 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; @@ -168,8 +168,8 @@ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 - 08 05 02 04 00 17 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 16 07 + 07 08 02 04 00 19 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From 8df9b3e146025c2143596ece8e1d74eb10a52490 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Fri, 11 Sep 2020 14:25:46 +0800 Subject: [PATCH 144/327] ARM: dts: msm: fix nt35597 panel video mode ESD check failure Change the VBP and VFP values to fix ESD check failure. Change-Id: I1083c50557fe1e7eb21785691bddec077962443f --- display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi index 417d22e3c8b5..63e65adbcce9 100644 --- a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi +++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -39,8 +39,8 @@ qcom,mdss-dsi-h-back-porch = <32>; qcom,mdss-dsi-h-pulse-width = <16>; qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <17>; - qcom,mdss-dsi-v-front-porch = <23>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <33>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-on-command = [ From d22c4097a10df22792421f552ec5991785835ec0 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 20 Aug 2020 12:43:24 +0530 Subject: [PATCH 145/327] ARM: dts: msm: enable ulps for visionox panel on Holi This change enables ulps support for visionox panel on Holi target. Change-Id: Ib2258c765fbc0b89169a322274ae16ef785b61aa --- display/holi-sde-display.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index a2da472f274f..e7470d8ab77d 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -53,6 +53,7 @@ }; &dsi_rm69299_visionox_amoled_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From a3196c14915a041d5f58594f0ada01039a8b7531 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Mon, 21 Sep 2020 18:51:29 +0800 Subject: [PATCH 146/327] ARM: dts: msm: add r66451 video mode 60hz panel support Adds visionox r66451 amoled video mode 60Hz dsi panel for holi target. Change-Id: I718f004d969a8a3f2c8abb239f789f878b62ce85 --- ...dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi | 2 +- ...i-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 2 +- display/holi-sde-display-common.dtsi | 14 ++++++++++++++ display/holi-sde-display-qrd.dtsi | 18 ++++++++++++++---- display/holi-sde-display.dtsi | 5 +++++ 5 files changed, 35 insertions(+), 6 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi index 8bf39c27e5f5..7674b87a769f 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_60hz_cmd: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_cmd { qcom,mdss-dsi-panel-name = - "r66451 amoled cmd mode dsi visionox 60HZ panel with DSC"; + "r66451 amoled cmd mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,mdss-dsi-virtual-channel-id = <0>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi index 50e11b87af55..310f28f3ee28 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_visionox_r66451_fhd_plus_60hz_video { qcom,mdss-dsi-panel-name = - "r66451 amoled video mode dsi visionox 60Hz panel with DSC"; + "r66451 amoled video mode dsi visionox panel with DSC"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 73fbb4cc0efc..78050aea9671 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -5,6 +5,8 @@ #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include @@ -228,6 +230,18 @@ }; }; +&dsi_r66451_amoled_60hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_qsync_fhd_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0c>; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index fcd4ddf34555..b079622c2f64 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -4,7 +4,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; @@ -14,7 +14,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; @@ -24,7 +24,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; @@ -34,12 +34,22 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index a2da472f274f..94670b7bc95e 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -79,6 +79,11 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-min-refresh-rate = <60>; + qcom,mdss-dsi-max-refresh-rate = <120>; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; }; &dsi_r66451_amoled_90hz_cmd { From 2df8b4cbe845e85b8b7c862f1c5f8206079a8e0a Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 25 Sep 2020 13:13:48 +0530 Subject: [PATCH 147/327] ARM: dts: msm: Change VDDIO and default panel on shima idp Update VDDIO panel power supply to 1.82V and select 60Hz command mode panel as default on shima IDP platform. Change-Id: I7620cddbe0274127dfa5df78baebd1a4bbbb8037 --- display/shima-sde-display-common.dtsi | 4 ++-- display/shima-sde-display-idp.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 9a03e141c726..69fa6501c5f4 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -13,8 +13,8 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1920000>; - qcom,supply-max-voltage = <1920000>; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; qcom,supply-enable-load = <60700>; qcom,supply-disable-load = <80>; qcom,supply-post-on-sleep = <20>; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 3cb99c69fa0b..151582b85217 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -49,5 +49,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; }; From 11737ba21af09c3b143f9e8d4f23832ee567c6ad Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 23 Sep 2020 18:54:04 +0530 Subject: [PATCH 148/327] ARM: dts: msm: enable DSI PHY power off when idle on Holi This change adds the feature which disables the DSI PHY hardware while going to idle screen on Holi target. Change-Id: I415bec33f2c7b42d99d783f678ff38948e0ab2a7 --- display/holi-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index fa0b5a57eb8b..c6d3d332a98a 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -140,6 +140,7 @@ &mdss_dsi_phy0 { vdda-0p9-supply = <&S5A_LEVEL>; + qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; memory-region = <&dfps_data_memory>; From dde33fb2e89b09b2193bfb9b616d32bfbccadce7 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Wed, 23 Sep 2020 20:39:56 +0530 Subject: [PATCH 149/327] ARM: dts: msm: Add LCD Command mode support on holi Add Qsync FHD Command mode support on holi lcd cdp. Change-Id: I1c79f098a8eb00132faf917287c1b0158a77a878 --- display/holi-sde-display-cdp.dtsi | 11 +- display/holi-sde-display-common.dtsi | 214 +++++++++++++++++++++++++++ 2 files changed, 224 insertions(+), 1 deletion(-) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index eb0cf7a029f3..501b2a615690 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -29,7 +29,16 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sharp_qsync_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 78050aea9671..4ffa9be16ad1 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -8,6 +8,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-video.dtsi" +#include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" #include &soc { @@ -313,3 +314,216 @@ }; }; }; + +&dsi_sharp_qsync_fhd_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03 + 03 02 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + + timing@1 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 + 05 06 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 00 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + + timing@2 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1e 1e 04 + 04 03 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 03 + 39 01 00 00 00 00 02 17 70 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + }; + }; +}; From cef87d2a2c3df1c26a36ffb6b387463e86741edc Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 24 Sep 2020 09:50:00 +0530 Subject: [PATCH 150/327] ARM: dts: msm: Add 144 fps support on shima target Add 144 fps panel display support on shima target. Change-Id: Ic70a4aec92fabb6c284dc5f36783cba9f4d04751 --- display/shima-sde-display-common.dtsi | 13 +++++++++++++ display/shima-sde-display-idp.dtsi | 11 +++++++++++ 2 files changed, 24 insertions(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 9a03e141c726..d601cb6cb167 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -2,6 +2,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -121,6 +122,18 @@ }; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 3cb99c69fa0b..9b5ef968a80a 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -42,6 +42,17 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 2b23cefb30bab6cd4f49efccac114107b8940063 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Mon, 28 Sep 2020 10:51:34 +0530 Subject: [PATCH 151/327] ARM: dts: msm: Enable ESD for 144 fps panel on shima target Enabling ESD for 144fps panel on shima target. Change-Id: I58e04b573125d058700e75c580e94b5acacfd270 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c13225ec0af7..190d87b4dda2 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -113,3 +113,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_144hz_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 4f090abc16324d89a44f10e4e91bdeb11a0e3807 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Fri, 18 Sep 2020 13:35:04 +0800 Subject: [PATCH 152/327] ARM: dts: msm: update vddio for r66451 panel Panel will dead sometimes because of power consumption high on r66451 panel, but the current max vddio can't reach, so updata max vddio for r66451 panel for holi qrd. Change-Id: I7c32c2fea7dedbeb5264c06a1af1410fbfe740fe --- display/holi-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index b079622c2f64..4d4feddfc61c 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ #include "holi-sde-display.dtsi" +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; + }; +}; + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From bfc088976cf002dece9ccfc3441b864a957584cc Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Mon, 28 Sep 2020 13:24:40 +0800 Subject: [PATCH 153/327] ARM: dts: msm: update r66451 video panel phy-timing for holi update r66451 video panel phy-timing for holi target. Change-Id: Iaae6c5eeee6455143c0155a57547437ecf269d54 --- display/holi-sde-display-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 4ffa9be16ad1..83a1a9196bb9 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -188,8 +188,8 @@ qcom,mdss-dsi-t-clk-pre = <0x27>; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00]; + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 23 22 07 + 07 08 02 04 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; From d7808793e0caedb2c08dc54b5afe322e54d898d5 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Fri, 7 Aug 2020 13:49:25 +0800 Subject: [PATCH 154/327] ARM: dts: msm: add ext bridge 1080p config for hdk8350 Add external bridge 1080p panel timing configure. Change-Id: Ib6a7171f9983c2eeb858f0783cc3ba0307dd75af --- display/lahaina-sde-display-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 5e4afa5c83f2..c23cc4f3a018 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -746,3 +746,15 @@ }; }; }; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 00 1a 0c]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; From 29b90dddd8ea8cec062f38c85fa74d7c682a8732 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Tue, 29 Sep 2020 14:32:52 +0530 Subject: [PATCH 155/327] ARM: dts: msm: Enable POMS feature for qsync panel on holi This change enables POMS feature on sharp qsync fhd video mode panel on holi. Change-Id: I843e2bc9908fa147798d1afa05b4ab87d51937f8 --- display/dsi-panel-sharp-qsync-fhd-video.dtsi | 1 + display/holi-sde-display-common.dtsi | 123 +++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/display/dsi-panel-sharp-qsync-fhd-video.dtsi b/display/dsi-panel-sharp-qsync-fhd-video.dtsi index 61f6078c69cd..185f32603582 100644 --- a/display/dsi-panel-sharp-qsync-fhd-video.dtsi +++ b/display/dsi-panel-sharp-qsync-fhd-video.dtsi @@ -12,6 +12,7 @@ qcom,mdss-dsi-bpp = <24>; qcom,mdss-dsi-border-color = <0>; qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; qcom,mdss-dsi-bllp-eof-power-mode; qcom,mdss-dsi-lane-0-state; qcom,mdss-dsi-lane-1-state; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 4ffa9be16ad1..bb0c67aed6d3 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -249,8 +249,16 @@ qcom,mdss-dsi-t-clk-pre = <0x2c>; qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-panel-mode-switch; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; qcom,mdss-dsi-display-timings { timing@0 { + qcom,mdss-dsi-video-mode; qcom,mdss-dsi-panel-width = <1080>; qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 07 07 02 04 00]; @@ -311,6 +319,121 @@ 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29 ]; + qcom,cmd-to-video-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 05 be 00 10 00 10 + ]; + qcom,cmd-to-video-mode-post-switch-commands-state = + "dsi_lp_mode"; + }; + + timing@1 { + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03 + 03 02 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,video-to-cmd-mode-post-switch-commands = [ + 39 00 00 00 00 00 02 ff 10 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 bb 10 + 39 00 00 00 00 00 02 ff 24 + 39 00 00 00 00 00 02 fb 01 + 39 00 00 00 00 00 02 14 00 + 39 00 00 00 00 00 02 15 10 + 39 00 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + ]; + qcom,video-to-cmd-mode-post-switch-commands-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; }; }; }; From ef5bbdabe3d71e92c760b29105d712c64461062c Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 29 Sep 2020 10:04:33 -0700 Subject: [PATCH 156/327] ARM: dts: msm: update init sequence for video mode for sharp qsync panel Change updates the init sequence for the video timing nodes to allow POMS switch to happen successfully even when we turn the panel on in video mode. Change-Id: I2088add09a607f53b1cca82a8f2b9baa6411c120 --- display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi index f8b7496b94cc..c0cba71a1e74 100644 --- a/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi +++ b/display/dsi-panel-sharp-qsync-wqhd-cmd.dtsi @@ -198,7 +198,7 @@ 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 05 be 00 10 00 10 @@ -210,6 +210,12 @@ 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 @@ -640,7 +646,7 @@ 39 01 00 00 00 00 02 de 00 39 01 00 00 00 00 02 e1 00 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 03 + 39 01 00 00 00 00 02 bb 10 39 01 00 00 00 00 02 f6 70 39 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 05 be 00 10 00 10 @@ -652,6 +658,12 @@ 39 01 00 00 00 00 02 5d 00 39 01 00 00 00 00 02 5e 14 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 10 39 01 00 00 00 00 02 ff 26 39 01 00 00 00 00 02 fb 01 39 01 00 00 00 00 02 60 00 From 1baf4047c24253aa40977514a68a7b414a752992 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 30 Sep 2020 10:29:30 +0530 Subject: [PATCH 157/327] ARM: dts: msm: Enable ULPS feature on Shima Enable ULPS feature for 60Hz and 120Hz command mode panel on shima platform. Change-Id: If9465cd11508d0da4a755fff3cf2358cea0ecc3b --- display/shima-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 190d87b4dda2..d1d9826fe587 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -97,6 +97,7 @@ }; &dsi_r66451_amoled_60hz_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -106,6 +107,7 @@ }; &dsi_r66451_amoled_cmd { + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From 5eb804e605a7a2e76047b42335737b29a55ea90d Mon Sep 17 00:00:00 2001 From: Raviteja Tamatam Date: Wed, 30 Sep 2020 17:50:19 +0530 Subject: [PATCH 158/327] bindings: Documentation: add property to specify qsync min fps list Add documentation for the property to specify list of fps that indicates the qsync min fps corresponding to the mode in the dfps list with same index. Change-Id: I1f0c75c7b473f7c5328525e777e13a1a3d916773 --- bindings/mdss-dsi-panel.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 01eb6805fb26..086fb76f0c73 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -170,6 +170,11 @@ Optional properties: "dfps_immediate_porch_mode_vfp" = FPS change request is implemented immediately by changing panel vertical front porch values. +- qcom,dsi-supported-dfps-list: List containing all the supported refresh rates. +- qcom,dsi-supported-qsync-min-fps-list: The fps value in this list indicates the qsync min fps + corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. + qcom,dsi-supported-qsync-min-fps-list cannot be defined along with + qcom,mdss-dsi-qsync-min-refresh-rate. - qcom,min-refresh-rate: Minimum refresh rate supported by the panel. - qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh rate is not specified, then the frame rate of the panel in @@ -731,6 +736,8 @@ Example: qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; + qcom,dsi-supported-dfps-list = <30 45 60>; + qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; qcom,min-refresh-rate = <30>; qcom,max-refresh-rate = <60>; qcom,mdss-dsi-bl-pmic-bank-select = <0>; From e771477ef8892a343a53d02a5bf85ca5d3281d69 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 1 Oct 2020 15:39:39 +0530 Subject: [PATCH 159/327] ARM: dts: msm: fix phy timing array size of sim panel on Holi This change fixes the phy timing array size of video sim panel on Holi target. Change-Id: I1d8364cd6d7460219498d812ab5263f29995a41d --- display/holi-sde-display-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 83a1a9196bb9..2dc88cc3b208 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -104,10 +104,12 @@ &dsi_sim_vid { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 + 07 05 02 04 00]; qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; }; From 864455d5dea145588056514bf0f9de422dc083aa Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Wed, 30 Sep 2020 10:52:10 +0530 Subject: [PATCH 160/327] ARM: dts: msm: Add support for dual display on shima This change adds support for 2 independent displays on shima for both video and command modes. Change-Id: Ia61230e5694a93fe115371557ba59de3738b0801 --- display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi | 3 +++ display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi | 2 ++ display/shima-sde-display-common.dtsi | 2 ++ display/shima-sde-display-idp.dtsi | 6 ++++++ 4 files changed, 13 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi index 7674b87a769f..6f408edc7be9 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi @@ -14,6 +14,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-lane-map = "lane_map_0123"; qcom,mdss-dsi-bllp-eof-power-mode; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi index 310f28f3ee28..1b00915032df 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi @@ -6,6 +6,8 @@ qcom,mdss-dsi-panel-physical-type = "oled"; qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; qcom,mdss-dsi-virtual-channel-id = <0>; qcom,mdss-dsi-stream = <0>; qcom,mdss-dsi-bpp = <24>; diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index d601cb6cb167..8dd9fd76391c 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -97,6 +97,7 @@ &dsi_r66451_amoled_60hz_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 @@ -109,6 +110,7 @@ &dsi_r66451_amoled_60hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <327096550 325733640 328459448>; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 9b5ef968a80a..5bbc92e9c622 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -12,23 +12,29 @@ &dsi_r66451_amoled_60hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_r66451_amoled_60hz_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-te-gpio = <&tlmm 82 0>; qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-sec-reset-gpio = <&tlmm 25 0>; }; &dsi_r66451_amoled_cmd { From 9ef4a0ccfe231d356a4451ede4037363032f5d01 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 1 Oct 2020 17:17:46 +0530 Subject: [PATCH 161/327] ARM: dts: msm: Enable Partial Update feature on holi Enable partial update feature for sharp qsync fhd 60hz command mode panel on holi target. Change-Id: I47bc60ae60d2b6dbcfbe833c61d90e8577fe4830 --- .../dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi | 131 ++++++++++++++++++ display/holi-sde-display-cdp.dtsi | 9 ++ display/holi-sde-display-common.dtsi | 17 +++ 3 files changed, 157 insertions(+) create mode 100644 display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi diff --git a/display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi b/display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi new file mode 100644 index 000000000000..ff985394e844 --- /dev/null +++ b/display/dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi @@ -0,0 +1,131 @@ +&mdss_mdp { + dsi_sharp_qsync_fhd_60hz_cmd: qcom,mdss_dsi_sharp_qsync_fhd_60hz_cmd { + qcom,mdss-dsi-panel-name = "Sharp qsync fhd cmd mode single dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <134>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 40 + 39 01 00 00 10 00 02 f1 40 + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 10 00 06 2c 01 02 04 08 10 + 39 01 00 00 00 00 02 ff d0 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 10 00 02 f1 00 + /* Initial Setting */ + 39 01 00 00 00 00 02 ff 10 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 ba 07 + 39 01 00 00 00 00 02 bc 08 + 39 01 00 00 00 00 02 c0 85 + 39 01 00 00 00 00 11 c1 89 28 00 08 02 + 00 02 0e 00 bb 00 07 0d b7 0c b7 + 39 01 00 00 00 00 03 c2 10 f0 + 39 01 00 00 00 00 02 d5 00 + 39 01 00 00 00 00 02 d6 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 e1 00 + 39 01 00 00 00 00 02 e5 01 + 39 01 00 00 00 00 02 bb 10 + 39 01 00 00 00 00 02 f6 70 + 39 01 00 00 00 00 02 f7 80 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 ff 20 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 5d 00 + 39 01 00 00 00 00 02 5e 14 + 39 01 00 00 00 00 02 5f eb + 39 01 00 00 00 00 02 ff 24 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 16 0a + 39 01 00 00 00 00 02 17 30 + 39 01 00 00 00 00 02 ff 26 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 60 00 + 39 01 00 00 00 00 02 62 01 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 ff 28 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 91 02 + 39 01 00 00 00 00 02 ff e0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 48 81 + 39 01 00 00 00 00 02 8e 09 + 39 01 00 00 00 00 02 ff f0 + 39 01 00 00 00 00 02 fb 01 + 39 01 00 00 00 00 02 33 20 + 39 01 00 00 00 00 02 34 35 + 39 01 00 00 00 00 02 ff 10 + 05 01 00 00 78 00 01 11 + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bc 00 + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 501b2a615690..a1a4df09a9b3 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -42,6 +42,15 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_sharp_qsync_fhd_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 985fafa82d2a..47b651b60bf0 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -9,6 +9,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" +#include "dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi" #include &soc { @@ -652,3 +653,19 @@ }; }; }; + +&dsi_sharp_qsync_fhd_60hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03 + 03 02 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 8 8 8 1080 8>; + }; + }; +}; From e7e022ff002752fa977e3e423cea85926f183a6d Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 5 Oct 2020 22:31:24 +0530 Subject: [PATCH 162/327] ARM: dts: msm: add r66451 120Hz DSI panel support on Holi CDP This change adds visionox r66451 120Hz amoled video and command mode dsi panel on Holi CDP platform. Change-Id: Icb4f1c506fd497cc8f05fbd77199ef3072c59287 --- display/holi-sde-display-cdp.dtsi | 20 +++++++++++++ display/holi-sde-display-common.dtsi | 44 ++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index a1a4df09a9b3..4da9c2161107 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -51,6 +51,26 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vddio_182>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vddio_182>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 47b651b60bf0..8796a6e5c02f 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -57,6 +57,50 @@ }; }; + dsi_panel_pwr_supply_vddio_182: dsi_panel_pwr_supply_vddio_182 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + dsi_panel_pwr_supply_labibb: dsi_panel_pwr_supply_labibb { #address-cells = <1>; #size-cells = <0>; From aefdd854250e4ad6d67ded953dfdff1249ab9b0e Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Wed, 30 Sep 2020 16:15:01 -0400 Subject: [PATCH 163/327] ARM: dts: msm: Introduce dummy demura panel ID node ABL expects a demura panel ID node to always be present under the DSI display definition. If this node is not present, ABL is unable to insert it and demura continuous splash can not be brought online. Introduce a dummy demura panel ID node into the device tree. This node is given a panel ID of 0 to allow the kernel to specially handle it. Change-Id: I4da25f02152c6410d4e67868f702149a7a81bd4c --- bindings/sde-dsi.txt | 2 ++ display/lahaina-sde-display-common.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt index 8e720f75f1ee..daad29293deb 100644 --- a/bindings/sde-dsi.txt +++ b/bindings/sde-dsi.txt @@ -42,6 +42,8 @@ Required properties: - interrupts: The interrupt signal from the DSI block. - qcom,dsi-default-panel: Specifies the default panel. - qcom,mdp: Specifies the mdp node which can find panel node from this. +- qcom,demura-panel-id: Specifies the u64 demura panel ID as an array <2> + If demura is not used this node must be set to <0,0>. Bus Scaling Data: - qcom,msm-bus,name: String property describing MDSS client. diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index c23cc4f3a018..5e75e63013cd 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -107,6 +107,7 @@ qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; + qcom,demura-panel-id = <0x0 0x0>; }; sde_dsi1: qcom,dsi-display-secondary { @@ -116,6 +117,7 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; }; }; From c9c8e77f49480c0a0a5a15c98c31a17f794b0019 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Mon, 12 Oct 2020 10:37:35 +0530 Subject: [PATCH 164/327] ARM: dts: msm: Add support for cphy video mode panel on shima This change adds support for cphy video mode panel on shima platform. Change-Id: I5e18853bb8bf8560fbecb8012c550e363adec50c --- display/shima-sde-display-common.dtsi | 14 ++++++++++++++ display/shima-sde-display-idp.dtsi | 10 ++++++++++ 2 files changed, 24 insertions(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 277df1f64085..95d7ee0a9079 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -3,6 +3,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -136,6 +137,19 @@ }; }; +&dsi_r66451_amoled_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 6db7f7e5dbf1..fd96a123258d 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -59,6 +59,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From d8b3c5f95c5cc5527b0af17f21c1c9a7cac247c3 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Mon, 12 Oct 2020 10:42:57 +0530 Subject: [PATCH 165/327] ARM: dts: msm: Enable ESD for cphy video mode panel on shima This change enables ESD for cphy video mode panel on shima target. Change-Id: Ica177fe8f0d51a43d1b32cb54c736fc29c1d4002 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d1d9826fe587..c8b0ed462c34 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -124,3 +124,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_video_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From e7985a7f8cfb3200006fce4508064d79f1e7c76a Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 8 Oct 2020 15:52:21 +0530 Subject: [PATCH 166/327] ARM: dts: msm: update topology to 111 for 60fps on shima Updating topology to 111 for 60fps on shima target. Change-Id: If64ccb535a46d0aaf9dfc11113dca9f6d7882827 --- display/shima-sde-display-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 95d7ee0a9079..7647aef3b1ac 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -103,7 +103,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 11 04 04 03 02 04 00 0e 09]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -119,7 +119,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 03 03 02 04 00 0f 13]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; }; }; From 8123d5ff02277388f121ee7bd7a44f766ab33a2e Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:20:24 +0530 Subject: [PATCH 167/327] ARM: dts: msm: Add support for sharp qhd dual dsi on shima This change adds support for sharp qhd dual dsi panel on shima platform. Change-Id: I258d1718c611433a06244ae95f02afab86b2dbda --- display/shima-sde-display-common.dtsi | 20 ++++++++++++++++++++ display/shima-sde-display-idp.dtsi | 13 +++++++++++++ 2 files changed, 33 insertions(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 7647aef3b1ac..d6e548f33235 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -4,6 +4,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -150,6 +151,25 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index fd96a123258d..3c07eaa27ac0 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -68,6 +68,17 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; +}; &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; @@ -76,5 +87,7 @@ }; &sde_dsi { + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-2 = <&lcd_backlight_ctrl_default>; qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; }; From 901c275c476481d272660851d9466e66bd284803 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:22:15 +0530 Subject: [PATCH 168/327] ARM: dts: msm: Enable ESD for sharp qhd dual dsi panel on shima This change enables ESD for sharp qhd dual dsi panel on shima target. Change-Id: I3d1b8b3ff09a58fc15d3f09062b8cb02b2a2a8f3 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c8b0ed462c34..576da914f8b6 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -133,3 +133,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 606afd50197686d42c4504e0cc25a73dc5734b22 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Wed, 21 Oct 2020 13:09:09 +0530 Subject: [PATCH 169/327] ARM: dts: msm: enable qsync along with VRR in shima target This change enables qsync support for shima target along with exisiting VRR. The required concurrency changes are already included in the commit 30b1dd339b45 ("disp: msm: sde: support qsync and vrr in same atomic commit"). Change-Id: I699334dc999857a8938bcb84d2ac4ca1386252c2 --- display/shima-sde-display-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index d601cb6cb167..eaef2892003a 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -78,6 +78,7 @@ qcom,mdss-dsi-min-refresh-rate = <48>; qcom,mdss-dsi-max-refresh-rate = <120>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0"; From c791642b71ad8d1962c01684dd18c05fdbc53123 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 21 Oct 2020 15:51:42 +0530 Subject: [PATCH 170/327] ARM: dts: msm: change default panel for trusted vm for shima target Use 120 fps command mode panel as the default panel for trusted vm for shima target. Change-Id: Ic7f24ac362a9ca51e8bd3a46b5625965c50901be --- display/trustedvm-shima-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi index f70e3fc880cf..dc497bf18f44 100644 --- a/display/trustedvm-shima-sde-display.dtsi +++ b/display/trustedvm-shima-sde-display.dtsi @@ -27,7 +27,7 @@ "shadow_byte_clk1", "shadow_pixel_clk1"; qcom,panel-te-source = <0>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_60hz_cmd>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; }; &mdss_mdp { From f970da119bc2dc083fe317503e6ede7cbf9fa671 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Thu, 22 Oct 2020 10:17:02 +0800 Subject: [PATCH 171/327] ARM: dts: msm: increase vddio for r66451 panel Increase vddio to 1.86v for qrd. Change-Id: I97f9b6b500ba023c01e80274524427d5552b2f90 --- display/holi-sde-display-qrd.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index 4d4feddfc61c..39f497d72ae7 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -2,8 +2,8 @@ &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { - qcom,supply-min-voltage = <1820000>; - qcom,supply-max-voltage = <1820000>; + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; }; }; From 35765d9d880d87be4368d54e06fa5174d4b7bee3 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:04:42 +0530 Subject: [PATCH 172/327] ARM: dts: msm: Add support for cphy command mode panel on shima This change adds support for cphy command mode panel on shima platform. Change-Id: I7ced651418954fa4c644422d59afe7cbe6162cf1 --- .../dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi | 2 +- display/shima-sde-display-common.dtsi | 14 ++++++++++++++ display/shima-sde-display-idp.dtsi | 10 ++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi index 8b540370ae41..443762b291b8 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi @@ -60,7 +60,7 @@ 39 01 00 00 00 00 02 b0 80 39 01 00 00 00 00 02 e6 00 39 01 00 00 00 00 02 b0 00 - 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 06 B6 6c 00 06 23 af 39 01 00 00 00 00 02 B4 20 39 01 00 00 00 00 19 cf 64 0b 00 00 00 00 00 00 08 00 0b 77 01 01 01 01 01 diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 27325abd1380..7006dffcdd0b 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -5,6 +5,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-sim-video.dtsi" #include @@ -171,6 +172,19 @@ }; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 3c07eaa27ac0..54c0f4fa4349 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -80,6 +80,16 @@ qcom,platform-en-gpio = <&tlmm 47 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 6bf20a6ee289500f133dcac5ace9f1fdd44f5e2e Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 11:08:19 +0530 Subject: [PATCH 173/327] ARM: dts: msm: Enable ESD for cphy command mode panel on shima This change enables ESD for cphy command mode panel on shima target. Change-Id: Ia70e000f0ac4a3d9cb144b05d8c3b7debece76a5 --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index 576da914f8b6..c4ad6d8c83fc 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -142,3 +142,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From b6b7549bbbde9a244b2dddf8865526e57d968b65 Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Thu, 29 Oct 2020 11:43:01 -0700 Subject: [PATCH 174/327] ARM: dts: msm: update INTF HW block size This change updates hardware INTF block size to right size as per Lahaina SWI. Change-Id: I0301c548a537cfd380a845b9e092a6bc8a442d03 --- display/lahaina-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 3730cc8d6dd7..9c009d960baf 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -62,7 +62,7 @@ qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; - qcom,sde-intf-size = <0x2c0>; + qcom,sde-intf-size = <0x2c4>; qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; From 3e1b332e301c6e023f7fb4ed8a2dc9d21bd92891 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 22 Oct 2020 16:32:34 +0530 Subject: [PATCH 175/327] ARM: dts: msm: Add support for sharp qhd video mode on shima This change adds support for sharp qhd video mode dual dsi panel on shima platform. Change-Id: I291fbf6d860c754f01bdcde29f51d0ef6c26644f --- .../dsi-panel-sharp-dsc-qhd-plus-video.dtsi | 193 ++++++++++++++++++ display/shima-sde-display-common.dtsi | 13 ++ display/shima-sde-display-idp.dtsi | 13 ++ 3 files changed, 219 insertions(+) create mode 100644 display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi new file mode 100644 index 000000000000..d61e11b05c2f --- /dev/null +++ b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi @@ -0,0 +1,193 @@ +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_video: qcom,mdss_dsi_sharp_qhd_plus_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp qhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/shima-sde-display-common.dtsi b/display/shima-sde-display-common.dtsi index 7006dffcdd0b..70fcc069c51d 100644 --- a/display/shima-sde-display-common.dtsi +++ b/display/shima-sde-display-common.dtsi @@ -3,6 +3,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" @@ -140,6 +141,18 @@ }; }; +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_video_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi index 54c0f4fa4349..1cbc9bc43f7e 100644 --- a/display/shima-sde-display-idp.dtsi +++ b/display/shima-sde-display-idp.dtsi @@ -68,6 +68,19 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 24 0>; }; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 24 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; +}; + &dsi_sharp_qhd_plus_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; From 6026ae9e14a2d23daa520edca905615b56901291 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 22 Oct 2020 16:35:14 +0530 Subject: [PATCH 176/327] ARM: dts: msm: Enable ESD for sharp qhd video mode on shima This change enables ESD for sharp qhd video mode dual dsi panel on shima target. Change-Id: Ibf4a83abdc0c247043d880ac67925905f055042b --- display/shima-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index c4ad6d8c83fc..d7f3efc6ec23 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -125,6 +125,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_sharp_qhd_plus_dsc_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_video_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From 4471e02a5795e19458dd5d9537c7226cb8b5215e Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 26 Oct 2020 00:39:41 -0700 Subject: [PATCH 177/327] ARM: dts: msm: add backlight properties for trusted vm displays Add backlight properties for displays supported in trusted vm environment. Change-Id: I593a9a94a4cd309638eda5b03793d0f5699c1036 --- display/trustedvm-lahaina-sde-display.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi index 036205f97d18..14697d22c7ca 100644 --- a/display/trustedvm-lahaina-sde-display.dtsi +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -31,3 +31,18 @@ &mdss_mdp { connectors = <&sde_dsi>; }; + +&dsi_sw43404_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; +}; + +&dsi_sw43404_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; +}; + From e42dcfcf5c04e05bc48b4fc4d680391fd74d473c Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Wed, 11 Nov 2020 11:18:54 +0800 Subject: [PATCH 178/327] ARM: dts: msm: enable LP mode DCS brightness setting for r66451 video panel Used LP mode for DCS brightness and power off commands. Change-Id: Id704c2adf0939717368a7de8108a9cecc530af7a --- display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 2 +- display/lahaina-sde-display-qrd.dtsi | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 995e4df38122..68925fcc9311 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -90,7 +90,7 @@ 05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 6792ded59c5e..6613c46cd877 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -13,6 +13,7 @@ &dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; From 5bd237eea1a68aea20724231f6be801012e1d8ea Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Wed, 4 Nov 2020 16:56:52 +0530 Subject: [PATCH 179/327] ARM: dts: msm: Add mdp_intf base address in dt This change adds mdp_intf_base address entry for dsi0 and dsi1 on shima, holi and lahaina targets. Change-Id: I56c118884690237e0559e928c4828fe575adf98c --- display/holi-sde-common.dtsi | 5 +++-- display/lahaina-sde-common.dtsi | 10 ++++++---- display/shima-sde-common.dtsi | 10 ++++++---- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index ca2ba7d915f7..3e49e2ac9420 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -173,8 +173,9 @@ cell-index = <0>; frame-threshold-time-us = <1000>; reg = <0x05e94000 0x400>, - <0x05f08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0x05f08000 0x4>, + <0x05e6b800 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 9c009d960baf..66182dd3bc09 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -283,8 +283,9 @@ cell-index = <0>; frame-threshold-time-us = <800>; reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; @@ -322,8 +323,9 @@ cell-index = <1>; frame-threshold-time-us = <800>; reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; diff --git a/display/shima-sde-common.dtsi b/display/shima-sde-common.dtsi index 8ed5332e3db4..8e003df778e8 100644 --- a/display/shima-sde-common.dtsi +++ b/display/shima-sde-common.dtsi @@ -241,8 +241,9 @@ cell-index = <0>; frame-threshold-time-us = <800>; reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae6b800 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; @@ -281,8 +282,9 @@ cell-index = <1>; frame-threshold-time-us = <800>; reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; + <0xaf08000 0x4>, + <0x0ae6c000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; From 8dea5d01c4afc215c3d40e2bc2187b5c3b5b47cd Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 11 Nov 2020 09:49:11 -0800 Subject: [PATCH 180/327] ARM: dts: msm: add backlight properties for visionox panel in TVM Add properties related to backlight for visionox panel in trusted-VM for lahaina target. Change-Id: I1e797ae25b797f29172efe9c22872aaf11194073 --- display/trustedvm-lahaina-sde-display.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi index 14697d22c7ca..f603189ccf1e 100644 --- a/display/trustedvm-lahaina-sde-display.dtsi +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -46,3 +46,19 @@ qcom,mdss-brightness-max-level = <255>; }; +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; + From 73aab44811ea268f61d3241eb57d13dc086c1b32 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Thu, 12 Nov 2020 11:38:15 +0530 Subject: [PATCH 181/327] bindings: disp: qcom: Update reg and reg-names binding documentation This change updates documentation for reg and reg-names which are used to specify the address & length and names respectively of the memory mapped regions. Change-Id: Id7f1c8f5cd13bdf8791fbcafc7e1b93a0664a914 --- bindings/sde-dsi.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt index 8e720f75f1ee..b05a411e2522 100644 --- a/bindings/sde-dsi.txt +++ b/bindings/sde-dsi.txt @@ -15,11 +15,12 @@ Required properties: qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 -- reg: Base address and length of DSI controller's memory - mapped regions. +- reg: List of base address and length of memory mapped + regions of DSI controller, disp_cc and mdp_intf. - reg-names: A list of strings that name the list of regs. "dsi_ctrl" - DSI controller memory region. - "mmss_misc" - MMSS misc memory region. + "disp_cc_base" - Base address of disp_cc memory region. + "mdp_intf_base" - Base address of mdp_intf memory region. - cell-index: Specifies the controller instance. - clocks: Clocks required for DSI controller operation. - clock-names: Names of the clocks corresponding to handles. Following From 420034d547b11599f9d4da79a98a095a3d58941c Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Fri, 13 Nov 2020 10:41:19 -0800 Subject: [PATCH 182/327] ARM: dts: msm: add name property for all display specific GPIOs Add a GPIO name property to capture all the GPIOs specific to display host and panel. The entries correspond to the GPIO pins in the property dsi-panel-gpio-pins. Change-Id: If820a47fcdf72e5ef6e907a92c947ea4d4480690 --- bindings/mdss-dsi-panel.txt | 3 +++ display/lahaina-sde-display-common.dtsi | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 086fb76f0c73..de435b32c172 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -604,6 +604,8 @@ Optional properties: - qcom,dsi-panel-gpio-pins: An u32 array consisting of all the GPIO pins used for driving the DSI host and the panels connected to the host. +- qcom,dsi-panel-gpio-names: A string array consisting of names of all the + GPIO pins used for driving the DSI host and panels. - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active region for video mode panels and line number after TE for command mode @@ -790,6 +792,7 @@ Example: qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; qcom,mdss-dsi-display-timings { wqhd { diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index c23cc4f3a018..4aa28560d687 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -127,6 +127,7 @@ qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; qcom,mdss-dsi-display-timings { timing@0 { @@ -149,6 +150,10 @@ qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 @@ -166,6 +171,11 @@ qcom,mdss-dsi-min-refresh-rate = <60>; qcom,mdss-dsi-max-refresh-rate = <120>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 16 07 @@ -179,6 +189,11 @@ &dsi_r66451_amoled_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; + qcom,dsi-panel-gpio-pins = <12 24 82>; + qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 From f0a7843b3380ebe1fb9f6b0704f7f37e4081b044 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 11 Nov 2020 16:16:22 -0800 Subject: [PATCH 183/327] ARM: dts: msm: enable ESD status check for all panels in lahaina TVM Move the ESD entries from lahaina specific device-tree to common device-tree to enable the feature in both VMs for lahaina target. Change-Id: I8fa9f14eb36f79078be16d380db6a213bf822639 --- display/lahaina-sde-display-common.dtsi | 99 +++++++++++++++++++++++++ display/lahaina-sde-display.dtsi | 92 +---------------------- 2 files changed, 100 insertions(+), 91 deletions(-) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 4aa28560d687..b4a2b6f5467c 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -125,6 +125,13 @@ qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24 82>; qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; @@ -150,6 +157,13 @@ qcom,dsi-dyn-clk-list = <534712320 532484352 530256384>; qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,dsi-panel-gpio-address = <0x0F100000 0x1000>; qcom,dsi-panel-gpio-pins = <12 24>; qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio"; @@ -194,6 +208,13 @@ qcom,dsi-panel-gpio-pins = <12 24 82>; qcom,dsi-panel-gpio-names = "reg-gpio", "reset-gpio", "platform-te-gpio"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 @@ -247,6 +268,14 @@ &dsi_r66451_amoled_144hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09 @@ -259,6 +288,15 @@ &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 @@ -272,6 +310,15 @@ &dsi_sharp_4k_dsc_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06 @@ -284,6 +331,15 @@ &dsi_sharp_1080_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 @@ -297,6 +353,14 @@ &dsi_sharp_qsync_wqhd_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 10 1c 03 @@ -358,6 +422,14 @@ &dsi_sharp_qsync_wqhd_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 @@ -389,6 +461,15 @@ &dsi_dual_nt35597_truly_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { /* DPHY regular margins */ @@ -408,6 +489,15 @@ qcom,mdss-dsi-max-refresh-rate = <60>; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 @@ -422,6 +512,15 @@ &dsi_nt35695b_truly_fhd_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { /* DPHY regular margins */ diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 3e3a389510da..f1949c65f7c4 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -112,13 +112,6 @@ &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; - qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; @@ -127,74 +120,24 @@ }; }; -&dsi_sw43404_amoled_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - &dsi_r66451_amoled_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x1c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; + &dsi_r66451_amoled_144hz_cmd { qcom,ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x1c>; - qcom,mdss-dsi-panel-status-read-length = <1>; }; &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x77>; - qcom,mdss-dsi-panel-on-check-value = <0x77>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - -&dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x77>; - qcom,mdss-dsi-panel-on-check-value = <0x77>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_sharp_1080_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_sharp_qsync_wqhd_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; qcom,mdss-dsi-display-timings { timing@0 { /* WQHD 60FPS CMD */ qcom,partial-update-enabled = "single_roi"; @@ -223,45 +166,12 @@ }; }; -&dsi_sharp_qsync_wqhd_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - &dsi_dual_nt35597_truly_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_nt35695b_truly_fhd_cmd { qcom,ulps-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; }; &dsi_sim_cmd { From 9ec8ceb91d722127ad14a544df0aa6a74cbf76c4 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Thu, 29 Oct 2020 12:01:46 -0400 Subject: [PATCH 184/327] ARM: dts: msm: add support for secondary display in TVM Add missing DSI clock nodes and dsi connector for secondary display in TVM. Change-Id: I34dab33fc478bcefff67f282cac35694013202ad --- display/trustedvm-lahaina-sde-display.dtsi | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi index 036205f97d18..f3799d5bb242 100644 --- a/display/trustedvm-lahaina-sde-display.dtsi +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -28,6 +28,23 @@ qcom,panel-te-source = <0>; }; -&mdss_mdp { - connectors = <&sde_dsi>; +&sde_dsi1 { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_MUX_1_CLK>, + <&clock_cpucc PCLK_MUX_1_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; + qcom,panel-te-source = <1>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; }; From 9595d70fba17bbe47ebd0a1390777c8f68729825 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Thu, 19 Nov 2020 11:41:59 -0500 Subject: [PATCH 185/327] bindings: Documentation: add DSC continuous PPS command support for DP Add support for DSC continuous PPS command for DP which allows sending PPS during every frame in hardware as per the requirement of some bridge chips. Change-Id: I6c81c08ca386ef7cf636fed0b1328c4e0c029ea3 --- bindings/sde-dp.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index 567cbd7dd81b..5f0c5fc4fba9 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -76,6 +76,8 @@ DP Controller: Required properties: - usb-controller: Phandle for the USB controller. - qcom,pll-revision: PLL hardware revision. - usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events. +- qcom,dsc-continuous-pps: Control node for sending PPS every frame in hardware for DSC over DP. + This is needed by certain bridge chips where there is such a requirement to do so. - qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. - qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. - qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. @@ -197,7 +199,7 @@ sde_dp: qcom,dp_display@0 { qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; - + qcom,dsc-continuous-pps; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; vdd_mx-supply = <&VDD_MXA_LEVEL>; From 930d2e9707a26ef2b281e94f455033321d7e931f Mon Sep 17 00:00:00 2001 From: Sudarsan Ramesh Date: Thu, 19 Nov 2020 12:03:05 -0500 Subject: [PATCH 186/327] ARM: dts: msm: Enable continuous PPS for DP DSC This change enables continuous PPS for DP DSC so that a PPS is sent via hardware for every frame. This is needed by certain bridge chips where there is a requirement to do so. Change-Id: Id0aa7238816ae888dffdf145f40e3cd03a387f14 --- display/lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 41286ac19ff8..08aac3611c8d 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -85,6 +85,7 @@ qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; + qcom,dsc-continuous-pps; vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; From b3c702d779f3c3efbc1bb54ff10669f61d307211 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Thu, 12 Nov 2020 15:14:05 -0800 Subject: [PATCH 187/327] ARM: dts: msm: enable dynamic clocks for CPHY panels on Lahaina Change enables Dynamic clocks for Visionox CPHY command and video mode panels on lahaina target. Change-Id: I330a8705c6383870ddc1bdf6e893d8c623427f81 --- display/lahaina-sde-display-common.dtsi | 8 +++++++- display/lahaina-sde-display.dtsi | 10 ++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index b4a2b6f5467c..b089d09f0801 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -242,6 +242,8 @@ &dsi_r66451_amoled_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <195173804 194360579 193547355>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 @@ -254,7 +256,11 @@ &dsi_r66451_amoled_video_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <394178400 392535990 387608760>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index f1949c65f7c4..685fd53fd828 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -48,6 +48,8 @@ <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, @@ -55,15 +57,19 @@ <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; + "shadow_byte_clk1", "shadow_pixel_clk1", + "shadow_cphybyte_clk1", "shadow_cphypixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; From 00110c49c641f9c85b6dd3f910e4de2962fb203c Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Wed, 25 Nov 2020 00:16:09 +0530 Subject: [PATCH 188/327] ARM: dts: msm: add backlight properties for visionox panel in TVM Add properties related to backlight for visionox panel in trusted-VM for shima target. Change-Id: I97913526ba38eb74ba4d6ea44ddbcee67a63ff91 --- display/trustedvm-shima-sde-display.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/display/trustedvm-shima-sde-display.dtsi b/display/trustedvm-shima-sde-display.dtsi index dc497bf18f44..c4df4865ec0f 100644 --- a/display/trustedvm-shima-sde-display.dtsi +++ b/display/trustedvm-shima-sde-display.dtsi @@ -33,3 +33,19 @@ &mdss_mdp { connectors = <&sde_dsi>; }; + +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; +}; From c594f29d70ff2b49fc9922be7f235033084c91b6 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Sun, 6 Dec 2020 08:46:08 +0530 Subject: [PATCH 189/327] ARM: dts: msm: add wake up on touch support Early wake up by perf hal ioctl is not enabled for holi target. Made changes to enable early wake up by legacy input touch handle method. Change-Id: Ib1efc689ba21a587bf4e32e34a2e55552ab138b9 --- display/holi-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index c6d3d332a98a..6b9b4af31c3f 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -109,6 +109,7 @@ interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; qcom,platform-supply-entries { #address-cells = <1>; From 363838ff2269e672f68f1e72c5cbae623045d90d Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Mon, 23 Nov 2020 17:33:06 +0800 Subject: [PATCH 190/327] ARM: dts: msm: add 60Hz panel node for holi Add 60Hz cmd mode and video mode support for qrd and cdp holi. Change-Id: I78b188ba95d324bad95da359aa2e7844ebe751d6 --- display/holi-sde-display-cdp.dtsi | 20 ++++++++++++++++++++ display/holi-sde-display-qrd.dtsi | 10 ++++++++++ display/holi-sde-display.dtsi | 20 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 4da9c2161107..bf75e6b46050 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -71,6 +71,26 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index 39f497d72ae7..f7f1aae2c61d 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -57,6 +57,16 @@ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + &dsi_sim_vid { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index c019341c0970..248d6f4e80f6 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -105,3 +105,23 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_60hz_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + From 45f00f6822f56dbcf3df30e388ef061f12f0426b Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Tue, 15 Dec 2020 18:18:03 +0800 Subject: [PATCH 191/327] ARM: dts: msm: increase vddio voltage for qrd lahaina panel Since some panels have larger vddio voltage drop, that will lead panel dead. So increase the voltage from 1.8v to 1.86v. Change-Id: I6e6d3cd95c550e976a170d99b7f3d3d311c8bb3e --- display/lahaina-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index 6613c46cd877..a82336ce618e 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ #include "lahaina-sde-display.dtsi" +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; + &dsi_r66451_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From f05b085b5f6e57efa2debaff023c127972999837 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Wed, 9 Dec 2020 18:16:33 +0530 Subject: [PATCH 192/327] ARM: dts: msm: Add NT36672E Video mode panel support on holi Add NT36672E 60, 120 and 144 fps fhd plus Video mode panel support on holi platform. Change-Id: I7a25b37ebce9fa9c7877dbd6cdfde2929b394663 --- ...dsi-panel-nt36672e-fhd-plus-120-video.dtsi | 334 ++++++++++++++++ ...dsi-panel-nt36672e-fhd-plus-144-video.dtsi | 376 ++++++++++++++++++ ...si-panel-nt36672e-fhd-plus-60hz-video.dtsi | 313 +++++++++++++++ display/holi-sde-display-cdp.dtsi | 24 ++ display/holi-sde-display-common.dtsi | 46 +++ 5 files changed, 1093 insertions(+) create mode 100644 display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi create mode 100644 display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi create mode 100644 display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi diff --git a/display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi new file mode 100644 index 000000000000..ddbf609aefa9 --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-120-video.dtsi @@ -0,0 +1,334 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_120_video: qcom,mdss_dsi_nt36672e_fhd_plus_120_video { + qcom,mdss-dsi-panel-name = + "nt36672e fhd plus 120Hz Video panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 B0 00 + 15 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 + 0D B7 0C B7 + 39 01 00 00 00 00 03 C2 1B A0 + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 01 66 + 15 01 00 00 00 00 02 06 40 + 15 01 00 00 00 00 02 07 38 + 15 01 00 00 00 00 02 2F 83 + 15 01 00 00 00 00 02 69 91 + 15 01 00 00 00 00 02 95 D1 + 15 01 00 00 00 00 02 96 D1 + 15 01 00 00 00 00 02 F2 64 + 15 01 00 00 00 00 02 F4 64 + 15 01 00 00 00 00 02 F6 64 + 15 01 00 00 00 00 02 F8 64 + + 15 01 00 00 00 00 02 89 1C + 15 01 00 00 00 00 02 8A 1C + 15 01 00 00 00 00 02 8B 1C + 15 01 00 00 00 00 02 8C 1C + + 15 01 00 00 00 00 02 FF 24 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 01 0F + 15 01 00 00 00 00 02 03 0C + 15 01 00 00 00 00 02 05 1D + + 15 01 00 00 00 00 02 08 2F + 15 01 00 00 00 00 02 09 2E + 15 01 00 00 00 00 02 0A 2D + 15 01 00 00 00 00 02 0B 2C + + 15 01 00 00 00 00 02 11 17 + 15 01 00 00 00 00 02 12 13 + 15 01 00 00 00 00 02 13 15 + 15 01 00 00 00 00 02 15 14 + 15 01 00 00 00 00 02 16 16 + 15 01 00 00 00 00 02 17 18 + 15 01 00 00 00 00 02 1B 01 + 15 01 00 00 00 00 02 1D 1D + + 15 01 00 00 00 00 02 20 2F + 15 01 00 00 00 00 02 21 2E + 15 01 00 00 00 00 02 22 2D + 15 01 00 00 00 00 02 23 2C + + 15 01 00 00 00 00 02 29 17 + 15 01 00 00 00 00 02 2A 13 + 15 01 00 00 00 00 02 2B 15 + 15 01 00 00 00 00 02 2F 14 + 15 01 00 00 00 00 02 30 16 + 15 01 00 00 00 00 02 31 18 + 15 01 00 00 00 00 02 32 04 + 15 01 00 00 00 00 02 34 10 + 15 01 00 00 00 00 02 35 1F + 15 01 00 00 00 00 02 36 1F + 15 01 00 00 00 00 02 4D 14 + 15 01 00 00 00 00 02 4E 36 + 15 01 00 00 00 00 02 4F 36 + 15 01 00 00 00 00 02 53 36 + 15 01 00 00 00 00 02 71 30 + 15 01 00 00 00 00 02 79 11 + 15 01 00 00 00 00 02 7A 82 + 15 01 00 00 00 00 02 7B 8F + 15 01 00 00 00 00 02 7D 04 + 15 01 00 00 00 00 02 80 04 + 15 01 00 00 00 00 02 81 04 + 15 01 00 00 00 00 02 82 13 + 15 01 00 00 00 00 02 84 31 + 15 01 00 00 00 00 02 85 00 + 15 01 00 00 00 00 02 86 00 + 15 01 00 00 00 00 02 87 00 + + 15 01 00 00 00 00 02 90 13 + 15 01 00 00 00 00 02 92 31 + 15 01 00 00 00 00 02 93 00 + 15 01 00 00 00 00 02 94 00 + 15 01 00 00 00 00 02 95 00 + 15 01 00 00 00 00 02 9C F4 + 15 01 00 00 00 00 02 9D 01 + 15 01 00 00 00 00 02 A0 0F + 15 01 00 00 00 00 02 A2 0F + 15 01 00 00 00 00 02 A3 02 + 15 01 00 00 00 00 02 A4 04 + 15 01 00 00 00 00 02 A5 04 + 15 01 00 00 00 00 02 C4 40 + 15 01 00 00 00 00 02 C6 C0 + 15 01 00 00 00 00 02 C9 00 + 15 01 00 00 00 00 02 D9 80 + 15 01 00 00 00 00 02 E9 02 + + 15 01 00 00 00 00 02 FF 25 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 19 E4 + 15 01 00 00 00 00 02 21 40 + 15 01 00 00 00 00 02 66 D8 + 15 01 00 00 00 00 02 68 50 + 15 01 00 00 00 00 02 69 10 + 15 01 00 00 00 00 02 6B 00 + 15 01 00 00 00 00 02 6D 0D + 15 01 00 00 00 00 02 6E 48 + + 15 01 00 00 00 00 02 72 41 + 15 01 00 00 00 00 02 73 4A + 15 01 00 00 00 00 02 74 D0 + 15 01 00 00 00 00 02 77 62 + 15 01 00 00 00 00 02 79 81 + 15 01 00 00 00 00 02 7D 03 + 15 01 00 00 00 00 02 7E 15 + 15 01 00 00 00 00 02 7F 00 + 15 01 00 00 00 00 02 84 4D + 15 01 00 00 00 00 02 CF 80 + 15 01 00 00 00 00 02 D6 80 + 15 01 00 00 00 00 02 D7 80 + 15 01 00 00 00 00 02 EF 20 + 15 01 00 00 00 00 02 F0 84 + + 15 01 00 00 00 00 02 FF 26 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 80 05 + 15 01 00 00 00 00 02 81 0F + 15 01 00 00 00 00 02 83 01 + 15 01 00 00 00 00 02 84 03 + 15 01 00 00 00 00 02 85 01 + 15 01 00 00 00 00 02 86 03 + 15 01 00 00 00 00 02 87 01 + 15 01 00 00 00 00 02 88 05 + 15 01 00 00 00 00 02 8A 1A + 15 01 00 00 00 00 02 8B 11 + 15 01 00 00 00 00 02 8C 24 + 15 01 00 00 00 00 02 8E 42 + 15 01 00 00 00 00 02 8F 11 + 15 01 00 00 00 00 02 90 11 + 15 01 00 00 00 00 02 91 11 + 15 01 00 00 00 00 02 9A 80 + 15 01 00 00 00 00 02 9B 04 + 15 01 00 00 00 00 02 9C 00 + 15 01 00 00 00 00 02 9D 00 + 15 01 00 00 00 00 02 9E 00 + + 15 01 00 00 00 00 02 FF 27 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 01 68 + 15 01 00 00 00 00 02 20 81 + 15 01 00 00 00 00 02 21 6A + 15 01 00 00 00 00 02 25 81 + 15 01 00 00 00 00 02 26 94 + 15 01 00 00 00 00 02 6E 00 + 15 01 00 00 00 00 02 6F 00 + 15 01 00 00 00 00 02 70 00 + 15 01 00 00 00 00 02 71 00 + 15 01 00 00 00 00 02 72 00 + 15 01 00 00 00 00 02 75 00 + 15 01 00 00 00 00 02 76 00 + 15 01 00 00 00 00 02 77 00 + 15 01 00 00 00 00 02 7D 09 + 15 01 00 00 00 00 02 7E 67 + 15 01 00 00 00 00 02 80 23 + 15 01 00 00 00 00 02 82 09 + 15 01 00 00 00 00 02 83 67 + 15 01 00 00 00 00 02 88 01 + 15 01 00 00 00 00 02 89 10 + 15 01 00 00 00 00 02 A5 10 + 15 01 00 00 00 00 02 A6 23 + 15 01 00 00 00 00 02 A7 01 + 15 01 00 00 00 00 02 B6 40 + + 15 01 00 00 00 00 02 FF 2A + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 00 91 + 15 01 00 00 00 00 02 03 20 + 15 01 00 00 00 00 02 07 50 + 15 01 00 00 00 00 02 0A 70 + 15 01 00 00 00 00 02 0C 04 + 15 01 00 00 00 00 02 0D 40 + 15 01 00 00 00 00 02 0F 01 + 15 01 00 00 00 00 02 11 E0 + 15 01 00 00 00 00 02 15 0F + 15 01 00 00 00 00 02 16 A4 + 15 01 00 00 00 00 02 19 0F + 15 01 00 00 00 00 02 1A 78 + 15 01 00 00 00 00 02 1B 23 + 15 01 00 00 00 00 02 1D 36 + 15 01 00 00 00 00 02 1E 3E + 15 01 00 00 00 00 02 1F 3E + 15 01 00 00 00 00 02 20 3E + 15 01 00 00 00 00 02 28 FD + 15 01 00 00 00 00 02 29 12 + 15 01 00 00 00 00 02 2A E1 + 15 01 00 00 00 00 02 2D 0A + 15 01 00 00 00 00 02 30 49 + 15 01 00 00 00 00 02 33 96 + 15 01 00 00 00 00 02 34 FF + 15 01 00 00 00 00 02 35 40 + 15 01 00 00 00 00 02 36 DE + 15 01 00 00 00 00 02 37 F9 + 15 01 00 00 00 00 02 38 45 + 15 01 00 00 00 00 02 39 D9 + 15 01 00 00 00 00 02 3A 49 + 15 01 00 00 00 00 02 4A F0 + + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96 + 00 AB 00 BD + 39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7 + 02 22 02 24 + 39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48 + 03 56 03 65 + 39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7 + 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C + 00 B2 00 C3 + 39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC + 02 27 02 29 + 39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C + 03 5A 03 69 + 39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7 + 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C + 00 B1 00 C2 + 39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8 + 02 23 02 25 + 39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C + 03 5B 03 6B + 39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7 + 00 00 + + 15 01 00 00 00 00 02 FF 21 + 15 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96 + 00 AB 00 BD + 39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7 + 02 22 02 24 + 39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48 + 03 56 03 65 + 39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7 + 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C + 00 B2 00 C3 + 39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC + 02 27 02 29 + 39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C + 03 5A 03 69 + 39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7 + 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C + 00 B1 00 C2 + 39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8 + 02 23 02 25 + 39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C + 03 5B 03 6B + 39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7 + 00 00 + + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 FF F0 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 FF 10 + + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 FB 01 + + 15 01 00 00 00 00 02 51 FF //CABC + 15 01 00 00 00 00 02 53 2C + 15 01 00 00 00 00 02 55 01 + + 05 01 00 00 C8 00 01 11 + 05 01 00 00 96 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi new file mode 100644 index 000000000000..eb5466ffe0d4 --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-144-video.dtsi @@ -0,0 +1,376 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_144_video: qcom,mdss_dsi_nt36672e_fhd_plus_144_video { + qcom,mdss-dsi-panel-name = + "nt36672e fhd plus 144Hz video panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 FF 10 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 29 01 00 00 00 00 03 C2 1B A0 + 29 01 00 00 00 00 02 E9 01 + + 29 01 00 00 00 00 02 FF 20 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 01 66 + 29 01 00 00 00 00 02 06 40 + 29 01 00 00 00 00 02 07 38 + 29 01 00 00 00 00 02 1B 01 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F0 + + 29 01 00 00 00 00 02 FF 20 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 29 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 29 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 29 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 29 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 29 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 29 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 29 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 29 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 29 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + 29 01 00 00 00 00 02 FF 21 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 29 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 29 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 29 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 29 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 29 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 29 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 29 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 29 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 29 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 29 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + + 29 01 00 00 00 00 02 FF C0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 9C 11 + 29 01 00 00 00 00 02 9D 11 + + 29 01 00 00 00 00 02 FF F0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 5A 00 + 29 01 00 00 00 00 02 9F 0C + + 29 01 00 00 00 00 02 FF D0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 53 22 + 29 01 00 00 00 00 02 54 02 + + 29 01 00 00 00 00 02 FF E0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 35 82 + + 29 01 00 00 00 00 02 FF 10 + 29 01 00 00 00 00 02 FB 01 + + 15 01 00 00 00 00 02 35 01 //TE + + 05 01 00 00 C8 00 01 11 + 05 01 00 00 96 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi new file mode 100644 index 000000000000..c9f454a0c27e --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi @@ -0,0 +1,313 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_60_video: qcom,mdss_dsi_nt36672e_fhd_plus_60_video { + qcom,mdss-dsi-panel-name = + "nt36672e 60 Hz fhd plus video mode panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750 + 39800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <56>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 C0 00 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 14 01 00 01 11 00 01 C1 + 39 01 00 00 00 00 03 C2 1B A0 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+ 39 01 00 00 00 00 02 75 00 + 39 01 00 00 00 00 02 76 00 + 39 01 00 00 00 00 02 77 00 + 39 01 00 00 00 00 02 7D 09 + 39 01 00 00 00 00 02 7E 67 + 39 01 00 00 00 00 02 80 23 + 39 01 00 00 00 00 02 82 09 + 39 01 00 00 00 00 02 83 67 + 39 01 00 00 00 00 02 88 01 + 39 01 00 00 00 00 02 89 10 + 39 01 00 00 00 00 02 A5 10 + 39 01 00 00 00 00 02 A6 23 + 39 01 00 00 00 00 02 A7 01 + 39 01 00 00 00 00 02 B6 40 + 39 01 00 00 00 00 02 E5 02 + 39 01 00 00 00 00 02 E6 D3 + 39 01 00 00 00 00 02 EB 03 + 39 01 00 00 00 00 02 EC 28 + 39 01 00 00 00 00 02 FF 2A + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 00 91 + 39 01 00 00 00 00 02 03 20 + 39 01 00 00 00 00 02 07 50 + 39 01 00 00 00 00 02 0A 70 + 39 01 00 00 00 00 02 0C 04 + 39 01 00 00 00 00 02 0D 40 + 39 01 00 00 00 00 02 0F 01 + 39 01 00 00 00 00 02 11 E0 + 39 01 00 00 00 00 02 15 0F + 39 01 00 00 00 00 02 16 A4 + 39 01 00 00 00 00 02 19 0F + 39 01 00 00 00 00 02 1A 78 + 39 01 00 00 00 00 02 1B 23 + 39 01 00 00 00 00 02 1D 36 + 39 01 00 00 00 00 02 1E 3E + 39 01 00 00 00 00 02 1F 3E + 39 01 00 00 00 00 02 20 3E + 39 01 00 00 00 00 02 28 FD + 39 01 00 00 00 00 02 29 12 + 39 01 00 00 00 00 02 2A E1 + 39 01 00 00 00 00 02 2D 0A + 39 01 00 00 00 00 02 30 49 + 39 01 00 00 00 00 02 33 96 + 39 01 00 00 00 00 02 34 FF + 39 01 00 00 00 00 02 35 40 + 39 01 00 00 00 00 02 36 DE + 39 01 00 00 00 00 02 37 F9 + 39 01 00 00 00 00 02 38 45 + 39 01 00 00 00 00 02 39 D9 + 39 01 00 00 00 00 02 3A 49 + 39 01 00 00 00 00 02 4A F0 + 39 01 00 00 00 00 02 7A 09 + 39 01 00 00 00 00 02 7B 40 + 39 01 00 00 00 00 02 7F F0 + 39 01 00 00 00 00 02 83 0F + 39 01 00 00 00 00 02 84 A4 + 39 01 00 00 00 00 02 87 0F + 39 01 00 00 00 00 02 88 78 + 39 01 00 00 00 00 02 89 23 + 39 01 00 00 00 00 02 8B 36 + 39 01 00 00 00 00 02 8C 7D + 39 01 00 00 00 00 02 8D 7D + 39 01 00 00 00 00 02 8E 7D + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 17 00 49 00 6A 00 89 00 9F 00 B6 00 C8 + 39 01 00 00 00 00 11 B1 00 D9 01 10 01 3A 01 7A 01 A9 01 F2 02 2D 02 2E + 39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1 + 39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36 + 39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B + 39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1 + 39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31 + 39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 02 FF 21 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 17 00 49 00 6A 00 89 00 9F 00 B6 00 C8 + 39 01 00 00 00 00 11 B1 00 D9 01 10 01 3A 01 7A 01 A9 01 F2 02 2D 02 2E + 39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1 + 39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36 + 39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B + 39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1 + 39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31 + 39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A + 39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00 + 39 01 00 00 00 00 02 FF 2C + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 61 1F + 39 01 00 00 00 00 02 62 1F + 39 01 00 00 00 00 02 7E 03 + 39 01 00 00 00 00 02 6A 14 + 39 01 00 00 00 00 02 6B 36 + 39 01 00 00 00 00 02 6C 36 + 39 01 00 00 00 00 02 6D 36 + 39 01 00 00 00 00 02 53 04 + 39 01 00 00 00 00 02 54 04 + 39 01 00 00 00 00 02 55 04 + 39 01 00 00 00 00 02 56 0F + 39 01 00 00 00 00 02 58 0F + 39 01 00 00 00 00 02 59 0F + 39 01 00 00 00 00 02 FF F0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 51 FF + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 55 01 + 05 01 00 00 78 00 01 11 + 05 01 00 00 64 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + }; + }; + }; +}; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index bf75e6b46050..405d99cc5725 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -94,3 +94,27 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 8796a6e5c02f..b4d0bf1d8d88 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -10,6 +10,9 @@ #include "dsi-panel-sharp-qsync-fhd-video.dtsi" #include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" #include "dsi-panel-sharp-qsync-fhd-60hz-cmd.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include &soc { @@ -713,3 +716,46 @@ }; }; }; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x32>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 + 08 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 08 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + + }; + }; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0F>; + qcom,mdss-dsi-t-clk-pre = <0x39>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 + 0a 09 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; From caf944c54712b068f384687ef9ee999b5bea54a8 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Tue, 22 Dec 2020 17:29:45 +0800 Subject: [PATCH 193/327] ARM: dts: msm: increase vddio voltage for qrd shima panel Since some panels have larger vddio voltage drop, that will lead panel dead. So increase the voltage from 1.82v to 1.86v. Change-Id: I129cdbb11e8b7687111f0c9d34c873a40ad15f54 --- display/shima-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/shima-sde-display-qrd.dtsi b/display/shima-sde-display-qrd.dtsi index 72107b66065a..bbd34e09bda6 100644 --- a/display/shima-sde-display-qrd.dtsi +++ b/display/shima-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ #include "shima-sde-display.dtsi" +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; + &dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From a6c095841c2712cb088e5fc470f86e38f78fdf63 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 28 Dec 2020 17:49:43 +0530 Subject: [PATCH 194/327] ARM: dts: msm: add display dt node for yupik target Add display related dt nodes for yupik target. Change-Id: I6c703e83fb174c65157fb3b6604e900857abba5c --- display/yupik-sde-common.dtsi | 325 ++++++++++++++++++++++++++ display/yupik-sde-display-common.dtsi | 119 ++++++++++ display/yupik-sde-display-idp.dtsi | 22 ++ display/yupik-sde-display.dtsi | 42 ++++ display/yupik-sde.dtsi | 107 +++++++++ 5 files changed, 615 insertions(+) create mode 100644 display/yupik-sde-common.dtsi create mode 100644 display/yupik-sde-display-common.dtsi create mode 100644 display/yupik-sde-display-idp.dtsi create mode 100644 display/yupik-sde-display.dtsi create mode 100644 display/yupik-sde.dtsi diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi new file mode 100644 index 000000000000..a91404665c0a --- /dev/null +++ b/display/yupik-sde-common.dtsi @@ -0,0 +1,325 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clock-rate = <0 0 0 0 506666667 19200000 506666667 19200000>; + clock-max-rate = <0 0 0 0 608000000 19200000 608000000 + 608000000>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000 0x1b000>; + qcom,sde-ctl-size = <0x1e8>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x47000 0x48000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", + "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", + "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-intf-off = <0x35000 0x36000 + 0x3a000>; + qcom,sde-intf-size = <0x2c4>; + qcom,sde-intf-type = "dp", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0>; + + qcom,sde-pp-off = <0x6a000 + 0x6c000 0x6d000>; + qcom,sde-pp-slave = <0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000>; + qcom,sde-dsc-size = <0x10>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00>; + qcom,sde-dsc-ctl-size = <0x10>; + qcom,sde-dsc-native422-supp = <1>; + qcom,sde-dsc-linewidth = <2048>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", + "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 + 0x25000 0x27000 0x29000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 + 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0 3 2>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>; + qcom,sde-sspp-clk-status = + <0x2b0 0>, + <0x2b0 12>, <0x2b8 12>, <0x2c8 12>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2400>; + qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-wb-linewidth-linear = <4096>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; + qcom,sde-ubwc-version = <0x300>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <4700000>; + qcom,sde-max-bw-high-kbps = <8800000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; + + qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000 + 0x00000000 0x0000ffff 0x0000ffff>; + qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x1 0xff00 0xff00>; + + qcom,sde-qos-lut-linear = <0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>; + qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0x0 0x0>; + qcom,sde-qos-lut-cwb = <0x66666666 0x66666540>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x4000901>; + + /* SPMI address related to display */ + qcom,pmic-arb = <&spmi_bus>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 74000>, + <0 148000>, + <0 265000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.5"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { + compatible = "qcom,dsi-phy-v4.1"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf01004 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi new file mode 100644 index 000000000000..a8c8e500697a --- /dev/null +++ b/display/yupik-sde-display-common.dtsi @@ -0,0 +1,119 @@ +#include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1820000>; + qcom,supply-max-voltage = <1820000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb: dsi_panel_pwr_supply_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; + }; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 08 02 04 00 1c 18]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + +&dsi_nt36672e_fhd_plus_60_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 + 0a 09 02 04 00 1f 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi new file mode 100644 index 000000000000..31e06dd7bacc --- /dev/null +++ b/display/yupik-sde-display-idp.dtsi @@ -0,0 +1,22 @@ +#include "yupik-sde-display.dtsi" + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; +}; + diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi new file mode 100644 index 000000000000..e85af3a1b632 --- /dev/null +++ b/display/yupik-sde-display.dtsi @@ -0,0 +1,42 @@ +#include "yupik-sde-display-common.dtsi" + +&soc { + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 80 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L12C>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi>; +}; diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi new file mode 100644 index 000000000000..464d7c34968c --- /dev/null +++ b/display/yupik-sde.dtsi @@ -0,0 +1,107 @@ +#include "yupik-sde-common.dtsi" +#include + +&soc { + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + status = "disabled"; + reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <4>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus"; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x900 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent-hint-cached; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x901 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &cnoc2 SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010001>; + /* offsets are based off dspp 0 */ + qcom,sde-dspp-ltm-off = <0x15300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L6B>; + refgen-supply = <&refgen>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L10C>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + +}; From c952e74f20c3de8517f4a2249f5d6fddb76ed8da Mon Sep 17 00:00:00 2001 From: Mitika Dodiya Date: Wed, 30 Dec 2020 20:06:30 +0530 Subject: [PATCH 195/327] ARM: dts: msm: add display dt node for yupik Add display dt node for yupik. Change-Id: I68f4686e670caaf480ed87b4eeb05e8daa289ae3 --- display/yupik-sde-common.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index a91404665c0a..5ab33d471d1e 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -147,14 +147,6 @@ qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-spr-off = <0x15400 0x14400>; - qcom,sde-dspp-spr-size = <0x200>; - qcom,sde-dspp-spr-version = <0x00010000>; - - qcom,sde-dspp-demura-off = <0x15600 0x14800>; - qcom,sde-dspp-demura-size = <0x200>; - qcom,sde-dspp-demura-version = <0x00010000>; - qcom,sde-uidle-off = <0x80000>; qcom,sde-uidle-size = <0x70>; @@ -187,7 +179,7 @@ qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; - /* offsets are relative to "mdp_phys + qcom,sde-off */ + /* offsets are relative to regdma_phys */ qcom,sde-reg-dma-off = <0 0x400>; qcom,sde-reg-dma-id = <0 1>; qcom,sde-reg-dma-version = <0x00020000>; From 9b58a1a3a91f8e5bd7f24c269e79b8cdbb986845 Mon Sep 17 00:00:00 2001 From: "Zhao, Yuan" Date: Tue, 5 Jan 2021 10:44:14 +0800 Subject: [PATCH 196/327] Revert "ARM: dts: msm: increase VFP value for video mode panel" This reverts commit 82b36f5105464d12e088ea7deac8d4171a488a67. Change-Id: I8fb1eb6b02f9730c2894cfdecf72e2d049361773 --- display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi | 2 +- display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 2 +- display/lahaina-sde-display-common.dtsi | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi index 68925fcc9311..7cfc0bd32bd3 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi @@ -36,7 +36,7 @@ qcom,mdss-dsi-h-pulse-width = <1>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <75>; + qcom,mdss-dsi-v-front-porch = <25>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-panel-framerate = <120>; qcom,mdss-dsi-on-command = [ diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi index d7cd192a4fbd..ecac0d4bfc65 100644 --- a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi +++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi @@ -37,7 +37,7 @@ qcom,mdss-dsi-h-pulse-width = <12>; qcom,mdss-dsi-h-sync-skew = <0>; qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-front-porch = <10>; qcom,mdss-dsi-v-pulse-width = <1>; qcom,mdss-dsi-h-left-border = <0>; qcom,mdss-dsi-panel-framerate = <60>; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 9ad13ecdeba6..7b54b749014e 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -172,7 +172,7 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05 05 06 02 04 00 12 0a]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; @@ -194,8 +194,8 @@ qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 16 07 - 07 08 02 04 00 19 0c]; + qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08 + 08 05 02 04 00 17 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From 7195d57c3f86b3e5ca78d1cd996250ea02de3e9a Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Wed, 6 Jan 2021 01:25:12 +0530 Subject: [PATCH 197/327] ARM: dts: msm: Add dp DT node for yupik target Add dp dt node for yupik target. Change-Id: Iba92179e4a9cfb5e5fe51438f69f85f8bb1e97d1 --- display/yupik-sde.dtsi | 116 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 464d7c34968c..ab62f8bc5bab 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -2,6 +2,122 @@ #include &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp: qcom,dp_display@ae90000 { + status="disabled"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + usb-phy = <&usb_qmp_dp_phy>; + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0fc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x098>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf01068 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xaf01004 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical","gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "pixel_clk_rcg", "pixel_parent","strm0_pixel_clk"; + + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; From 72ce46c2efbe27dfad556ff467843d00d4f2aa0d Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Tue, 12 Jan 2021 13:30:35 +0530 Subject: [PATCH 198/327] ARM: dts: msm: add cwb pingpong and mixer in yupik DT Add pingpong and mixer blocks in yupik dt, which are used only in cwb case. Change-Id: I9e2dd9143b0b45bc5497634ef2ae1a5af3852793 --- display/yupik-sde-common.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index a91404665c0a..5853774a468e 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -29,12 +29,12 @@ qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; - qcom,sde-mixer-off = <0x45000 0x47000 0x48000>; + qcom,sde-mixer-off = <0x45000 0x45000 0x47000 0x48000>; qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", + qcom,sde-mixer-display-pref = "primary", "none", "none", "none"; - qcom,sde-mixer-cwb-pref = "none", + qcom,sde-mixer-cwb-pref = "none", "cwb", "none", "none"; qcom,sde-dspp-top-off = <0x1300>; @@ -60,9 +60,9 @@ qcom,sde-intf-type = "dp", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0 0x36800 0>; - qcom,sde-pp-off = <0x6a000 + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000>; - qcom,sde-pp-slave = <0x0 0x0 0x0>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; qcom,sde-pp-size = <0xd4>; qcom,sde-cdm-off = <0x7a200>; @@ -78,7 +78,7 @@ qcom,sde-dsc-native422-supp = <1>; qcom,sde-dsc-linewidth = <2048>; - qcom,sde-dither-off = <0xe0 0xe0 0xe0>; + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0>; qcom,sde-dither-version = <0x00020000>; qcom,sde-dither-size = <0x20>; @@ -95,7 +95,7 @@ qcom,sde-sspp-smart-dma-priority = <4 1 2 3>; qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - qcom,sde-mixer-pair-mask = <0 3 2>; + qcom,sde-mixer-pair-mask = <0 0 4 3>; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; From a0ded072040b5024ee893f6ce3aedef7fd2893b8 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 13 Jan 2021 11:54:34 +0530 Subject: [PATCH 199/327] ARM: dts: msm: Update lcdb ldo/ncp voltage for yupik Update lcdb ldo and ncp minimum voltage to 5.6V on yupik idp platform. Change-Id: I1fe6a46cd9c549e7b9d4a678ef22a27683635c5f --- display/yupik-sde-display-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index a8c8e500697a..d91b86f042f2 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -64,7 +64,7 @@ qcom,panel-supply-entry@1 { reg = <1>; qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; + qcom,supply-min-voltage = <5600000>; qcom,supply-max-voltage = <6000000>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; @@ -73,7 +73,7 @@ qcom,panel-supply-entry@2 { reg = <2>; qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; + qcom,supply-min-voltage = <5600000>; qcom,supply-max-voltage = <6000000>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; From c00a2ead24819fb5ccd5e8f48ed7320dc9e9d628 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Wed, 13 Jan 2021 14:15:03 +0530 Subject: [PATCH 200/327] ARM: dts: msm: add pll revision for yupik target Add pll revision for yupik target. Change-Id: Ied69469dcb6bc0dec1a64fb050dbaca44c6abff3 --- display/yupik-sde.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index ab62f8bc5bab..9883ea6ae039 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -32,7 +32,7 @@ <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, - <0xaf01068 0x1a0>, + <0xaf00f98 0x1a0>, <0x88ea000 0x200>, <0x88e8000 0x20>, <0x0aee1000 0x034>, @@ -45,6 +45,7 @@ interrupt-parent = <&mdss_mdp>; interrupts = <12 0>; + qcom,pll-revision = "7nm"; #clock-cells = <1>; clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&clock_rpmh RPMH_CXO_CLK>, From 29b1a28e725ac6756c95843a165766f49cfa893a Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Mon, 11 Jan 2021 16:16:06 +0800 Subject: [PATCH 201/327] ARM: dts: msm: add r66451 display cphy panel support for yupik qrd Add r66451 display cphy panel support for yupik qrd. Change-Id: I91b93b54396df275357743df7af9c0659e84f04f --- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 134 ++++++++++++++++++ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 110 ++++++++++++++ display/yupik-sde-display-common.dtsi | 30 +++- display/yupik-sde-display-qrd.dtsi | 36 +++++ 4 files changed, 309 insertions(+), 1 deletion(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi create mode 100644 display/yupik-sde-display-qrd.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..6ff943606cce --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -0,0 +1,134 @@ +&mdss_mdp { + dsi_r66451_amoled_144hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..a9aa91546d5c --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -0,0 +1,110 @@ +&mdss_mdp { + dsi_r66451_amoled_90hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 10 00 00 00 09 40 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index d91b86f042f2..b4cd94c1e229 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,5 +1,7 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include &soc { @@ -105,7 +107,6 @@ }; }; - &dsi_nt36672e_fhd_plus_60_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { @@ -117,3 +118,30 @@ }; }; }; + +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 21 1f 06 + 19 07 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi new file mode 100644 index 000000000000..71120732ef0f --- /dev/null +++ b/display/yupik-sde-display-qrd.dtsi @@ -0,0 +1,36 @@ +#include "yupik-sde-display.dtsi" + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + }; +}; + +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&sde_dsi { + vddio-supply = <&L12C>; + vdd-supply = <&L13C>; + lab-supply = <&ab_vreg>; + ibb-supply = <&ibb_vreg>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy >; +}; From 97f4b2e2724df7c46f1e7eab22f1e254f79607d6 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Fri, 15 Jan 2021 11:06:10 +0530 Subject: [PATCH 202/327] ARM: dts: msm: correct the clock references for yupik target Correct the clock references for yupik target. Change-Id: If1ef29498c827d11ab4c56cfff8bbb7505271946 --- display/yupik-sde.dtsi | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index ab62f8bc5bab..3eb918fd9300 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -46,14 +46,14 @@ interrupts = <12 0>; #clock-cells = <1>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", "pixel_clk_rcg", "pixel_parent","strm0_pixel_clk"; @@ -74,7 +74,6 @@ vdda-1p2-supply = <&L6B>; vdda-0p9-supply = <&L1B>; - vdd_mx-supply = <&VDD_MXA_LEVEL>; qcom,ctrl-supply-entries { #address-cells = <1>; From 9296ca397319abb5c9f618e05a51f2cbd638d2c6 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Fri, 15 Jan 2021 15:39:57 +0530 Subject: [PATCH 203/327] ARM: dts: msm: add merge 3d block in yupik target Add 3d merge block in yupik target. Removed scheduler op4 and op5. Change-Id: Id27f756c9d8f6bf1947470ee1f7891413d644e8e --- display/yupik-sde-common.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 5853774a468e..2a106f69f8bc 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -24,10 +24,10 @@ qcom,sde-len = <0x494>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 - 0x19000 0x1a000 0x1b000>; + 0x19000>; qcom,sde-ctl-size = <0x1e8>; qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none", "none"; + "none"; qcom,sde-mixer-off = <0x45000 0x45000 0x47000 0x48000>; qcom,sde-mixer-size = <0x320>; @@ -64,6 +64,10 @@ 0x6c000 0x6d000>; qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x50000 0x50000>; + qcom,sde-merge-3d-size = <0x10>; qcom,sde-cdm-off = <0x7a200>; qcom,sde-cdm-size = <0x224>; @@ -109,7 +113,7 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, - <0x2ac 8>, <0x2b4 8>, <0x2bc 8>; + <0x2ac 8>, <0x2b4 8>, <0x2c4 8>; qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>, <0x2b8 12>, <0x2c8 12>; From 0d91f0552770cd16aa1e24aa82f94e8d5c6a717c Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 19 Jan 2021 04:45:47 +0530 Subject: [PATCH 204/327] ARM: dts: msm: Update lcd setting for yupik Update lcd setting for yupik idp platform. Change-Id: I0a02725e0f57e9c0e4f88481f370c674b156a2ac --- display/yupik-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index e85af3a1b632..7d939b6b3714 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -32,7 +32,7 @@ qcom,platform-te-gpio = <&tlmm 80 0>; qcom,panel-te-source = <0>; - vddio-supply = <&L12C>; + vddio-supply = <&L8C>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; }; From 51101eaf233cfe31be02387716fe28cad3d38d71 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 19 Jan 2021 04:42:02 +0530 Subject: [PATCH 205/327] ARM: dts: msm: Select 60Hz Video as default panel on yupik Select 60Hz video mode as default panel on yupik idp platform. Change-Id: Icd9f8d43d6cae4d0bda43b4f1e2ff139afec6f2a --- display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi | 1 - display/yupik-sde-display-idp.dtsi | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi index c9f454a0c27e..92f70b56493e 100644 --- a/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi +++ b/display/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi @@ -45,7 +45,6 @@ 39 01 00 00 00 00 02 B0 00 39 01 00 00 00 00 02 C0 00 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 - 14 01 00 01 11 00 01 C1 39 01 00 00 00 00 03 C2 1B A0 39 01 00 00 00 00 02 FF 20 39 01 00 00 00 00 02 FB 01 diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 31e06dd7bacc..50c7e266a497 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -17,6 +17,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_144_video>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; + vddio-supply = <&L8C>; }; From ab1334c06400e352e96e9efc3e43ce0b25f20c08 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 18 Jan 2021 22:31:41 +0530 Subject: [PATCH 206/327] ARM: dts: msm: remove gcc ahb clock for yupik Clock drivers have moved GCC_DISP_AHB_CLK to their probe and kept it always ON, and are not registering this clock with the framework. Hence, removing GCC_DISP_AHB_CLK from display clock list. Change-Id: Ifc21194814275f65776c642777263d9d37da3637 --- display/yupik-sde-common.dtsi | 4 ++-- display/yupik-sde.dtsi | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 2a106f69f8bc..ca5e68650d1b 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -10,8 +10,8 @@ "vbif_phys", "regdma_phys"; - clock-rate = <0 0 0 0 506666667 19200000 506666667 19200000>; - clock-max-rate = <0 0 0 0 608000000 19200000 608000000 + clock-rate = <0 0 0 506666667 19200000 506666667 19200000>; + clock-max-rate = <0 0 0 608000000 19200000 608000000 608000000>; /* interrupt config */ diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 464d7c34968c..d3cefc88044b 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -47,7 +47,6 @@ &mdss_mdp { clocks = - <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -55,7 +54,7 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + clock-names = "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; From ce9c1a5cd1d8766bab7bd491d57a2901c7ec54ce Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 20 Jan 2021 17:15:47 +0800 Subject: [PATCH 207/327] ARM: dts: msm: increase vddio voltage to 1.88v for qrd Some qrd devices vddio voltage have larger drop, need to increase the vddio votage to 1.88v, then they might work well. Change-Id: I951dc1240a84161828dc6a0e79a79aff15fb8d16 --- display/lahaina-sde-display-qrd.dtsi | 4 ++-- display/shima-sde-display-qrd.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index a82336ce618e..f70f7d46176d 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -2,8 +2,8 @@ &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { - qcom,supply-min-voltage = <1860000>; - qcom,supply-max-voltage = <1860000>; + qcom,supply-min-voltage = <1880000>; + qcom,supply-max-voltage = <1880000>; }; }; diff --git a/display/shima-sde-display-qrd.dtsi b/display/shima-sde-display-qrd.dtsi index bbd34e09bda6..b5a0ab04fa79 100644 --- a/display/shima-sde-display-qrd.dtsi +++ b/display/shima-sde-display-qrd.dtsi @@ -2,8 +2,8 @@ &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { - qcom,supply-min-voltage = <1860000>; - qcom,supply-max-voltage = <1860000>; + qcom,supply-min-voltage = <1880000>; + qcom,supply-max-voltage = <1880000>; }; }; From 451521798247aa8a16349a1e81fa359299d7f063 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 22 Jan 2021 10:49:26 +0530 Subject: [PATCH 208/327] ARM: dts: msm: Enable ESD feature on yupik idp Enable ESD feature for video mode panel on yupik idp platform. Change-Id: I25328ef729133865d15ae7427fca0e39a94aa0fa --- display/yupik-sde-display.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7d939b6b3714..5c04e4d978c7 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -40,3 +40,21 @@ &mdss_mdp { connectors = <&sde_wb &sde_dsi>; }; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 8a08711f31c73dd9e3eb248b45ae86767cbba308 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Fri, 22 Jan 2021 19:38:44 +0530 Subject: [PATCH 209/327] ARM: dts: msm: enable SDE RSC driver on yupik Enable sde rscc v4 driver on yupik target Change-Id: If3cec83048cb3061cf02c7b9d96256fd9b28d6f8 --- display/yupik-sde-display.dtsi | 2 +- display/yupik-sde.dtsi | 16 ---------------- 2 files changed, 1 insertion(+), 17 deletions(-) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7d939b6b3714..4c4de67ec5a0 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -38,5 +38,5 @@ }; &mdss_mdp { - connectors = <&sde_wb &sde_dsi>; + connectors = <&sde_wb &sde_dsi &sde_rscc>; }; diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index bc1a0b82e06d..5be02098e827 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -122,7 +122,6 @@ sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; - status = "disabled"; reg = <0xaf20000 0x4d68>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -180,25 +179,10 @@ &cnoc2 SLAVE_DISPLAY_CFG>; interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; qcom,sde-has-idle-pc; qcom,sde-dspp-ltm-version = <0x00010001>; /* offsets are based off dspp 0 */ qcom,sde-dspp-ltm-off = <0x15300>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi0 { From 2178aab16ceba6270e6409692d01b35c83ac0e07 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 25 Jan 2021 18:48:21 +0530 Subject: [PATCH 210/327] ARM: dts: msm: add smmu nodes in mdp connector list for yupik target Add smmu nodes in mdp connector list for yupik target. Change-Id: If66db7aada636ca8d3f1fc9a3a800fe8e38b9d53 --- display/yupik-sde-common.dtsi | 2 +- display/yupik-sde-display.dtsi | 2 +- display/yupik-sde.dtsi | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 40f403744008..fcdf37a6c5d4 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -191,7 +191,7 @@ qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - qcom,sde-secure-sid-mask = <0x4000901>; + qcom,sde-secure-sid-mask = <0x901 0xD01>; /* SPMI address related to display */ qcom,pmic-arb = <&spmi_bus>; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7adaccbdd5b8..71e495a3ffa5 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -38,7 +38,7 @@ }; &mdss_mdp { - connectors = <&sde_wb &sde_dsi &sde_rscc>; + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_rscc>; }; &dsi_nt36672e_fhd_plus_60_video { diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 5be02098e827..631580dab3dd 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -153,7 +153,8 @@ smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x901 0x400>; + iommus = <&apps_smmu 0x901 0x0>, + <&apps_smmu 0xD01 0x0>; qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; From 2eb2c30f0edd7b7cff2e9ca60e24df72ed8ac8de Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sat, 23 Jan 2021 16:17:05 +0530 Subject: [PATCH 211/327] ARM: dts: msm: Enable DFPS feature on yupik idp Enable DFPS feature to support 120, 60 and 48 fps for 144Hz Video mode panel on yupik idp. Change-Id: I2846c65ee43322949980db3c1fdcf46161995b09 --- display/yupik-sde-display-common.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index b4cd94c1e229..80ed70b3527d 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -97,6 +97,9 @@ &dsi_nt36672e_fhd_plus_144_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <144 120 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 From 42f1bbcf3e2b10a2a77d7e1bdbf17fcae646eea2 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sun, 24 Jan 2021 11:08:26 +0530 Subject: [PATCH 212/327] ARM: dts: msm: Add amoled cphy panel support on yupik Add amoled cphy command mode panel support for 90Hz and 144Hz on yupik idp platform. Change-Id: I3d83a2b603a05d213124ea8d7a8dc4122346844a --- display/yupik-sde-display-common.dtsi | 25 +++++++++++++++++++++++++ display/yupik-sde-display-idp.dtsi | 25 ++++++++++++++++++++++--- display/yupik-sde-display.dtsi | 18 ++++++++++++++++++ 3 files changed, 65 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index b4cd94c1e229..71160b50c270 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -83,6 +83,31 @@ }; }; + dsi_panel_pwr_supply_amoled: dsi_panel_pwr_supply_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 50c7e266a497..d3886dad50f1 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -16,8 +16,27 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; -&sde_dsi { - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; - vddio-supply = <&L8C>; +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; }; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7adaccbdd5b8..2c4cc24f002c 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -58,3 +58,21 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_90hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_144hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From 37b3c2a81554b8423620e5c8d99c5c6600b1ab2b Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Wed, 27 Jan 2021 10:39:28 +0800 Subject: [PATCH 213/327] ARM: dts: msm: enable display external vdd power for qrd yupik Enable a new external vdd power for qrd panel. Change-Id: I6330b3e52e79b535385a46a5aa4854dda7b0c540 --- display/yupik-sde-display-qrd.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index 71120732ef0f..e7a88a182bea 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -5,6 +5,15 @@ qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <1800000>; }; + qcom,panel-supply-entry@4 { + reg = <4>; + qcom,supply-name = "extvdd"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <60700>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <0>; + }; }; &dsi_r66451_amoled_90hz_cmd_cphy { @@ -32,5 +41,6 @@ vdd-supply = <&L13C>; lab-supply = <&ab_vreg>; ibb-supply = <&ibb_vreg>; - qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy >; + extvdd-supply = <&pm8350b_l1>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_144hz_cmd_cphy>; }; From a6f27505e4e0dcd8ce52142e557c857588df53c9 Mon Sep 17 00:00:00 2001 From: Rajat Gupta Date: Fri, 22 Jan 2021 15:51:43 +0530 Subject: [PATCH 214/327] ARM: dts: msm: enable dp for yupik target Enable display port for yupik target. Change-Id: I659877278509f1dacb11c440fb6b7a43d7ddf6a8 --- display/yupik-sde-display.dtsi | 2 +- display/yupik-sde.dtsi | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index f79c40f89def..7359e3d9d407 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -38,7 +38,7 @@ }; &mdss_mdp { - connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_rscc>; + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi &sde_rscc &sde_dp>; }; &dsi_nt36672e_fhd_plus_60_video { diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 631580dab3dd..5367d035d47c 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -15,7 +15,6 @@ }; sde_dp: qcom,dp_display@ae90000 { - status="disabled"; cell-index = <0>; compatible = "qcom,dp-display"; From f140b74952362eb296356ba4ef816893483f5e12 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Thu, 28 Jan 2021 17:04:48 +0530 Subject: [PATCH 215/327] ARM: dts: msm: add trusted vm display dtsi files for yupik target Add trusted VM display device tree files for yupik. Change-Id: I3ecef743c38a5751d3db13ee0d4f72fc00b2b15c --- display/trustedvm-yupik-sde-display.dtsi | 26 +++++++++++ display/trustedvm-yupik-sde.dtsi | 55 ++++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 display/trustedvm-yupik-sde-display.dtsi create mode 100644 display/trustedvm-yupik-sde.dtsi diff --git a/display/trustedvm-yupik-sde-display.dtsi b/display/trustedvm-yupik-sde-display.dtsi new file mode 100644 index 000000000000..7919d11a4a16 --- /dev/null +++ b/display/trustedvm-yupik-sde-display.dtsi @@ -0,0 +1,26 @@ +#include "yupik-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + qcom,panel-te-source = <0>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; +}; + + +&mdss_mdp { + connectors = <&sde_dsi>; +}; diff --git a/display/trustedvm-yupik-sde.dtsi b/display/trustedvm-yupik-sde.dtsi new file mode 100644 index 000000000000..a80a08afb696 --- /dev/null +++ b/display/trustedvm-yupik-sde.dtsi @@ -0,0 +1,55 @@ +#include "yupik-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>, + <0x0ae8f000 0x02c>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version = <0x70020000>; + + clocks = + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_cpucc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + qcom,sde-trusted-vm-env; + qcom,vram-size = <0x200000>; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; From add15e2846f03c8789489176b66e59c70673b374 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Fri, 29 Jan 2021 18:16:27 +0800 Subject: [PATCH 216/327] ARM: dts: msm: enable RFI feature for 60hz panel on qrd yupik Add r66451 60hz cphy command mode panel for qrd yupik, and enable RFI and ESD check for this panel. Change-Id: Ibfbb942c4a2747db9b80b0c81cf9cef40803517b --- ...nel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi | 135 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 16 +++ display/yupik-sde-display-qrd.dtsi | 10 ++ display/yupik-sde-display.dtsi | 9 ++ 4 files changed, 170 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..a6564f74dea3 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi @@ -0,0 +1,135 @@ +&mdss_mdp { + dsi_r66451_amoled_60hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_60hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 d1 0b + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 10 04 a0 00 09 40 + 39 01 00 00 00 00 2c c4 00 00 00 00 00 + 00 00 00 0d 00 00 05 00 00 00 36 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 0d 17 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 45 00 00 01 13 + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 95 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3c 00 3c 00 3c 00 3c 00 + 3c 05 00 00 00 00 00 00 00 00 00 0e + 00 0e 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0e 00 36 00 0e 00 30 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 21 00 ff d4 0e 00 00 00 00 + 00 20 00 53 18 20 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 3b 08 04 9a + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 65a61e861a67..01eac6a41f47 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,5 +1,6 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include @@ -147,6 +148,21 @@ }; }; +&dsi_r66451_amoled_60hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <600652800 598150080 595647360>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 + 19 02 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index 71120732ef0f..00b0f2d2a135 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -7,6 +7,16 @@ }; }; +&dsi_r66451_amoled_60hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index f79c40f89def..878e64cfb8cd 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -59,6 +59,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_r66451_amoled_60hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From fc81f2053a20f4d747b75151ab2a4f25ea00648e Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Thu, 28 Jan 2021 11:58:47 +0800 Subject: [PATCH 217/327] ARM: dts: msm: add some more display modes for yupik qrd Add 144hz video, 120hz cmd, and video modes for qrd device. And also enable 120hz cmd dynamic fps switch, 144hz, and 120hz video dfps feature. Change-Id: I5a2e896cf0ad9c3ce8bfd8f4de421385ae98c15e --- ...el-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi | 383 ++++++++++++++++++ ...-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi | 121 ++++++ ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 1 - ...-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi | 123 ++++++ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 1 - display/yupik-sde-display-common.dtsi | 61 +++ display/yupik-sde-display-qrd.dtsi | 30 ++ display/yupik-sde-display.dtsi | 27 ++ 8 files changed, 745 insertions(+), 2 deletions(-) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi new file mode 100644 index 000000000000..ba037bc6840b --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi @@ -0,0 +1,383 @@ +&mdss_mdp { + dsi_r66451_amoled_120hz_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 03 14 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 00 00 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 0c c2 09 24 0c 00 00 + 0c 00 00 00 09 3c + 39 01 00 00 00 00 1a d7 00 b9 3c 00 40 + 04 00 a0 0a 00 40 00 00 00 00 00 00 + 19 3c 00 40 04 00 a0 0a + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 14 de 40 00 18 00 18 + 00 18 00 18 10 00 18 00 18 00 18 02 + 00 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi new file mode 100644 index 000000000000..39e2b56a457a --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi @@ -0,0 +1,121 @@ +&mdss_mdp { + dsi_r66451_amoled_120hz_video_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_120hz_vid { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 6ff943606cce..782f933515b7 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -107,7 +107,6 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi new file mode 100644 index 000000000000..d72020ad1f71 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi @@ -0,0 +1,123 @@ +&mdss_mdp { + dsi_r66451_amoled_144hz_video_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi index a9aa91546d5c..1f2857b7c0cd 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -83,7 +83,6 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 65a61e861a67..d88190c5eac3 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,7 +1,10 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi" #include &soc { @@ -160,6 +163,49 @@ }; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 + 19 02 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 + 19 06 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_120hz_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 + 19 06 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; @@ -173,3 +219,18 @@ }; }; +&dsi_r66451_amoled_144hz_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index e7a88a182bea..e8f03feb5565 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -26,6 +26,26 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + +&dsi_r66451_amoled_120hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -36,6 +56,16 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_r66451_amoled_144hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &sde_dsi { vddio-supply = <&L12C>; vdd-supply = <&L13C>; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7359e3d9d407..f11298e93a81 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -68,6 +68,24 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + +&dsi_r66451_amoled_120hz_video_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -76,3 +94,12 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; }; + +&dsi_r66451_amoled_144hz_video_cphy { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; From c318ad98bff0c333fbbfb37d37a80f85395cdaec Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Mon, 1 Feb 2021 12:13:11 +0530 Subject: [PATCH 218/327] ARM: dts: msm: add display ramdump node for yupik target This change adds dt support for display during ramdump in yupik target. Change-Id: I9784e6bcd8ee787af42e9fa6fa30302adba385fa --- display/yupik-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 5367d035d47c..f664f6d65855 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -2,6 +2,11 @@ #include &soc { + disp_rdump_memory: disp_rdump_region@e1000000 { + reg = <0xe1000000 0x02300000>; + label = "disp_rdump_region"; + }; + ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; From 431e59038734e07d5ee8007b54a01c917843b34f Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Tue, 2 Feb 2021 11:50:23 +0530 Subject: [PATCH 219/327] ARM: dts: msm: remove display related SPMI address for yupik target Remove display related SPMI address for yupik target. Change-Id: Ic42daf564cf9ed2edcd57ccc61d6662e32f8501e --- display/yupik-sde-common.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index fcdf37a6c5d4..16846daaf579 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -193,10 +193,6 @@ qcom,sde-secure-sid-mask = <0x901 0xD01>; - /* SPMI address related to display */ - qcom,pmic-arb = <&spmi_bus>; - qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; - qcom,sde-reg-bus,vectors-KBps = <0 0>, <0 74000>, <0 148000>, From 3ea8483654eb13343b649240914cfb57d689106e Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 2 Feb 2021 18:09:12 +0530 Subject: [PATCH 220/327] ARM: dts: msm: Add 120Hz Video mode support on yupik Add 120Hz nt36672e Video mode panel support on yupik idp platform. Also, enable DFPS and ESD feature for the panel. Change-Id: Ic8e0bf998c3ebf83fba917389754326b39bbac96 --- display/yupik-sde-display-common.dtsi | 16 ++++++++++++++++ display/yupik-sde-display-idp.dtsi | 8 ++++++++ display/yupik-sde-display.dtsi | 9 +++++++++ 3 files changed, 33 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 4412e52d98c2..237b335586e3 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,4 +1,5 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" @@ -139,6 +140,21 @@ }; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <120 60 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 + 08 08 02 04 00 1b 18]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index d3886dad50f1..4fcaf173b2b8 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -8,6 +8,14 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 6a9ebe422387..82bc6fd4768d 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -59,6 +59,15 @@ qcom,mdss-dsi-panel-status-read-length = <1>; }; +&dsi_nt36672e_fhd_plus_120_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; +}; + &dsi_r66451_amoled_60hz_cmd_cphy { qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; From 555ff0e1066f1073aedfc100bca2004596239356 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Wed, 3 Feb 2021 18:22:16 +0530 Subject: [PATCH 221/327] ARM: dts: msm: enable qsync along with VRR in yupik target This change enables qsync support for yupik target along with existing VRR. Change-Id: I6c238fa1bce3102744c10b2b3a2c678773adb922 --- display/yupik-sde-display-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 237b335586e3..4de9ed87f6fa 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -130,6 +130,7 @@ qcom,dsi-supported-dfps-list = <144 120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -145,6 +146,7 @@ qcom,dsi-supported-dfps-list = <120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-qsync-min-refresh-rate = <48>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 From ed33ad6a6d59b0ef055bda4499573b03a9dbd775 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Fri, 5 Feb 2021 17:46:07 +0530 Subject: [PATCH 222/327] ARM: dts: msm: Add display support for r66451 120fps panel Add r66451 120fps display cphy panel support on Yupik target. Change-Id: Ia295e22add42916343e7c12b3fdd64375ebb8d08 --- display/yupik-sde-display-idp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 4fcaf173b2b8..045d7c6ac25f 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -34,6 +34,16 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_r66451_amoled_120hz_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_144hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 7ba9fa1b8b1760cc7311c2fcabfda7e9b2bdf21f Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 1 Feb 2021 21:00:23 +0530 Subject: [PATCH 223/327] ARM: dts: msm: Enable Dynamic clock on yupik IDP Enable Dynamic clock for 144Hz and 120Hz Video mode panel on yupik IDP platform. Change-Id: Ic1df031247fdcc3782d3a2ce231c02524deba74e --- display/yupik-sde-display-common.dtsi | 16 ++++++++++++++-- display/yupik-sde.dtsi | 1 + 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 4de9ed87f6fa..acb348abab67 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -126,11 +126,17 @@ }; &dsi_nt36672e_fhd_plus_144_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-supported-dfps-list = <144 120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-qsync-min-refresh-rate = <48>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <953341056 946720632 950030848>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -142,11 +148,17 @@ }; &dsi_nt36672e_fhd_plus_120_video { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-supported-dfps-list = <120 60 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-qsync-min-refresh-rate = <48>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <901327680 893816616 897572152>; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index f664f6d65855..43f616b8e540 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -207,5 +207,6 @@ vdda-0p9-supply = <&L10C>; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; }; From 97e93b7430d45a250e29e8152161c65af1fbb065 Mon Sep 17 00:00:00 2001 From: Chandan Uddaraju Date: Fri, 29 Jan 2021 17:35:57 -0800 Subject: [PATCH 224/327] ARM: dts: msm: add dispcc clock reference for dsi-display nodes Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes for cont_splash use case. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I47c458f4f6f2937effdd1212496b41eacab4e052 --- display/lahaina-sde-display.dtsi | 41 ++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 685fd53fd828..c448cca46045 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -1,4 +1,5 @@ #include "lahaina-sde-display-common.dtsi" +#include &tlmm { display_panel_avdd_default: display_panel_avdd_default { @@ -59,7 +60,22 @@ <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", @@ -69,7 +85,8 @@ "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", "shadow_byte_clk1", "shadow_pixel_clk1", - "shadow_cphybyte_clk1", "shadow_cphypixel_clk1"; + "shadow_cphybyte_clk1", "shadow_cphypixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -93,11 +110,27 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; From 73f32ee4cf90d844d8b86f1a13d9451497a4c17a Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Tue, 2 Feb 2021 10:51:25 +0530 Subject: [PATCH 225/327] ARM: dts: msm: add dispcc clock reference for dsi-display nodes Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I4c4baf15171a13a066a3383bdc1242279809444d --- display/shima-sde-display.dtsi | 41 ++++++++++++++++++++++++++++++---- display/yupik-sde-display.dtsi | 21 +++++++++++++++-- 2 files changed, 56 insertions(+), 6 deletions(-) diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi index d7f3efc6ec23..2f3634ba7b7a 100644 --- a/display/shima-sde-display.dtsi +++ b/display/shima-sde-display.dtsi @@ -1,4 +1,5 @@ #include "shima-sde-display-common.dtsi" +#include &soc { sde_wb: qcom,wb-display@0 { @@ -24,7 +25,22 @@ <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", @@ -32,7 +48,8 @@ "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; + "shadow_byte_clk1", "shadow_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -55,11 +72,27 @@ <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1"; + "cphy_byte_clk1", "cphy_pixel_clk1", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; diff --git a/display/yupik-sde-display.dtsi b/display/yupik-sde-display.dtsi index 7359e3d9d407..d371070af713 100644 --- a/display/yupik-sde-display.dtsi +++ b/display/yupik-sde-display.dtsi @@ -1,4 +1,5 @@ #include "yupik-sde-display-common.dtsi" +#include &soc { sde_wb: qcom,wb-display@0 { @@ -18,12 +19,28 @@ <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; From 059ffe80af581156ce3777bcc1fb9ada08a17e9f Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Mon, 15 Feb 2021 18:17:10 +0530 Subject: [PATCH 226/327] ARM: dts: msm: Add 60fps display support on Lahaina MTP 2.1 This change adds display support for r66451 dsc fhd plus 60fps command mode panel on lahaina. Change-Id: Icec5feb452347aef02d69fe15f86717f7b4852fe --- display/lahaina-sde-display-common.dtsi | 24 ++++++++++++++++++++++++ display/lahaina-sde-display-mtp.dtsi | 10 ++++++++++ 2 files changed, 34 insertions(+) diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 7b54b749014e..1db49fb02ed8 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -15,6 +15,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" @@ -273,6 +274,29 @@ }; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <327096544 325733641 324370739>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1e 1e 04 + 04 03 02 04 00 10 14]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_144hz_cmd { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index ad1eb186123b..0d39900163fc 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -28,6 +28,16 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_r66451_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 5efac50fc3fbb42d97d8dae27b3a6933394d0abc Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 19 Feb 2021 19:54:09 +0530 Subject: [PATCH 227/327] ARM: dts: msm: Update 120Hz Video as default on yupik svm Update 120Hz Video mode as default panel on yupik idp LA and LE dtsi. Change-Id: I94f9220ce90bd73a0cc9037934514ea66cfb544e --- display/trustedvm-yupik-sde-display.dtsi | 2 +- display/yupik-sde-display-idp.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-yupik-sde-display.dtsi b/display/trustedvm-yupik-sde-display.dtsi index 7919d11a4a16..be0b4c27acca 100644 --- a/display/trustedvm-yupik-sde-display.dtsi +++ b/display/trustedvm-yupik-sde-display.dtsi @@ -17,7 +17,7 @@ "shadow_byte_clk0", "shadow_pixel_clk0", "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; qcom,panel-te-source = <0>; - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; }; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 045d7c6ac25f..e27b789918f7 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -55,6 +55,6 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_60_video>; + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; }; From e975639f71719d53bb5f39211c2e6480766be401 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Fri, 26 Feb 2021 12:55:14 +0530 Subject: [PATCH 228/327] ARM: dts: msm: reduce transfer time by 100 usec in yupik target This change reduces transfer time by 100 usec for 144fps and 120 fps in yupik. Change-Id: Ib92ecba8dcc4779b636c6c8efa926d5af7d1ffc4 --- display/yupik-sde-display-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index acb348abab67..9b6d97247d27 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -232,6 +232,7 @@ 19 06 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,mdss-mdp-transfer-time-us = <7550>; }; }; }; @@ -261,6 +262,7 @@ 19 07 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,mdss-mdp-transfer-time-us = <6210>; }; }; }; From ec7a16dbf560151872df441c3e4236f71197a379 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 3 Feb 2021 12:57:11 +0800 Subject: [PATCH 229/327] ARM: dts: msm: Enable fps switch for 144Hz cphy on yupik qrd Enable 144/120/60 Hz fps switch feature for 144Hz cphy command mode panel on yupik qrd platform. Change-Id: I1343c6419c07b80b93f9572d891c005a7c4c8383 --- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 249 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 14 + 2 files changed, 263 insertions(+) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 782f933515b7..5938221c9fcc 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -48,6 +48,18 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 04 00 00 00 09 34 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 02 b0 04 39 01 00 00 00 00 03 e8 00 02 @@ -113,7 +125,244 @@ 05 01 00 00 78 00 01 11 05 01 00 00 00 00 01 29 ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + timing@1 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 09 3c 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 1a c2 09 24 0c 00 00 + 0c 00 00 00 09 3c 00 00 00 00 00 00 + 00 00 00 00 00 30 00 6c + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 e8 00 02 + 39 01 00 00 00 00 03 e4 00 08 + 39 01 00 00 00 00 03 b4 20 1c + 39 01 00 00 00 00 0d b6 6c 00 06 23 af + 13 1a 05 04 fa 05 20 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 32 c4 00 00 00 00 00 + 00 00 00 10 00 00 02 00 00 00 29 00 + 01 00 00 00 00 00 00 00 00 00 00 00 + 22 00 00 00 00 11 00 00 0c 00 00 00 + 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d + 39 01 00 00 00 00 15 d3 49 00 00 01 1a + 15 00 15 07 0f 77 77 77 37 b2 11 00 + a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 30 00 30 00 30 00 30 00 + 30 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + 39 01 00 00 00 00 2b df 50 42 58 81 2d + 00 00 00 00 00 00 6b 00 00 00 00 00 + 00 00 00 01 0f ff d4 0e 00 00 00 00 + 00 00 0f 53 18 00 0f 00 00 00 00 00 + 00 + 39 01 00 00 00 00 03 eb 8b 8b + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 0a e4 34 b4 00 00 00 + 30 04 0c e2 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 0d d0 44 44 b2 28 00 + 28 5a 00 5a 03 03 01 + 39 01 00 00 00 00 34 d8 00 00 00 00 00 + 00 00 00 00 3a 00 3a 00 3a 00 3a 00 + 3a 05 00 00 00 00 00 00 00 00 00 0f + 00 0f 00 00 00 00 00 00 00 00 00 00 + 00 00 00 0f 00 2f 00 0f 00 20 + ]; qcom,mdss-dsi-off-command = [ 05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 9b6d97247d27..fae8e0561940 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -264,6 +264,20 @@ qcom,default-topology-index = <0>; qcom,mdss-mdp-transfer-time-us = <6210>; }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1d 13 03 + 19 02 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1b 05 + 19 06 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; }; }; From 452b779bf03b90caaac4220416cdb19dae594c15 Mon Sep 17 00:00:00 2001 From: Yashwanth Date: Mon, 8 Mar 2021 10:59:00 +0530 Subject: [PATCH 230/327] ARM: dts: msm: remove fixed transfer time for cphy panels in yupik This change reverts commit 8198c2b43d6e ("reduce transfer time by 100 usec in yupik target"). The original issue of unstable fps on cphy panels will be fixed with commit 72f31fb34bc3 ("disp: msm: dsi: update CPHY command mode clock calculation"). Change-Id: I57ab55416c1fd264b49f9097738942c2b9471096 --- display/yupik-sde-display-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index fae8e0561940..fd0475cfcb0b 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -232,7 +232,6 @@ 19 06 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; - qcom,mdss-mdp-transfer-time-us = <7550>; }; }; }; @@ -262,7 +261,6 @@ 19 07 02 04 00 00 00]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; - qcom,mdss-mdp-transfer-time-us = <6210>; }; timing@1 { From 2509c23273a560dc1332d09294d1aa51e5e7fc5e Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Tue, 9 Mar 2021 11:01:12 +0530 Subject: [PATCH 231/327] ARM: dts: msm: add scaler max line width for yupik target This change adds check for max line width for scaling in yupik target. Change-Id: Iec4ca10b7f52cdbedd53c9b0de17cf9d573170a9 --- display/yupik-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/yupik-sde-common.dtsi b/display/yupik-sde-common.dtsi index 16846daaf579..e44b556dac4a 100644 --- a/display/yupik-sde-common.dtsi +++ b/display/yupik-sde-common.dtsi @@ -125,6 +125,7 @@ qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2400>; qcom,sde-vig-sspp-linewidth = <4096>; + qcom,sde-scaling-linewidth = <2560>; qcom,sde-wb-linewidth = <4096>; qcom,sde-wb-linewidth-linear = <4096>; qcom,sde-mixer-blendstages = <0x9>; From f8ae9ee4764e9e8912d92b1d1322a4bcff46434d Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 10 Mar 2021 16:04:13 +0530 Subject: [PATCH 232/327] ARM: dts: msm: Remove timing nodes from sim panel Remove timing nodes from dual dsi dsc sim panel to reduce dtbo image size. Change-Id: I6cabb57da9b49420f3f731f54eb7ef5ef183dcec --- .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 1448 ----------------- display/kona-sde-display.dtsi | 112 -- display/lahaina-sde-display-common.dtsi | 126 -- 3 files changed, 1686 deletions(-) diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index 6b5a5b7f04f9..4087a2219dd8 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -89,1454 +89,6 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; - - timing@1 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <90>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@3 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@4 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <30>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@5 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@6 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <90>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@7 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@8 { - qcom,mdss-dsi-panel-framerate = <30>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@9 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@10 { - qcom,mdss-dsi-panel-framerate = <90>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@11 { - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@12 { - qcom,mdss-dsi-panel-width = <2520>; - qcom,mdss-dsi-panel-height = <2160>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <1080>; - qcom,mdss-dsc-slice-width = <1260>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@13 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <30>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@14 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@15 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <90>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@16 { - qcom,mdss-dsi-panel-width = <360>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@17 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <144>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@18 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <144>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; }; }; }; diff --git a/display/kona-sde-display.dtsi b/display/kona-sde-display.dtsi index a477f44fffc0..00c36cf8e166 100644 --- a/display/kona-sde-display.dtsi +++ b/display/kona-sde-display.dtsi @@ -721,118 +721,6 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; - - timing@1 { /* 4k 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 - 06 04 02 04 00 15 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 4k 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09 - 09 06 02 04 00 1c 19]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4k 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c - 0c 08 02 04 00 24 1b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@4 { /* 1080 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 - 01 01 02 04 00 0a 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@5 { /* 1080 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 02 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* 1080 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04 - 03 02 02 04 00 0e 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@7 { /* 1080 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04 - 04 02 02 04 00 10 14]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@8 { /* qhd 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 - 02 01 02 04 00 0b 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@9 { /* qhd 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04 - 04 02 02 04 00 0f 13]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@10 { /* qhd 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05 - 05 03 02 04 00 12 15]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@11 { /* qhd 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07 - 06 04 02 04 00 15 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@12 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 - 07 04 02 04 00 16 16]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@13 { /* 720p 30 FPS */ - qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01 - 01 00 02 04 00 08 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@14 { /* 720p 60 FPS */ - qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 - 01 01 02 04 00 0a 11]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@15 { /* 720p 90 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02 - 02 01 02 04 00 0b 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@16 { /* 720 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03 - 03 01 02 04 00 0c 12]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; }; }; diff --git a/display/lahaina-sde-display-common.dtsi b/display/lahaina-sde-display-common.dtsi index 1db49fb02ed8..35e4b962161f 100644 --- a/display/lahaina-sde-display-common.dtsi +++ b/display/lahaina-sde-display-common.dtsi @@ -752,132 +752,6 @@ qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; - - timing@1 { /* 4k 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05 - 05 03 02 04 00 10 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 4k 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 1a 08 07 0c 0b 08 - 08 05 02 04 00 16 0c]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@3 { /* 4k 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@4 { /* 1080 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [01 04 01 01 03 03 01 - 01 01 02 04 00 05 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@5 { /* 1080 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 07 02 02 04 04 02 - 02 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@6 { /* 1080 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@7 { /* 1080 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 06 06 04 - 04 02 02 04 00 0c 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@8 { /* qhd 30 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 06 01 01 03 03 02 - 01 00 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@9 { /* qhd 60 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 09 03 03 05 05 03 - 03 01 02 04 00 09 08]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@10 { /* qhd 90 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 0e 03 04 07 06 04 - 04 02 02 04 00 0c 09]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@11 { /* qhd 120 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05 - 05 03 02 04 00 0f 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@12 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 17 07 06 0b 0a 07 - 07 04 02 04 00 14 0b]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@13 { /* 720p 30 FPS */ - qcom,mdss-dsi-panel-phy-timings = [03 03 00 01 02 02 01 - 01 00 02 04 00 04 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@14 { /* 720p 60 FPS */ - qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 - 01 01 02 04 00 06 06]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@15 { /* 720p 90 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 06 02 02 04 04 02 - 02 01 02 04 00 07 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@16 { /* 720 120 FPS */ - qcom,mdss-dsi-panel-phy-timings = [00 08 02 02 04 04 03 - 03 01 02 04 00 08 07]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@17 { /* 1080 144FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 - 06 06 02 04 00 13 0a]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@18 { /* WQHD 144 FPS*/ - qcom,mdss-dsi-panel-phy-timings = [00 23 0a 09 10 0e 0a - 0a 07 02 04 00 1d 0e]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; }; }; From 50b8070a9106ad630e55361bb703ffc953e8fa94 Mon Sep 17 00:00:00 2001 From: Bruce Hoo Date: Fri, 19 Mar 2021 15:23:17 +0800 Subject: [PATCH 233/327] ARM: dts: msm: Update dsi-on-command to fix brightness issue on yupik qrd Update dsi-on-command to fix low brightness issue on yupik qrd. Change-Id: I29c4747229a16d205b2fe888ac5e954ae5273b4c --- ...el-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi | 57 ++----------------- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 57 ++----------------- ...nel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi | 18 ------ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 17 ------ 4 files changed, 12 insertions(+), 137 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi index ba037bc6840b..a956720ea3b1 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi @@ -79,26 +79,9 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -139,6 +122,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -196,26 +181,9 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -256,6 +224,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -313,26 +283,9 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -369,6 +322,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 5938221c9fcc..408f668ba110 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -73,28 +73,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -130,6 +113,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -182,28 +167,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -251,6 +219,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -304,28 +274,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a - 39 01 00 00 00 00 1a d7 00 b9 34 00 40 - 04 00 f0 0f 00 40 00 00 00 00 00 00 - 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -368,6 +321,8 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi index a6564f74dea3..e7b81243224f 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi @@ -62,28 +62,11 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 0d 17 01 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 95 - 39 01 00 00 00 00 1a d7 00 b9 40 00 40 - 00 00 e0 0e 00 40 00 00 00 00 00 00 - 19 40 00 00 00 00 e0 0e 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3c 00 3c 00 3c 00 3c 00 3c 05 00 00 00 00 00 00 00 00 00 0e @@ -108,7 +91,6 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 - 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi index 1f2857b7c0cd..e59208eb7b21 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -57,23 +57,6 @@ 13 1a 05 04 fa 05 20 39 01 00 00 00 00 0c c2 09 24 0c 00 00 10 00 00 00 09 40 - 39 01 00 00 00 00 1a d7 00 b9 40 00 40 - 00 00 e0 0e 00 40 00 00 00 00 00 00 - 19 40 00 00 00 00 e0 0e - 39 01 00 00 00 00 86 cf 64 0b 00 22 00 - cd 03 33 04 00 0b 77 01 01 01 02 02 - 03 03 04 04 04 04 05 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 00 00 00 3b 00 - 3b 01 64 01 64 01 64 01 64 01 64 01 - 64 03 ff 03 ff 03 ff 01 62 01 62 01 - 62 01 62 01 62 01 62 01 62 01 62 01 - 62 01 62 01 62 01 62 19 19 19 19 19 - 19 19 19 19 19 19 19 00 00 00 43 00 - 43 01 98 01 98 06 61 06 61 0f f6 0f - f6 0f f6 0f f6 0f f6 19 - 39 01 00 00 00 00 09 d1 05 00 21 02 24 - 19 24 2d 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 From 2efad915bb51be8a56ee123f82e17a22470f733d Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Tue, 6 Apr 2021 18:56:28 +0530 Subject: [PATCH 234/327] ARM: dts: msm: Add support for sim vid panel on Yupik This change adds support for sim vid panel on Yupik. Change-Id: If43074bfd2ffd20e277e2c80a092b6ac27fdaafd --- display/yupik-sde-display-common.dtsi | 13 +++++++++++++ display/yupik-sde-display-idp.dtsi | 6 ++++++ display/yupik-sde-display-qrd.dtsi | 6 ++++++ 3 files changed, 25 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index fd0475cfcb0b..3f1debe20f9b 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -7,6 +7,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-120hz-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi" +#include "dsi-panel-sim-video.dtsi" #include &soc { @@ -294,3 +295,15 @@ }; }; }; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index e27b789918f7..26f690f77de3 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -54,6 +54,12 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; }; diff --git a/display/yupik-sde-display-qrd.dtsi b/display/yupik-sde-display-qrd.dtsi index dbd96c47b950..c03b994e5eea 100644 --- a/display/yupik-sde-display-qrd.dtsi +++ b/display/yupik-sde-display-qrd.dtsi @@ -76,6 +76,12 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &sde_dsi { vddio-supply = <&L12C>; vdd-supply = <&L13C>; From 316036281b3cd939768723ab6b3d5e18d43d94ef Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 26 Apr 2021 19:06:47 +0530 Subject: [PATCH 235/327] Revert "ARM: dts: msm: Update dsi-on-command to fix brightness issue on yupik qrd" This reverts commit 50b8070a9106ad630e55361bb703ffc953e8fa94. Change-Id: I1656aba5ff0dc3733cc0cf044604d528ffab922a --- ...el-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi | 57 +++++++++++++++++-- ...el-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi | 57 +++++++++++++++++-- ...nel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi | 18 ++++++ ...nel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi | 17 ++++++ 4 files changed, 137 insertions(+), 12 deletions(-) diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi index a956720ea3b1..ba037bc6840b 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi @@ -79,9 +79,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -122,8 +139,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -181,9 +196,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -224,8 +256,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -283,9 +313,26 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3a 00 3a 00 3a 00 3a 00 3a 05 00 00 00 00 00 00 00 00 00 0f @@ -322,8 +369,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi index 408f668ba110..5938221c9fcc 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi @@ -73,11 +73,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -113,8 +130,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -167,11 +182,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -219,8 +251,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; @@ -274,11 +304,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 00 00 00 00 00 00 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 03 0d 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 49 00 00 01 1a 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 9a + 39 01 00 00 00 00 1a d7 00 b9 34 00 40 + 04 00 f0 0f 00 40 00 00 00 00 00 00 + 19 34 00 40 04 00 f0 0f 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 30 00 30 00 30 00 30 00 30 05 00 00 00 00 00 00 00 00 00 0f @@ -321,8 +368,6 @@ 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; qcom,mdss-dsc-slice-height = <20>; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi index e7b81243224f..a6564f74dea3 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi @@ -62,11 +62,28 @@ 01 00 00 00 00 00 00 00 00 00 00 00 22 00 00 00 00 11 00 00 0c 00 00 00 00 30 + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 39 01 00 00 00 00 0d d0 44 44 b2 28 00 28 5a 00 5a 0d 17 01 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 15 d3 45 00 00 01 13 15 00 15 07 0f 77 77 77 37 b2 11 00 a0 3c 95 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e 39 01 00 00 00 00 34 d8 00 00 00 00 00 00 00 00 00 3c 00 3c 00 3c 00 3c 00 3c 05 00 00 00 00 00 00 00 00 00 0e @@ -91,6 +108,7 @@ 39 01 00 00 00 00 03 f4 00 02 39 01 00 00 00 00 02 f2 19 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 03 51 0f ff 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 23 diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi index e59208eb7b21..1f2857b7c0cd 100644 --- a/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi +++ b/display/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi @@ -57,6 +57,23 @@ 13 1a 05 04 fa 05 20 39 01 00 00 00 00 0c c2 09 24 0c 00 00 10 00 00 00 09 40 + 39 01 00 00 00 00 1a d7 00 b9 40 00 40 + 00 00 e0 0e 00 40 00 00 00 00 00 00 + 19 40 00 00 00 00 e0 0e + 39 01 00 00 00 00 86 cf 64 0b 00 22 00 + cd 03 33 04 00 0b 77 01 01 01 02 02 + 03 03 04 04 04 04 05 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 00 00 00 3b 00 + 3b 01 64 01 64 01 64 01 64 01 64 01 + 64 03 ff 03 ff 03 ff 01 62 01 62 01 + 62 01 62 01 62 01 62 01 62 01 62 01 + 62 01 62 01 62 01 62 19 19 19 19 19 + 19 19 19 19 19 19 19 00 00 00 43 00 + 43 01 98 01 98 06 61 06 61 0f f6 0f + f6 0f f6 0f f6 0f f6 19 + 39 01 00 00 00 00 09 d1 05 00 21 02 24 + 19 24 2d 39 01 00 00 00 00 03 eb 8b 8b 39 01 00 00 00 00 02 f7 01 39 01 00 00 00 00 03 df 50 40 From 76b011f12402d5fa8bce5c0d7ed5d7a2ca04730e Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 29 Apr 2021 16:32:25 +0530 Subject: [PATCH 236/327] ARM: dts: msm: Add NT36672E 90hz Video Mode Panel on Yupik IDP Add NT36672E 90fps fhd plus Video mode panel support on yupik platform. Change-Id: Ic1506e239f8d473c8bd005591905429d0ea993d4 --- ...si-panel-nt36672e-fhd-plus-90hz-video.dtsi | 480 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 13 + display/yupik-sde-display-idp.dtsi | 8 + 3 files changed, 501 insertions(+) create mode 100644 display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi diff --git a/display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi b/display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi new file mode 100644 index 000000000000..02f1cee08a1a --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi @@ -0,0 +1,480 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_90hz_video: qcom,mdss_dsi_nt36672e_fhd_plus_90hz_video { + qcom,mdss-dsi-panel-name = + "nt36672e 90Hz fhd plus video mode panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750 + 39800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <68>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 39 01 00 00 00 00 03 C2 1B A0 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 66 + 39 01 00 00 00 00 02 06 40 + 39 01 00 00 00 00 02 07 38 + 39 01 00 00 00 00 02 18 66 + 39 01 00 00 00 00 02 1B 01 + 39 01 00 00 00 00 02 5C 90 + 39 01 00 00 00 00 02 5E AA + 39 01 00 00 00 00 02 69 91 + + 39 01 00 00 00 00 02 89 0D + 39 01 00 00 00 00 02 8A 0D + 39 01 00 00 00 00 02 8D 0D + 39 01 00 00 00 00 02 8E 0D + 39 01 00 00 00 00 02 8F 0D + 39 01 00 00 00 00 02 91 0D + + 39 01 00 00 00 00 02 95 D1 + 39 01 00 00 00 00 02 96 D1 + 39 01 00 00 00 00 02 F2 65 + 39 01 00 00 00 00 02 F3 64 + 39 01 00 00 00 00 02 F4 65 + 39 01 00 00 00 00 02 F5 64 + 39 01 00 00 00 00 02 F6 65 + 39 01 00 00 00 00 02 F7 64 + 39 01 00 00 00 00 02 F8 65 + 39 01 00 00 00 00 02 F9 64 + + 39 01 00 00 00 00 02 FF 24 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 0F + 39 01 00 00 00 00 02 03 0C + 39 01 00 00 00 00 02 05 1D + 39 01 00 00 00 00 02 08 2F + 39 01 00 00 00 00 02 09 2E + 39 01 00 00 00 00 02 0A 2D + 39 01 00 00 00 00 02 0B 2C + 39 01 00 00 00 00 02 11 17 + 39 01 00 00 00 00 02 12 13 + 39 01 00 00 00 00 02 13 15 + 39 01 00 00 00 00 02 15 14 + 39 01 00 00 00 00 02 16 16 + 39 01 00 00 00 00 02 17 18 + 39 01 00 00 00 00 02 1B 01 + 39 01 00 00 00 00 02 1D 1D + 39 01 00 00 00 00 02 20 2F + 39 01 00 00 00 00 02 21 2E + 39 01 00 00 00 00 02 22 2D + 39 01 00 00 00 00 02 23 2C + 39 01 00 00 00 00 02 29 17 + 39 01 00 00 00 00 02 2A 13 + 39 01 00 00 00 00 02 2B 15 + 39 01 00 00 00 00 02 2F 14 + 39 01 00 00 00 00 02 30 16 + 39 01 00 00 00 00 02 31 18 + 39 01 00 00 00 00 02 32 04 + 39 01 00 00 00 00 02 34 10 + 39 01 00 00 00 00 02 35 1F + 39 01 00 00 00 00 02 36 1F + 39 01 00 00 00 00 02 4D 19 + 39 01 00 00 00 00 02 4E 45 + 39 01 00 00 00 00 02 4F 45 + 39 01 00 00 00 00 02 53 45 + 39 01 00 00 00 00 02 71 30 + 39 01 00 00 00 00 02 79 11 + 39 01 00 00 00 00 02 7A 82 + 39 01 00 00 00 00 02 7B 94 + 39 01 00 00 00 00 02 7D 04 + 39 01 00 00 00 00 02 80 04 + 39 01 00 00 00 00 02 81 04 + 39 01 00 00 00 00 02 82 13 + 39 01 00 00 00 00 02 84 31 + 39 01 00 00 00 00 02 85 00 + 39 01 00 00 00 00 02 86 00 + 39 01 00 00 00 00 02 87 00 + 39 01 00 00 00 00 02 90 13 + 39 01 00 00 00 00 02 92 31 + 39 01 00 00 00 00 02 93 00 + 39 01 00 00 00 00 02 94 00 + 39 01 00 00 00 00 02 95 00 + 39 01 00 00 00 00 02 9C F4 + 39 01 00 00 00 00 02 9D 01 + 39 01 00 00 00 00 02 A0 14 + 39 01 00 00 00 00 02 A2 14 + 39 01 00 00 00 00 02 A3 02 + 39 01 00 00 00 00 02 A4 04 + 39 01 00 00 00 00 02 A5 04 + 39 01 00 00 00 00 02 C4 40 + 39 01 00 00 00 00 02 C6 C0 + 39 01 00 00 00 00 02 C9 00 + 39 01 00 00 00 00 02 D9 80 + 39 01 00 00 00 00 02 E9 02 + + 39 01 00 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88 06 + 39 01 00 00 00 00 02 8A 1A + 39 01 00 00 00 00 02 8B 11 + 39 01 00 00 00 00 02 8C 24 + 39 01 00 00 00 00 02 8E 42 + 39 01 00 00 00 00 02 8F 11 + 39 01 00 00 00 00 02 90 11 + 39 01 00 00 00 00 02 91 11 + 39 01 00 00 00 00 02 9A 81 + 39 01 00 00 00 00 02 9B 03 + 39 01 00 00 00 00 02 9C 00 + 39 01 00 00 00 00 02 9D 00 + 39 01 00 00 00 00 02 9E 00 + + 39 01 00 00 00 00 02 FF 27 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 68 + 39 01 00 00 00 00 02 20 81 + 39 01 00 00 00 00 02 21 EA + 39 01 00 00 00 00 02 25 82 + 39 01 00 00 00 00 02 26 1F + 39 01 00 00 00 00 02 6E 00 + 39 01 00 00 00 00 02 6F 00 + 39 01 00 00 00 00 02 70 00 + 39 01 00 00 00 00 02 71 00 + 39 01 00 00 00 00 02 72 00 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 00 00 02 76 00 + 39 01 00 00 00 00 02 77 00 + 39 01 00 00 00 00 02 7D 09 + 39 01 00 00 00 00 02 7E 67 + 39 01 00 00 00 00 02 80 23 + 39 01 00 00 00 00 02 82 09 + 39 01 00 00 00 00 02 83 67 + 39 01 00 00 00 00 02 88 01 + 39 01 00 00 00 00 02 89 10 + 39 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00 02 2F 04 + 39 01 00 00 00 00 02 30 54 + 39 01 00 00 00 00 02 33 04 + 39 01 00 00 00 00 02 34 E6 + 39 01 00 00 00 00 02 35 32 + 39 01 00 00 00 00 02 36 02 + 39 01 00 00 00 00 02 37 E1 + 39 01 00 00 00 00 02 38 36 + 39 01 00 00 00 00 02 39 FE + 39 01 00 00 00 00 02 3A 14 + 39 01 00 00 00 00 02 46 40 + 39 01 00 00 00 00 02 47 02 + 39 01 00 00 00 00 02 4A F0 + 39 01 00 00 00 00 02 4E 0F + 39 01 00 00 00 00 02 4F 65 + 39 01 00 00 00 00 02 52 0F + 39 01 00 00 00 00 02 53 39 + 39 01 00 00 00 00 02 54 14 + 39 01 00 00 00 00 02 56 36 + 39 01 00 00 00 00 02 57 7E + 39 01 00 00 00 00 02 58 7E + 39 01 00 00 00 00 02 59 7E + 39 01 00 00 00 00 02 60 80 + 39 01 00 00 00 00 02 61 C9 + 39 01 00 00 00 00 02 62 03 + 39 01 00 00 00 00 02 63 FB + 39 01 00 00 00 00 02 64 03 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 66 01 + 39 01 00 00 00 00 02 67 04 + 39 01 00 00 00 00 02 68 91 + 39 01 00 00 00 00 02 6A 19 + 39 01 00 00 00 00 02 6B CB + 39 01 00 00 00 00 02 6C 20 + 39 01 00 00 00 00 02 6D E5 + 39 01 00 00 00 00 02 6E C8 + 39 01 00 00 00 00 02 6F 22 + 39 01 00 00 00 00 02 70 E3 + 39 01 00 00 00 00 02 71 04 + 39 01 00 00 00 00 02 7A 07 + 39 01 00 00 00 00 02 7B 40 + 39 01 00 00 00 00 02 7D 01 + 39 01 00 00 00 00 02 7F 2C + 39 01 00 00 00 00 02 83 0F + 39 01 00 00 00 00 02 84 65 + 39 01 00 00 00 00 02 87 0F + 39 01 00 00 00 00 02 88 39 + 39 01 00 00 00 00 02 89 14 + 39 01 00 00 00 00 02 8B 36 + 39 01 00 00 00 00 02 8C 39 + 39 01 00 00 00 00 02 8D 39 + 39 01 00 00 00 00 02 8E 39 + 39 01 00 00 00 00 02 95 80 + 39 01 00 00 00 00 02 96 FD + 39 01 00 00 00 00 02 97 14 + 39 01 00 00 00 00 02 98 B3 + 39 01 00 00 00 00 02 99 01 + 39 01 00 00 00 00 02 9A 08 + 39 01 00 00 00 00 02 9B 02 + 39 01 00 00 00 00 02 9C 4C + 39 01 00 00 00 00 02 9D BC + 39 01 00 00 00 00 02 9F AC + 39 01 00 00 00 00 02 A0 FF + 39 01 00 00 00 00 02 A2 44 + 39 01 00 00 00 00 02 A3 78 + 39 01 00 00 00 00 02 A4 F8 + 39 01 00 00 00 00 02 A5 4A + 39 01 00 00 00 00 02 A6 72 + 39 01 00 00 00 00 02 A7 4C + + 39 01 00 00 00 00 02 FF 2C + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 00 02 + 39 01 00 00 00 00 02 01 02 + 39 01 00 00 00 00 02 02 02 + 39 01 00 00 00 00 02 03 16 + 39 01 00 00 00 00 02 04 16 + 39 01 00 00 00 00 02 05 16 + 39 01 00 00 00 00 02 0D 1F + 39 01 00 00 00 00 02 0E 1F + 39 01 00 00 00 00 02 16 1B + 39 01 00 00 00 00 02 17 4B + 39 01 00 00 00 00 02 18 4B + 39 01 00 00 00 00 02 19 4B + 39 01 00 00 00 00 02 2A 03 + 39 01 00 00 00 00 02 4D 16 + 39 01 00 00 00 00 02 4E 02 + 39 01 00 00 00 00 02 4F 2F + 39 01 00 00 00 00 02 53 02 + 39 01 00 00 00 00 02 54 02 + 39 01 00 00 00 00 02 55 02 + 39 01 00 00 00 00 02 56 0E + 39 01 00 00 00 00 02 58 0E + 39 01 00 00 00 00 02 59 0E + 39 01 00 00 00 00 02 61 1F + 39 01 00 00 00 00 02 62 1F + 39 01 00 00 00 00 02 6A 14 + 39 01 00 00 00 00 02 6B 34 + 39 01 00 00 00 00 02 6C 34 + 39 01 00 00 00 00 02 6D 34 + 39 01 00 00 00 00 02 7E 03 + 39 01 00 00 00 00 02 9D 0E + 39 01 00 00 00 00 02 9E 02 + 39 01 00 00 00 00 02 9F 02 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3 + 39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E + 39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F + 39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1 + 39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28 + 39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63 + 39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3 + 39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26 + 39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61 + 39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00 + + 39 01 00 00 00 00 02 C6 00 + 39 01 00 00 00 00 02 C7 00 + 39 01 00 00 00 00 02 C8 00 + 39 01 00 00 00 00 02 C9 00 + 39 01 00 00 00 00 02 CA 00 + + 39 01 00 00 00 00 02 CB 00 + 39 01 00 00 00 00 02 CC 00 + 39 01 00 00 00 00 02 CD 00 + 39 01 00 00 00 00 02 CE 00 + 39 01 00 00 00 00 02 CF 00 + + 39 01 00 00 00 00 02 D0 00 + 39 01 00 00 00 00 02 D1 00 + 39 01 00 00 00 00 02 D2 00 + 39 01 00 00 00 00 02 D3 00 + 39 01 00 00 00 00 02 D4 00 + + 39 01 00 00 00 00 02 D5 00 + 39 01 00 00 00 00 02 D6 00 + 39 01 00 00 00 00 02 D7 00 + 39 01 00 00 00 00 02 D8 00 + 39 01 00 00 00 00 02 D9 00 + + 39 01 00 00 00 00 02 DA 00 + 39 01 00 00 00 00 02 DB 00 + 39 01 00 00 00 00 02 DC 00 + 39 01 00 00 00 00 02 DD 00 + 39 01 00 00 00 00 02 DE 00 + + 39 01 00 00 00 00 02 DF 00 + 39 01 00 00 00 00 02 E0 00 + 39 01 00 00 00 00 02 E1 00 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 E3 00 + + 39 01 00 00 00 00 02 E4 00 + 39 01 00 00 00 00 02 E5 00 + 39 01 00 00 00 00 02 E6 00 + 39 01 00 00 00 00 02 E7 00 + 39 01 00 00 00 00 02 E8 00 + 39 01 00 00 00 00 02 E9 00 + + + 39 01 00 00 00 00 02 FF 21 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3 + 39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E + 39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F + 39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1 + 39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28 + 39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63 + 39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3 + 39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26 + 39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61 + 39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00 + + 39 01 00 00 00 00 02 FF E0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 35 82 + 39 01 00 00 00 00 02 85 32 + + 39 01 00 00 00 00 02 FF F0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 1C 01 + 39 01 00 00 00 00 02 33 01 + 39 01 00 00 00 00 02 5A 00 + + 39 01 00 00 00 00 02 FF D0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 53 22 + 39 01 00 00 00 00 02 54 02 + + 39 01 00 00 00 00 02 FF C0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 9C 11 + 39 01 00 00 00 00 02 9D 11 + + 39 01 00 00 00 00 02 FF 2B + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B7 0A + 39 01 00 00 00 00 02 B8 1C + 39 01 00 00 00 00 02 C0 01 + + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 35 01 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 28 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 3f1debe20f9b..5b31658f12e6 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -1,5 +1,6 @@ #include "dsi-panel-nt36672e-fhd-plus-144-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" @@ -170,6 +171,18 @@ }; }; +&dsi_nt36672e_fhd_plus_90hz_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 + 06 07 02 04 00 16 16]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 26f690f77de3..1b1fcd8a6792 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -16,6 +16,14 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_nt36672e_fhd_plus_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; From a79f539b3764b23765b795c2a842ef241aae8696 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Thu, 22 Apr 2021 13:13:54 +0530 Subject: [PATCH 237/327] ARM: dts: msm: Add display support for yupik IDP with PM7250B Add display support for yupik IDP variant with PM7250B replacing PM7325B. Change-Id: I4275a099fc488648027a7f68cd6655433af924ba --- display/yupik-sde-display-common.dtsi | 15 +++++ display/yupik-sde-display-idp-pm7250b.dtsi | 77 ++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 display/yupik-sde-display-idp-pm7250b.dtsi diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 3f1debe20f9b..7b598d850195 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -114,6 +114,21 @@ }; }; + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; diff --git a/display/yupik-sde-display-idp-pm7250b.dtsi b/display/yupik-sde-display-idp-pm7250b.dtsi new file mode 100644 index 000000000000..4fe3bd0a54a6 --- /dev/null +++ b/display/yupik-sde-display-idp-pm7250b.dtsi @@ -0,0 +1,77 @@ +#include "yupik-sde-display.dtsi" + +&pm7250b_gpios { + disp_lcd_bias_en { + disp_lcd_bias_en_default: disp_lcd_bias_en_default { + pins = "gpio2"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&pm8350c_gpios { + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio8"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>; + pinctrl-2 = <&lcd_backlight_ctrl_default>; + + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-en-gpio = <&pm7250b_gpios 2 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-en-gpio = <&pm7250b_gpios 2 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-en-gpio = <&pm7250b_gpios 2 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + From 33b27c7b90443ef66a962d210f3f995a444c9a94 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Sun, 18 Apr 2021 14:17:42 +0530 Subject: [PATCH 238/327] ARM: dts: msm: Add display support for pm6125 platform of Holi This change adds display nodes for MTP & CDP platforms of the Holi target with PM6125 PMIC. Change-Id: I97725d27dc97c2fed7040735ef1ef16d047a67b6 --- display/holi-sde-display-atp.dtsi | 13 ++++ display/holi-sde-display-cdp-pm6125.dtsi | 75 ++++++++++++++++++++++++ display/holi-sde-display-cdp.dtsi | 13 ++++ display/holi-sde-display-common.dtsi | 25 ++++++++ display/holi-sde-display-mtp-pm6125.dtsi | 75 ++++++++++++++++++++++++ display/holi-sde-display-mtp.dtsi | 13 ++++ display/holi-sde-display-qrd.dtsi | 13 ++++ display/holi-sde-display.dtsi | 13 ---- 8 files changed, 227 insertions(+), 13 deletions(-) create mode 100644 display/holi-sde-display-cdp-pm6125.dtsi create mode 100644 display/holi-sde-display-mtp-pm6125.dtsi diff --git a/display/holi-sde-display-atp.dtsi b/display/holi-sde-display-atp.dtsi index 50e6d5d948d1..5c9cca798fbe 100644 --- a/display/holi-sde-display-atp.dtsi +++ b/display/holi-sde-display-atp.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi new file mode 100644 index 000000000000..8bb2a7fb3e8b --- /dev/null +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -0,0 +1,75 @@ +#include "holi-sde-display.dtsi" + +&pmr735a_gpios { + disp_pins { + disp_pins_reset: disp_pins_reset { + pins = "gpio2"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 24 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&sde_dsi { + vddio-supply = <&L13A>; + avdd-supply = <&display_panel_avdd>; + + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-0 = <&sde_te_active &disp_pins_reset>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; diff --git a/display/holi-sde-display-cdp.dtsi b/display/holi-sde-display-cdp.dtsi index 405d99cc5725..520ee6175071 100644 --- a/display/holi-sde-display-cdp.dtsi +++ b/display/holi-sde-display-cdp.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index b4d0bf1d8d88..18078ece180f 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -138,6 +138,31 @@ }; }; + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #size-cells = <0>; + #address-cells = <1>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi new file mode 100644 index 000000000000..8bb2a7fb3e8b --- /dev/null +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -0,0 +1,75 @@ +#include "holi-sde-display.dtsi" + +&pmr735a_gpios { + disp_pins { + disp_pins_reset: disp_pins_reset { + pins = "gpio2"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 24 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&sde_dsi { + vddio-supply = <&L13A>; + avdd-supply = <&display_panel_avdd>; + + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-0 = <&sde_te_active &disp_pins_reset>; + qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; diff --git a/display/holi-sde-display-mtp.dtsi b/display/holi-sde-display-mtp.dtsi index 50e6d5d948d1..5c9cca798fbe 100644 --- a/display/holi-sde-display-mtp.dtsi +++ b/display/holi-sde-display-mtp.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-qrd.dtsi b/display/holi-sde-display-qrd.dtsi index f7f1aae2c61d..dc34ad3fea52 100644 --- a/display/holi-sde-display-qrd.dtsi +++ b/display/holi-sde-display-qrd.dtsi @@ -1,5 +1,18 @@ #include "holi-sde-display.dtsi" +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + &dsi_panel_pwr_supply { qcom,panel-supply-entry@0 { qcom,supply-min-voltage = <1860000>; diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 248d6f4e80f6..19d406208854 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,18 +1,5 @@ #include "holi-sde-display-common.dtsi" -&pm6150l_gpios { - disp_pins { - disp_pins_default: disp_pins_default { - pins = "gpio9"; - function = "func1"; - qcom,drive-strength = <2>; - power-source = <1>; - bias-disable; - output-low; - }; - }; -}; - &sde_dsi { clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, From 14a9e4ccbd4799337db8bd7eaee981a7f3aba4f7 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 19 May 2021 12:37:06 +0530 Subject: [PATCH 239/327] ARM: dts: msm: Add display nodes for Blair target Add display DT nodes for Blair target. Change-Id: I858c76262a44fa836bb61348ad82074c7ade381a --- display/blair-sde-display-cdp.dtsi | 88 ++++++++++++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 1 + display/blair-sde.dtsi | 24 ++++++++ display/holi-sde-display-common.dtsi | 15 +++++ 4 files changed, 128 insertions(+) create mode 100644 display/blair-sde-display-cdp.dtsi create mode 100644 display/blair-sde-display-mtp.dtsi create mode 100644 display/blair-sde.dtsi diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi new file mode 100644 index 000000000000..2ed34724f9df --- /dev/null +++ b/display/blair-sde-display-cdp.dtsi @@ -0,0 +1,88 @@ +/* Should extend holi-sde-display-cdp-pm6125.dtsi */ + +&tlmm { + pmx_sde_bias_en: pmx_sde_bias_en { + lcd_bias_en_active: lcd_bias_en_active { + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + lcd_bias_en_suspend: lcd_bias_en_suspend { + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; + +&pm6125_gpios { + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio8"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; +}; + +&sde_dsi { + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-0 = <&sde_te_active &disp_pins_reset &lcd_bias_en_active>; + pinctrl-1 = <&sde_te_suspend &lcd_bias_en_suspend>; + pinctrl-2 = <&lcd_backlight_ctrl_default>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; +}; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; +}; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi new file mode 100644 index 000000000000..11ff69c6b5a2 --- /dev/null +++ b/display/blair-sde-display-mtp.dtsi @@ -0,0 +1 @@ +/* Should extend holi-sde-display-mtp-pm6125.dtsi */ diff --git a/display/blair-sde.dtsi b/display/blair-sde.dtsi new file mode 100644 index 000000000000..1a5e4b575150 --- /dev/null +++ b/display/blair-sde.dtsi @@ -0,0 +1,24 @@ +#include "holi-sde.dtsi" + +&mdss_dsi0 { + vdda-1p2-supply = <&L4A>; +}; + +&mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v4.1"; + reg = <0xae94400 0x800>, + <0xae94900 0x27c>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; + pll-label = "dsi_pll_5nm"; + + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + + vdda-0p9-supply = <&S1E_LEVEL>; +}; + diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index 18078ece180f..b9bd7bf572f0 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -163,6 +163,21 @@ }; }; + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #size-cells = <0>; + #address-cells = <1>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; From f40d17f5cad073477ad7e0ef6af98ac41c3fddb4 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Wed, 19 May 2021 01:18:19 +0530 Subject: [PATCH 240/327] ARM: dts: msm: add display support for monaco IDP Add panel dtsi for RM69090 truly 1.78" amoled panel. Change-Id: Ifca7f108a6578062f3b186d37a6a9db4187ada34 --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 74 ++++ display/monaco-sde-display.dtsi | 134 ++++++++ display/monaco-sde.dtsi | 318 ++++++++++++++++++ 3 files changed, 526 insertions(+) create mode 100644 display/dsi-panel-rm69090-amoled-178-cmd.dtsi create mode 100644 display/monaco-sde-display.dtsi create mode 100644 display/monaco-sde.dtsi diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi new file mode 100644 index 000000000000..55601b26b6e5 --- /dev/null +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -0,0 +1,74 @@ +&mdss_mdp { + dsi_rm69090_amoled_cmd: qcom,mdss_dsi_rm69090_amoled_178_cmd { + qcom,mdss-dsi-panel-name = + "RM69090 1.78 amoled cmd mode"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <368>; + qcom,mdss-dsi-panel-height = <448>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 01 + 15 01 00 00 00 00 02 6A 03 + 15 01 00 00 00 00 02 FE 00 + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 05 2A 00 10 01 7F + 39 01 00 00 00 00 05 2B 00 00 01 BF + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 40 00 02 29 00 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 15 01 00 00 00 00 02 4F 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi new file mode 100644 index 000000000000..96f16f6bede1 --- /dev/null +++ b/display/monaco-sde-display.dtsi @@ -0,0 +1,134 @@ +#include +#include "dsi-panel-rm69090-amoled-178-cmd.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + /*TODO: check if MDP clock WA is required*/ + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 73 0>; + qcom,panel-te-source = <0>; + vddio-supply = <&L21A>; + qcom,mdp = <&mdss_mdp>; + + qcom,dsi-default-panel = + <&dsi_rm69090_amoled_cmd>; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; + +&dsi_rm69090_amoled_cmd { + qcom,mdss-dsi-t-clk-post = <0x08>; + qcom,mdss-dsi-t-clk-pre = <0x0B>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", /*TODO: check these*/ + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0C 03 03 10 1D 03 + 03 03 02 02 04 0B 08]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi new file mode 100644 index 000000000000..0c61a0fd7c46 --- /dev/null +++ b/display/monaco-sde.dtsi @@ -0,0 +1,318 @@ +#include + +&soc { + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <2700000>; + qcom,sde-max-bw-high-kbps = <2700000>; + qcom,sde-min-core-ib-kbps = <1300000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x00000000 + 0x00000000 0x00000000 0x00000000>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma"; + qcom,sde-limit-ids= <0x1 0x2>; + qcom,sde-limit-values = <0x1 2160>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2700000>, + <0x9 2700000>, + <0x2 2700000>, + <0xa 2700000>, + <0x4 2700000>, + <0xc 2700000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi0_ctrl { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L9A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1312000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v4.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x800>, + <0x5e94900 0x27c>, + <0x5e94200 0x100>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base", "gdsc_base"; + pll-label = "dsi_pll_5nm"; + memory-region = <&dfps_data_memory>; + vdda-0p9-supply = <&L12A>; + /*TODO: check these*/ + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <37550>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; From d028a56a38911ada8407f7efba08ce3600b33fa2 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 24 May 2021 16:48:34 +0530 Subject: [PATCH 241/327] ARM: dts: qcom: add thermal cooling dev property under mdss_mdp on Holi The display connector_init fails if the thermal cooling device property "#cooling-cells" is not present under the mdss_mdp DT node. Earlier this property used to be defined in "-thermal-overlay.dtsi" file, because of this, sometimes it gets missed. Looking at the code of the sde_connector, it appears the "#cooling-cells" is a mandatory property of the mdss_mdp. Add this property under mdss_mdp DT node. Change-Id: Icd4b076e0c718327df762f0dae10347162fa2299 --- display/holi-sde.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/holi-sde.dtsi b/display/holi-sde.dtsi index 6b9b4af31c3f..17db671487d1 100644 --- a/display/holi-sde.dtsi +++ b/display/holi-sde.dtsi @@ -88,6 +88,9 @@ }; &mdss_mdp { + /* Enable thermal cooling device */ + #cooling-cells = <2>; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, From 974f4ecc2c4e3f8594f144c627a5f9a3eb02c8d2 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 13 May 2021 16:57:38 +0530 Subject: [PATCH 242/327] ARM: dts: msm: Add NT36672E 144hz C-phy Video Mode Panel on Yupik IDP Add NT36672E 144fps fhd plus Video mode C-Phy panel support on yupik platform. Change-Id: I186eb8b9d92b873781a2ae2652b7c47c95c758c3 --- ...el-nt36672e-fhd-plus-144hz-video-cphy.dtsi | 430 ++++++++++++++++++ display/yupik-sde-display-common.dtsi | 14 + display/yupik-sde-display-idp.dtsi | 8 + 3 files changed, 452 insertions(+) create mode 100644 display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi diff --git a/display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi b/display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi new file mode 100644 index 000000000000..d569a87561c8 --- /dev/null +++ b/display/dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi @@ -0,0 +1,430 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_144hz_video_cphy: qcom,mdss_dsi_nt36672e_fhd_plus_cphy_144hz_video { + qcom,mdss-dsi-panel-name = + "nt36672e 144Hz fhd plus video mode cphy panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750 + 39800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <80>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <54>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 39 01 00 00 00 00 03 C2 1B A0 + 39 01 00 00 00 00 02 E9 01 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 66 + 39 01 00 00 00 00 02 06 40 + 39 01 00 00 00 00 02 07 38 + 39 01 00 00 00 00 02 18 77 + 39 01 00 00 00 00 02 69 91 + 39 01 00 00 00 00 02 95 D1 + 39 01 00 00 00 00 02 96 D1 + 39 01 00 00 00 00 02 F2 65 + 39 01 00 00 00 00 02 F3 74 + 39 01 00 00 00 00 02 F4 65 + 39 01 00 00 00 00 02 F5 74 + 39 01 00 00 00 00 02 F6 65 + 39 01 00 00 00 00 02 F7 74 + 39 01 00 00 00 00 02 F8 65 + 39 01 00 00 00 00 02 F9 74 + + 39 01 00 00 00 00 02 89 15 + 39 01 00 00 00 00 02 8A 15 + 39 01 00 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C9 + 39 01 00 00 00 00 02 6C 1F + 39 01 00 00 00 00 02 6D E3 + 39 01 00 00 00 00 02 6E C6 + 39 01 00 00 00 00 02 6F 20 + 39 01 00 00 00 00 02 70 E2 + 39 01 00 00 00 00 02 71 04 + 39 01 00 00 00 00 02 7A 04 + 39 01 00 00 00 00 02 7B 40 + 39 01 00 00 00 00 02 7C 01 + 39 01 00 00 00 00 02 7D 01 + 39 01 00 00 00 00 02 7F E0 + 39 01 00 00 00 00 02 83 0F + 39 01 00 00 00 00 02 84 C5 + 39 01 00 00 00 00 02 87 0F + 39 01 00 00 00 00 02 88 42 + 39 01 00 00 00 00 02 89 14 + 39 01 00 00 00 00 02 8B 36 + 39 01 00 00 00 00 02 8C 33 + 39 01 00 00 00 00 02 8D 33 + 39 01 00 00 00 00 02 8E 33 + 39 01 00 00 00 00 02 95 80 + 39 01 00 00 00 00 02 96 FD + 39 01 00 00 00 00 02 97 19 + 39 01 00 00 00 00 02 98 4A + 39 01 00 00 00 00 02 99 07 + 39 01 00 00 00 00 02 9A 0B + 39 01 00 00 00 00 02 9B 03 + 39 01 00 00 00 00 02 9C 8B + 39 01 00 00 00 00 02 9D FF + 39 01 00 00 00 00 02 9F 8B + 39 01 00 00 00 00 02 A0 FF + 39 01 00 00 00 00 02 A2 4E + 39 01 00 00 00 00 02 A3 01 + 39 01 00 00 00 00 02 A4 F8 + 39 01 00 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9E 04 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 39 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 39 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 39 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 39 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 39 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 39 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 39 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 39 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 39 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + + 39 01 00 00 00 00 02 FF 21 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 E2 00 E9 00 F6 01 01 01 0C 01 15 01 20 01 28 + 39 01 00 00 00 00 11 B1 01 33 01 51 01 6E 01 9A 01 C0 01 FD 02 34 02 35 + 39 01 00 00 00 00 11 B2 02 6B 02 A9 02 D1 03 04 03 25 03 51 03 5F 03 6D + 39 01 00 00 00 00 0F B3 03 7D 03 90 03 A7 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B4 00 AA 00 B3 00 C4 00 D4 00 E2 00 F0 00 FC 01 08 + 39 01 00 00 00 00 11 B5 01 12 01 39 01 58 01 8C 01 B5 01 F7 02 30 02 31 + 39 01 00 00 00 00 11 B6 02 68 02 A6 02 CE 03 01 03 23 03 4E 03 5C 03 6A + 39 01 00 00 00 00 0F B7 03 7B 03 8E 03 A5 03 BB 03 D4 03 D8 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 20 00 47 00 65 00 85 00 99 00 AD 00 C0 + 39 01 00 00 00 00 11 B9 00 D2 01 06 01 30 01 70 01 9F 01 E8 02 25 02 26 + 39 01 00 00 00 00 11 BA 02 5F 02 9F 02 C7 02 FD 03 20 03 52 03 63 03 67 + 39 01 00 00 00 00 0F BB 03 78 03 8B 03 A3 03 B9 03 D4 03 D8 00 00 + + 39 01 00 00 00 00 02 FF E0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 35 82 + + 39 01 00 00 00 00 02 FF F0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 5A 00 + 39 01 00 00 00 00 02 D2 52 + 39 01 00 00 00 00 02 9F 12 + + 39 01 00 00 00 00 02 FF D0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 53 22 + 39 01 00 00 00 00 02 54 02 + + 39 01 00 00 00 00 02 FF C0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 9C 11 + 39 01 00 00 00 00 02 9D 11 + + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + + 39 01 00 00 00 00 02 35 01 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 32 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index f04cb048c16c..dc79e9e90769 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -2,6 +2,7 @@ #include "dsi-panel-nt36672e-fhd-plus-120-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-120hz-cmd-cphy.dtsi" @@ -210,6 +211,19 @@ }; }; +&dsi_nt36672e_fhd_plus_144hz_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 22 1F 06 + 19 07 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_r66451_amoled_60hz_cmd_cphy { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; diff --git a/display/yupik-sde-display-idp.dtsi b/display/yupik-sde-display-idp.dtsi index 1b1fcd8a6792..942d2f1a263b 100644 --- a/display/yupik-sde-display-idp.dtsi +++ b/display/yupik-sde-display-idp.dtsi @@ -32,6 +32,14 @@ qcom,platform-reset-gpio = <&tlmm 44 0>; }; +&dsi_nt36672e_fhd_plus_144hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; +}; + &dsi_r66451_amoled_90hz_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_amoled>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From f90911f35b5c9927265c3fef9e081d346165195d Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 27 May 2021 21:00:47 +0530 Subject: [PATCH 243/327] ARM: dts: msm: Fix backlight pinctrl config for Blair target Fix pinctrl config of LCD backlight PWM enable pin for Blair CDP target. Change-Id: I3091cc4698d69553b24da25608487b28170ff665 --- display/blair-sde-display-cdp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 2ed34724f9df..4ebd9f1a8942 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -36,10 +36,10 @@ pins = "gpio8"; function = "func1"; input-disable; - output-enable; + output-low; bias-disable; - power-source = <1>; /* 1.8V */ - qcom,drive-strength = <2>; + power-source = <0>; + qcom,drive-strength = <3>; }; }; }; From 926c1e5659eaeac52ef414a836f02f01c632815d Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 27 May 2021 19:13:10 +0530 Subject: [PATCH 244/327] ARM: dts: msm: Fix backlight pinctrl config for yupik IDP with PM7250B Fix pinctrl config of lcd_backlight_ctrl_default for yupik IDP with PM7250B. Change-Id: I3acbb2802dfca11186b0eb1936ac52a79d0b8282 --- display/yupik-sde-display-idp-pm7250b.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/display/yupik-sde-display-idp-pm7250b.dtsi b/display/yupik-sde-display-idp-pm7250b.dtsi index 4fe3bd0a54a6..cfe5719a65e6 100644 --- a/display/yupik-sde-display-idp-pm7250b.dtsi +++ b/display/yupik-sde-display-idp-pm7250b.dtsi @@ -20,10 +20,10 @@ pins = "gpio8"; function = "func1"; input-disable; - output-enable; + output-low; bias-disable; - power-source = <1>; /* 1.8V */ - qcom,drive-strength = <2>; + power-source = <0>; + qcom,drive-strength = <3>; }; }; }; From 1e20027096d20b609c8b1da08e564e87c11be392 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Fri, 21 May 2021 13:11:26 +0800 Subject: [PATCH 245/327] ARM: dts: msm: add panel support for qrd pm6125 platform of Holi Add panel support for this qrd device. Change-Id: I17ec0619d69a340e4bb79361ab87b05159a77ce0 --- display/holi-sde-display-qrd-pm6125.dtsi | 121 +++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 display/holi-sde-display-qrd-pm6125.dtsi diff --git a/display/holi-sde-display-qrd-pm6125.dtsi b/display/holi-sde-display-qrd-pm6125.dtsi new file mode 100644 index 000000000000..6ed7c6ad2e0b --- /dev/null +++ b/display/holi-sde-display-qrd-pm6125.dtsi @@ -0,0 +1,121 @@ +#include "holi-sde-display.dtsi" + +&pmr735a_gpios { + disp_pins { + disp_pins_reset: disp_pins_reset { + pins = "gpio2"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; + +&tlmm { + display_panel_avdd_default: display_panel_avdd_default { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 24 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&sde_dsi { + vddio-supply = <&L13A>; + avdd-supply = <&display_panel_avdd>; + + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-0 = <&sde_te_active &disp_pins_reset>; + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; From ab5dbedad3c7817b3e48b44fc487c67fcbea8adf Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 4 Jun 2021 22:33:30 +0530 Subject: [PATCH 246/327] ARM: dts: msm: Update dsi phy addresses and timings for Blair target Update dsi phy addresses and phy timings of amoled panel for the Blair target as per 6nm-FF. Change-Id: I366d26b0939f9b7fe969b6c503adc1c3c0574ada --- display/blair-sde-display-cdp.dtsi | 18 ++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 18 ++++++++++++++++++ display/blair-sde.dtsi | 8 ++++---- 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 4ebd9f1a8942..7c64312e4db0 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -51,6 +51,24 @@ pinctrl-2 = <&lcd_backlight_ctrl_default>; }; +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index 11ff69c6b5a2..e5e55997454a 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1 +1,19 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ + +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; diff --git a/display/blair-sde.dtsi b/display/blair-sde.dtsi index 1a5e4b575150..dc45549650c4 100644 --- a/display/blair-sde.dtsi +++ b/display/blair-sde.dtsi @@ -6,10 +6,10 @@ &mdss_dsi_phy0 { compatible = "qcom,dsi-phy-v4.1"; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; + reg = <0x05e94400 0x800>, + <0x05e94900 0x264>, + <0x05f01004 0x8>, + <0x05e94200 0x100>; reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; pll-label = "dsi_pll_5nm"; From 04b36a3c54801a4497baa1099cf2092eff876fe7 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Tue, 13 Apr 2021 15:37:56 +0800 Subject: [PATCH 247/327] bindings: Documentation: add documentation for qpic display Add the documentation for configuring the QPIC display block. Change-Id: I03a0f9f4754b8dfe18165ed7c00a9b12de1c9f7a --- bindings/qcom-qpic-lcdc.txt | 69 +++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 bindings/qcom-qpic-lcdc.txt diff --git a/bindings/qcom-qpic-lcdc.txt b/bindings/qcom-qpic-lcdc.txt new file mode 100644 index 000000000000..e6ee71c512e1 --- /dev/null +++ b/bindings/qcom-qpic-lcdc.txt @@ -0,0 +1,69 @@ +Qualcomm Technologies, Inc. QPIC display + +QPIC LCDC Controller: +Mandatory properties: +- compatible: + * "qcom,mdss_qpic" +- reg: Physical base address and length of registers of controller +- reg-names: The names of register regions. The following regions are required: + * "qpic_base" +- interrupts: The interrupt signal from the QPIC LCDC block. +- clocks: It contains list of required clock. List contain core clock. +- clock-names: Must contain "core" for the core clock and "aon" for the + always on clock. +- qcom,panel-name: The panel peripheral name "string" which is used by QPIC display. +- qcom.rst-gpio: Specifies the gpio used to reset panel. +- qcom,cs-gpio: Specifies the gpio used for LCDC chip select signal. +- qcom,ad8-gpio: Specifies the gpio used for LCDC data pin 8. +- qcom,panel-te-gpio: Specifies the gpio used for TE. + +Optional properties: +- vdd-supply: phandle to vdd regulator device node +- vdda-supply: phandle to vdda regulator device node +- pinctrl-names: the pin control state names; should contain "default" +- pinctrl-0: the default pinctrl state (active) +- pinctrl-n: the "sleep" pinctrl state +- qcom,bl-gpio: Specifies the gpio used to enable backlight. +- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for +below optional properties: + - qcom,msm-bus,name + - qcom,msm-bus,num-cases + - qcom,msm-bus,active-only + - qcom,msm-bus,num-paths + - qcom,msm-bus,vectors-KBps + + +Example: + mdss_qpic: qcom,msm_qpic@1b00000 { + compatible = "qcom,mdss_qpic"; + reg = <0x1b00000 0x24000>; + reg-names = "qpic_base"; + interrupts = <0 251 0>; + + qcom,msm-bus,name = "mdss_qpic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <91 512 0 0>, + /* Voting for max b/w on PNOC bus for now */ + <91 512 400000 800000>; + + panel-name = "ili_qvga"; + vdd-supply = <&pmxprairie_l6>; + + qcom,rst-gpio = <&tlmm 23 0>; + qcom,cs-gpio = <&tlmm 21 0>; + qcom,ad8-gpio = <&tlmm 20 0>; + qcom,te-gpio = <&tlmm 22 0>; + qcom,bl-gpio = <&pmxprairie_gpios 1 0>; + + clocks = <&clock_rpmh RPMH_QPIC_CLK>; + clock-names = "core_clk"; + + pinctrl-names= "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_cs_active &mdss_te_active + &mdss_rs_active &mdss_ad_active>; + pinctrl-1 = <&mdss_cs_sleep &mdss_te_sleep + &mdss_rs_sleep &mdss_ad_sleep>; + }; From 8cb47b462ea9eaa145d62624be489271ea6cf58e Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Fri, 19 Mar 2021 17:12:58 +0800 Subject: [PATCH 248/327] ARM: dts: msm: add support for QPIC display Add support for QPIC display and ili panel for MDM project. Change-Id: Ia7a4d47d62333867264e4b29fbaa8ead0ab0fe25 --- display/sdxlemur-qpic-display.dtsi | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 display/sdxlemur-qpic-display.dtsi diff --git a/display/sdxlemur-qpic-display.dtsi b/display/sdxlemur-qpic-display.dtsi new file mode 100644 index 000000000000..b6ede6f9fbea --- /dev/null +++ b/display/sdxlemur-qpic-display.dtsi @@ -0,0 +1,40 @@ +&soc { + mdss_qpic: qcom,msm_qpic@1b00000 { + compatible = "qcom,mdss_qpic"; + + reg = <0x1b00000 0x24000>; + reg-names = "qpic_base"; + + interrupts = <0 75 0>; + interrupt-names = "qpic_irq"; + + interconnect-names = "qpic-display-data-bus"; + interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>; + qcom,msm-bus,name = "mdss_qpic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <400000 800000>; + + qcom,panel-name = "ili_qvga"; + vdd-supply = <&pmx65_l6>; + + qcom,rst-gpio = <&tlmm 85 0>; + qcom,cs-gpio = <&tlmm 90 0>; + qcom,ad8-gpio = <&tlmm 89 0>; + qcom,panel-te-gpio = <&tlmm 84 0>; + qcom,panel-bl-gpio = <&tlmm 97 0>; + + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "core_clk"; + + pinctrl-names= "qpic_display_default", "qpic_display_sleep"; + pinctrl-0 = <&qpic_cs_active &qpic_te_active + &qpic_rs_active &qpic_ad_active>; + pinctrl-1 = <&qpic_cs_sleep &qpic_te_sleep + &qpic_rs_sleep &qpic_ad_sleep>; + }; +}; From e8cdab7f8a6ef2baaa283ba2f8255eefc77f46f4 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Tue, 8 Jun 2021 20:19:41 +0530 Subject: [PATCH 249/327] ARM: dts: msm: update clock list for monaco-sde Remove GCC_DISP_AHB_CLK as this is always ON clk and support for this clk was removed in clk driver. Change-Id: I641f6c0a69b2a4395357519e1fe732a74144052a --- display/monaco-sde.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 0c61a0fd7c46..69ddb0a24925 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -31,14 +31,13 @@ "sde_imem_phys"; clocks = - <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_THROTTLE_CORE_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + clock-names = "gcc_bus", "throttle_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; From 4b221658a3355b600af70aeda86e88f1d062d4be Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 9 Jun 2021 15:50:13 +0800 Subject: [PATCH 250/327] ARM: dts: msm: add a new display qrd dtsi for Blair Add a new display dtsi file. Change-Id: I1f02b6d4dfbf71b75feb2cfc3ffdeeccc8eb8de5 --- display/blair-sde-display-qrd.dtsi | 61 ++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 display/blair-sde-display-qrd.dtsi diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi new file mode 100644 index 000000000000..e8d21a2f08c7 --- /dev/null +++ b/display/blair-sde-display-qrd.dtsi @@ -0,0 +1,61 @@ +/* Should extend holi-sde-display-qrd-pm6125.dtsi */ + +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00 1a 17]; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00 1a 17]; + }; + }; +}; + +&dsi_r66451_amoled_90hz_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + }; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + }; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + }; +}; From c0b572c6c6e743f00bb664317d352d7bfd880e62 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 4 Jun 2021 22:33:30 +0530 Subject: [PATCH 251/327] ARM: dts: msm: Update dsi phy addresses and timings for Blair target Update dsi phy addresses and phy timings of amoled panel for the Blair target as per 6nm-FF. Change-Id: I366d26b0939f9b7fe969b6c503adc1c3c0574ada --- display/blair-sde-display-cdp.dtsi | 18 ++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 18 ++++++++++++++++++ display/blair-sde.dtsi | 8 ++++---- 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 4ebd9f1a8942..7c64312e4db0 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -51,6 +51,24 @@ pinctrl-2 = <&lcd_backlight_ctrl_default>; }; +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + &dsi_nt36672e_fhd_plus_60_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index 11ff69c6b5a2..e5e55997454a 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1 +1,19 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ + +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; diff --git a/display/blair-sde.dtsi b/display/blair-sde.dtsi index 1a5e4b575150..dc45549650c4 100644 --- a/display/blair-sde.dtsi +++ b/display/blair-sde.dtsi @@ -6,10 +6,10 @@ &mdss_dsi_phy0 { compatible = "qcom,dsi-phy-v4.1"; - reg = <0xae94400 0x800>, - <0xae94900 0x27c>, - <0xaf03000 0x8>, - <0xae94200 0x100>; + reg = <0x05e94400 0x800>, + <0x05e94900 0x264>, + <0x05f01004 0x8>, + <0x05e94200 0x100>; reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; pll-label = "dsi_pll_5nm"; From 2a1195e26f0ecdd1bffa9b27b42baecc2b2d2a63 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Wed, 9 Jun 2021 15:50:13 +0800 Subject: [PATCH 252/327] ARM: dts: msm: add a new display qrd dtsi for Blair Add a new display dtsi file. Change-Id: I1f02b6d4dfbf71b75feb2cfc3ffdeeccc8eb8de5 --- display/blair-sde-display-qrd.dtsi | 61 ++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 display/blair-sde-display-qrd.dtsi diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi new file mode 100644 index 000000000000..e8d21a2f08c7 --- /dev/null +++ b/display/blair-sde-display-qrd.dtsi @@ -0,0 +1,61 @@ +/* Should extend holi-sde-display-qrd-pm6125.dtsi */ + +&dsi_r66451_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00 1a 17]; + }; + }; +}; + +&dsi_r66451_amoled_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 08 02 04 00 1a 17]; + }; + }; +}; + +&dsi_r66451_amoled_90hz_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + }; +}; + +&dsi_r66451_amoled_90hz_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 + 06 06 02 04 00 15 15]; + }; + }; +}; + +&dsi_r66451_amoled_60hz_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 + 04 03 02 04 00 10 14]; + }; + }; +}; From f983684180883b11052a1dd46f6047035ba169d6 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Tue, 15 Jun 2021 14:44:12 +0530 Subject: [PATCH 253/327] ARM: dts: msm: update lane-config settings for monaco-sde Update the lane config and LDO settings with correct values. Change-Id: I9bf725599abbf6d1850bd658155bc9b4959a84d2 --- display/monaco-sde.dtsi | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 0c61a0fd7c46..cf38e4c839c2 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -46,6 +46,9 @@ sde-vdd-supply = <&mdss_core_gdsc>; + /* Enable thermal cooling device */ + #cooling-cells = <2>; + /* data and reg bus scale settings */ interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, <&bimc MASTER_AMPSS_M0 @@ -287,17 +290,16 @@ pll-label = "dsi_pll_5nm"; memory-region = <&dfps_data_memory>; vdda-0p9-supply = <&L12A>; - /*TODO: check these*/ qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; - qcom,platform-lane-config = [00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 8f]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-en; @@ -308,8 +310,8 @@ qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; + qcom,supply-min-voltage = <904000>; + qcom,supply-max-voltage = <904000>; qcom,supply-enable-load = <37550>; qcom,supply-disable-load = <0>; }; From d076934d6b0960465b541d1d1a5bb6c1f8bbf6fc Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 7 Jun 2021 14:21:57 +0530 Subject: [PATCH 254/327] bindings: Documentation: LP11 insertion between lines feature This change adds documentation for LP11 insertion between command mode mdp packets feature. Change-Id: Icb6fdd14866cb9768cb735597afb9b989bf5d9c8 --- bindings/mdss-dsi-panel.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index de435b32c172..f2554a75ed98 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -612,6 +612,11 @@ Optional properties: panels, at which command DMA needs to be triggered. - qcom,mdss-dsi-dma-schedule-window: An integer value indicates the width of the DMA window during which a DCS command will be triggered for command mode panels +- qcom,mdss-dsi-mdp-idle-ctrl-en: A boolean to enable LP11 insertion after transmission of every line. + This requires command mdp burst mode to be disabled. +- qcom,mdss-dsi-mdp-idle-ctrl-len: An u32 value indicating the number of dsi pclk cycles of idle time + to insert between command mode mdp packets. This time must be long + enough to cover the time link takes to switch between HS to LP11 mode. Required properties for sub-nodes: None Optional properties: From 8608a4b95263c720718e3576e4313f09be8e23c0 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 18 Jun 2021 12:13:39 +0530 Subject: [PATCH 255/327] ARM: dts: msm: add support of sim panel for Blair target Add support of video simulation panel for the Blair target. The Blair display DT includes DT of PM6125 variant of Holi, so this change automatically adds the same support there too. Change-Id: I705d08e87025f9accb9abdecab330d3a20c33e9a --- display/blair-sde-display-cdp.dtsi | 9 +++++++++ display/blair-sde-display-mtp.dtsi | 9 +++++++++ display/holi-sde-display-cdp-pm6125.dtsi | 6 ++++++ display/holi-sde-display-mtp-pm6125.dtsi | 6 ++++++ 4 files changed, 30 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 7c64312e4db0..c22aa8d0b7ae 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -51,6 +51,15 @@ pinctrl-2 = <&lcd_backlight_ctrl_default>; }; +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index e5e55997454a..bec02d25e750 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1,5 +1,14 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index 8bb2a7fb3e8b..4daffd87cf89 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -57,6 +57,12 @@ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi index 8bb2a7fb3e8b..4daffd87cf89 100644 --- a/display/holi-sde-display-mtp-pm6125.dtsi +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -57,6 +57,12 @@ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From 16c4ddeaffbaec2e09c12aaa0d36b4c0c4c9bd5f Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 18 Jun 2021 12:13:39 +0530 Subject: [PATCH 256/327] ARM: dts: msm: add support of sim panel for Blair target Add support of video simulation panel for the Blair target. The Blair display DT includes DT of PM6125 variant of Holi, so this change automatically adds the same support there too. Change-Id: I705d08e87025f9accb9abdecab330d3a20c33e9a --- display/blair-sde-display-cdp.dtsi | 9 +++++++++ display/blair-sde-display-mtp.dtsi | 9 +++++++++ display/holi-sde-display-cdp-pm6125.dtsi | 6 ++++++ display/holi-sde-display-mtp-pm6125.dtsi | 6 ++++++ 4 files changed, 30 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 7c64312e4db0..c22aa8d0b7ae 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -51,6 +51,15 @@ pinctrl-2 = <&lcd_backlight_ctrl_default>; }; +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index e5e55997454a..bec02d25e750 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1,5 +1,14 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_video { qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index 8bb2a7fb3e8b..4daffd87cf89 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -57,6 +57,12 @@ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi index 8bb2a7fb3e8b..4daffd87cf89 100644 --- a/display/holi-sde-display-mtp-pm6125.dtsi +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -57,6 +57,12 @@ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; }; +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + &dsi_rm69299_visionox_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; From bca2f8f839e3feda8f2ef83890bb2d41c20a5206 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Thu, 1 Jul 2021 00:47:22 +0530 Subject: [PATCH 257/327] ARM: dts: msm: update sde qos config for monaco Update safe, danger and qos config for 60fps. Change-Id: I28136c73d2156c128c222ea62549028802a9fb34 --- display/monaco-sde.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 8b595879d446..70f5404675c9 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -140,12 +140,13 @@ /*Pending macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x000000ff 0x00000000 + qcom,sde-danger-lut = <0x000000ff 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; - qcom,sde-safe-lut-linear = <0 0xfff0>; + qcom,sde-safe-lut = <0xfff0 0x0000 0x0000 0x0000 + 0x0000 0x0000>; - qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + qcom,sde-qos-lut-linear = <0x00112222 0x22335777>; qcom,sde-cdp-setting = <1 0>; From 0a998afc76e5e72c0914fc4a3d35ca5618292992 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Sat, 3 Jul 2021 18:21:34 +0530 Subject: [PATCH 258/327] ARM: dts: msm: update tear irq offsets for monaco Add tear irq offset for interface 1. Change-Id: I972627be369a14296b055ce48f96ee3c0384587f --- display/monaco-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 8b595879d446..a7b33e6e4ae6 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -82,6 +82,7 @@ qcom,sde-intf-off = <0x0 0x6b800>; qcom,sde-intf-size = <0x2b8>; qcom,sde-intf-type = "none", "dsi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800>; qcom,sde-pp-off = <0x71000>; qcom,sde-pp-size = <0xd4>; From 9559dce593161724cb1c88326202e59097d1c85e Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Mon, 5 Jul 2021 18:28:07 +0530 Subject: [PATCH 259/327] ARM: dts: msm: add list-cells property for mdp node Add list-cells property for mdp device node. Which is needed to populate parent device node for rotator device. Change-Id: I679343160c81f6047cb1a3ff207cd386a0f31580 --- display/holi-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/holi-sde-common.dtsi b/display/holi-sde-common.dtsi index 3e49e2ac9420..8cf5b56c7c9f 100644 --- a/display/holi-sde-common.dtsi +++ b/display/holi-sde-common.dtsi @@ -20,6 +20,7 @@ #interrupt-cells = <1>; #power-domain-cells = <0>; + #list-cells = <1>; /* hw blocks */ qcom,sde-off = <0x1000>; From a8080985235e7cbc7672c6025e371d6dd409894e Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 8 Jul 2021 17:23:47 +0530 Subject: [PATCH 260/327] ARM: dts: msm: update supply-min-voltage of dsi phy supply for Blair MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In Blair target, the MX Rail supports till SVSL1 mode whereas in Holi target it’s Nominal. Change the qcom,supply-min-voltage of the dsi phy 0p9 power supply to SVSL1. Change-Id: If6bfe3021f27ce844783b586b42ef0edb7db157f --- display/blair-sde.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/display/blair-sde.dtsi b/display/blair-sde.dtsi index dc45549650c4..ba11d88339bc 100644 --- a/display/blair-sde.dtsi +++ b/display/blair-sde.dtsi @@ -20,5 +20,21 @@ 00 00 8a 8a]; vdda-0p9-supply = <&S1E_LEVEL>; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; From 8d1ee4be470729544b7c4d1ef8f64766085ff983 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Tue, 13 Jul 2021 22:14:07 +0530 Subject: [PATCH 261/327] ARM: dts: msm: Enable NT36672E D-PHY LCD panel for Blair target Enable NT36672E 60/120/144fps D-PHY fhd plus video mode display panel support for the Blair target. Change-Id: Ie5e69943f7b7984f4b625372ce91a6555a1f2467 --- display/blair-sde-display-cdp.dtsi | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index c22aa8d0b7ae..9926d84935a3 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -88,6 +88,20 @@ qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; qcom,platform-en-gpio = <&tlmm 47 0>; qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 + 0a 09 02 04 00 1f 19]; + }; + }; }; &dsi_nt36672e_fhd_plus_120_video { @@ -100,6 +114,20 @@ qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; qcom,platform-en-gpio = <&tlmm 47 0>; qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 + 08 08 02 04 00 1b 18]; + }; + }; }; &dsi_nt36672e_fhd_plus_144_video { @@ -112,4 +140,18 @@ qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; qcom,platform-en-gpio = <&tlmm 47 0>; qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 08 02 04 00 1c 18]; + }; + }; }; From ccde9200c253511a1ee14f43917aa7a8492bcc54 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Tue, 13 Jul 2021 22:16:51 +0530 Subject: [PATCH 262/327] ARM: dts: msm: Enable NT36672E C-PHY LCD panel for Blair target Enable NT36672E 144fps C-PHY fhd plus video mode display panel support for the Blair target. Change-Id: Ife56a47baec80b5580f9820f1a7ff689af7bc26b --- display/blair-sde-display-cdp.dtsi | 49 ++++++++++++++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 19 ++++++++++++ 2 files changed, 68 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 9926d84935a3..cad3a0ad1a34 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -1,4 +1,6 @@ /* Should extend holi-sde-display-cdp-pm6125.dtsi */ +#include +#include "dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi" &tlmm { pmx_sde_bias_en: pmx_sde_bias_en { @@ -45,6 +47,22 @@ }; &sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; pinctrl-0 = <&sde_te_active &disp_pins_reset &lcd_bias_en_active>; pinctrl-1 = <&sde_te_suspend &lcd_bias_en_suspend>; @@ -155,3 +173,34 @@ }; }; }; + +&dsi_nt36672e_fhd_plus_144hz_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; + qcom,platform-en-gpio = <&tlmm 47 0>; + qcom,platform-bklight-en-gpio = <&pmr735a_gpios 3 0>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 22 1F 06 + 19 07 02 04 00 00 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index bec02d25e750..f1786f5e53d2 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1,4 +1,23 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; +}; &dsi_sim_vid { qcom,mdss-dsi-display-timings { From 387f098f1b3ca665b2d5634ddcab9b3252396edd Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Tue, 20 Jul 2021 13:12:00 +0530 Subject: [PATCH 263/327] ARM: dts: msm: remove the t-clk-post and t-clk-pre timings from Blair The qcom,mdss-dsi-t-clk-post and qcom,mdss-dsi-t-clk-pre panel properties are not required for DSI ctrl v2.3.0 and above, using DSI phy v4.0.0 and above. As the Blair is reusing the display nodes from the Holi target, these two properties are getting included automatically. If these properties are defined, the DSI ctrl programs the DSI_CLKOUT_TIMING_CTRL register for all the DSI PHY versions, that is not recommended as per the DSI HPG. We don't need these two for the Blair, remove them from Blair CDP and MTP platforms. Change-Id: I81d66c53fabfc389466b0dbf82c8d8678f08868a --- display/blair-sde-display-cdp.dtsi | 21 +++++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 9 +++++++++ 2 files changed, 30 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index cad3a0ad1a34..c373b3910512 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -70,6 +70,9 @@ }; &dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 @@ -79,6 +82,9 @@ }; &dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -88,6 +94,9 @@ }; &dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -114,6 +123,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 @@ -140,6 +152,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 @@ -166,6 +181,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -195,6 +213,9 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 22 1F 06 diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index f1786f5e53d2..bab296d1f4a0 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -20,6 +20,9 @@ }; &dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 @@ -29,6 +32,9 @@ }; &dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -38,6 +44,9 @@ }; &dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 From b4ae932b6165a73f2251c0ba9aeb63dfbd3fa324 Mon Sep 17 00:00:00 2001 From: Yu Wu Date: Tue, 20 Jul 2021 18:34:22 +0800 Subject: [PATCH 264/327] ARM: dts: msm: remove the t-clk-post and t-clk-pre timings for blair QRD The qcom,mdss-dsi-t-clk-post and qcom,mdss-dsi-t-clk-pre panel properties are not required for DSI ctrl v2.3.0 and above, using DSI phy v4.0.0 and above. As the Blair is reusing the display nodes from the Holi target, these two properties are getting included automatically. If these properties are defined, the DSI ctrl programs the DSI_CLKOUT_TIMING_CTRL register for all the DSI PHY versions, that is not recommended as per the DSI HPG. We don't need these two for the Blair, remove them. Change-Id: Ic4e1a3a306e4aa191cd7cb3b6017cd3b2f226e8e --- display/blair-sde-display-qrd.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index e8d21a2f08c7..e12529ae97cf 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -1,6 +1,8 @@ /* Should extend holi-sde-display-qrd-pm6125.dtsi */ &dsi_r66451_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 @@ -20,6 +22,8 @@ }; &dsi_r66451_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 @@ -29,6 +33,8 @@ }; &dsi_r66451_amoled_90hz_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 @@ -43,6 +49,8 @@ }; &dsi_r66451_amoled_90hz_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 @@ -52,6 +60,8 @@ }; &dsi_r66451_amoled_60hz_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 From bc6891875c3b0c9ffcfd93339e3b409d3ba6fb79 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Tue, 20 Jul 2021 19:47:53 +0530 Subject: [PATCH 265/327] ARM: dts: msm: add dummy regulator for ibb supply for Blair When the AMOLED panel is powered from the external power source, the IBB regulator is not needed. In the absence of ibb regulator node we are getting error message (non-fatal) for AMOLED panel's operation on ibb during change in the power states. Using stub regulator for ibb supply to fix this error. The Blair display DT includes DT of PM6125 variant of Holi, so this change applies to both. Change-Id: I851cef3e6c235b8ee2fa334c45c96caa038262bf --- display/holi-sde-display-cdp-pm6125.dtsi | 9 ++++++++- display/holi-sde-display-common.dtsi | 10 ++++++++++ display/holi-sde-display-mtp-pm6125.dtsi | 9 ++++++++- display/holi-sde-display-qrd-pm6125.dtsi | 9 ++++++++- 4 files changed, 34 insertions(+), 3 deletions(-) diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index 4daffd87cf89..964f8a8ff0d8 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -44,14 +44,21 @@ pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; }; &sde_dsi { vddio-supply = <&L13A>; avdd-supply = <&display_panel_avdd>; + ibb-supply = <&display_panel_ibb>; /delete-property/ lab-supply; - /delete-property/ ibb-supply; pinctrl-0 = <&sde_te_active &disp_pins_reset>; qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; diff --git a/display/holi-sde-display-common.dtsi b/display/holi-sde-display-common.dtsi index b9bd7bf572f0..7534c0b447a8 100644 --- a/display/holi-sde-display-common.dtsi +++ b/display/holi-sde-display-common.dtsi @@ -161,6 +161,16 @@ qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; }; dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi index 4daffd87cf89..964f8a8ff0d8 100644 --- a/display/holi-sde-display-mtp-pm6125.dtsi +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -44,14 +44,21 @@ pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; }; &sde_dsi { vddio-supply = <&L13A>; avdd-supply = <&display_panel_avdd>; + ibb-supply = <&display_panel_ibb>; /delete-property/ lab-supply; - /delete-property/ ibb-supply; pinctrl-0 = <&sde_te_active &disp_pins_reset>; qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>; diff --git a/display/holi-sde-display-qrd-pm6125.dtsi b/display/holi-sde-display-qrd-pm6125.dtsi index 6ed7c6ad2e0b..3ae08c2c7434 100644 --- a/display/holi-sde-display-qrd-pm6125.dtsi +++ b/display/holi-sde-display-qrd-pm6125.dtsi @@ -44,14 +44,21 @@ pinctrl-names = "default"; pinctrl-0 = <&display_panel_avdd_default>; }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; }; &sde_dsi { vddio-supply = <&L13A>; avdd-supply = <&display_panel_avdd>; + ibb-supply = <&display_panel_ibb>; /delete-property/ lab-supply; - /delete-property/ ibb-supply; pinctrl-0 = <&sde_te_active &disp_pins_reset>; qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; From 83c9346d407211cf989d2595f25383ae22635074 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Fri, 23 Jul 2021 14:55:30 +0800 Subject: [PATCH 266/327] ARM: dts: msm: Update phy timings based on Blair revision YK The display panel timings for Blair QRD need to be updated to match with latest timing revision to avoid display issues. Change-Id: I49cd26e2bde2dbc8100580269e06b0e159ecc2ca --- display/blair-sde-display-qrd.dtsi | 32 +++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index e12529ae97cf..a197818eee41 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -5,18 +5,18 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00 10 14]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; }; timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00 15 15]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; }; timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 - 07 08 02 04 00 1a 17]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; }; }; }; @@ -26,8 +26,8 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 - 07 08 02 04 00 1a 17]; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; }; }; }; @@ -37,13 +37,13 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00 10 14]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; }; timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00 15 15]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; }; }; }; @@ -53,8 +53,8 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 06 02 04 00 15 15]; + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; }; }; }; @@ -64,8 +64,8 @@ /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 - 04 03 02 04 00 10 14]; + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; }; }; }; From 9dce5d956dab6c9f7782d33b3bd0dea305401817 Mon Sep 17 00:00:00 2001 From: Yu Wu Date: Tue, 20 Jul 2021 18:34:22 +0800 Subject: [PATCH 267/327] ARM: dts: msm: remove the t-clk-post and t-clk-pre timings for blair QRD The qcom,mdss-dsi-t-clk-post and qcom,mdss-dsi-t-clk-pre panel properties are not required for DSI ctrl v2.3.0 and above, using DSI phy v4.0.0 and above. As the Blair is reusing the display nodes from the Holi target, these two properties are getting included automatically. If these properties are defined, the DSI ctrl programs the DSI_CLKOUT_TIMING_CTRL register for all the DSI PHY versions, that is not recommended as per the DSI HPG. We don't need these two for the Blair, remove them. Change-Id: Ic4e1a3a306e4aa191cd7cb3b6017cd3b2f226e8e --- display/blair-sde-display-qrd.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index e8d21a2f08c7..e12529ae97cf 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -1,6 +1,8 @@ /* Should extend holi-sde-display-qrd-pm6125.dtsi */ &dsi_r66451_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 @@ -20,6 +22,8 @@ }; &dsi_r66451_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 @@ -29,6 +33,8 @@ }; &dsi_r66451_amoled_90hz_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 @@ -43,6 +49,8 @@ }; &dsi_r66451_amoled_90hz_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 @@ -52,6 +60,8 @@ }; &dsi_r66451_amoled_60hz_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04 From 98d60e8e789b0de5781b7c824ed276aca701f400 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Tue, 20 Jul 2021 13:12:00 +0530 Subject: [PATCH 268/327] ARM: dts: msm: remove the t-clk-post and t-clk-pre timings from Blair The qcom,mdss-dsi-t-clk-post and qcom,mdss-dsi-t-clk-pre panel properties are not required for DSI ctrl v2.3.0 and above, using DSI phy v4.0.0 and above. As the Blair is reusing the display nodes from the Holi target, these two properties are getting included automatically. If these properties are defined, the DSI ctrl programs the DSI_CLKOUT_TIMING_CTRL register for all the DSI PHY versions, that is not recommended as per the DSI HPG. We don't need these two for the Blair, remove them from Blair CDP and MTP platforms. Change-Id: I81d66c53fabfc389466b0dbf82c8d8678f08868a --- display/blair-sde-display-cdp.dtsi | 21 +++++++++++++++++++++ display/blair-sde-display-mtp.dtsi | 9 +++++++++ 2 files changed, 30 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index cad3a0ad1a34..c373b3910512 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -70,6 +70,9 @@ }; &dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 @@ -79,6 +82,9 @@ }; &dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -88,6 +94,9 @@ }; &dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -114,6 +123,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 24 09 0a 26 25 09 @@ -140,6 +152,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08 @@ -166,6 +181,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 @@ -195,6 +213,9 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0"; + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 22 1F 06 diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index f1786f5e53d2..bab296d1f4a0 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -20,6 +20,9 @@ }; &dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 @@ -29,6 +32,9 @@ }; &dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 @@ -38,6 +44,9 @@ }; &dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 From f1c340e64b71457f063774176b9991e65b0a2b1e Mon Sep 17 00:00:00 2001 From: osaisruj Date: Thu, 8 Jul 2021 22:06:41 +0530 Subject: [PATCH 269/327] ARM: dts: msm: Add rounded corner dtsi nodes for monaco add rounded corner feature dtsi nodes for monaco target. Change-Id: Ic8c7246dfcda8538285af53ecc69a10a782e0dd0 --- display/monaco-sde.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 00150f1a4710..6a08b33837d0 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -79,6 +79,11 @@ qcom,sde-dspp-off = <0x55000>; qcom,sde-dspp-size = <0xfe4>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-intf-off = <0x0 0x6b800>; qcom,sde-intf-size = <0x2b8>; qcom,sde-intf-type = "none", "dsi"; From 5a5a785736ffbe79adeabf63881a8ea98ccbaf6a Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 29 Jul 2021 16:10:29 +0530 Subject: [PATCH 270/327] ARM: dts: msm: Add display support for Blair ATP platform Add DSI display support for the Blair ATP platform. Change-Id: I0fbd9e5548e065f12b07f1a070617899f9b0fbbc --- display/blair-sde-display-atp.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 display/blair-sde-display-atp.dtsi diff --git a/display/blair-sde-display-atp.dtsi b/display/blair-sde-display-atp.dtsi new file mode 100644 index 000000000000..70996f26740e --- /dev/null +++ b/display/blair-sde-display-atp.dtsi @@ -0,0 +1,59 @@ +/* Should extend holi-sde-display-atp.dtsi */ +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; +}; + +&dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + /delete-property/ qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + /delete-property/ qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + From bc51801a60792b924fc37ef399630a36ffafd2d4 Mon Sep 17 00:00:00 2001 From: osaisruj Date: Fri, 9 Jul 2021 15:26:24 +0530 Subject: [PATCH 271/327] ARM: dts: msm: add idle mode commands in panel dtsi Add idle mode commands for RM69090 truly 1.78" amoled panel. Change-Id: I5989861547cc2cd83a735512f95c897489f3c19b --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi index 55601b26b6e5..9b5899fe751f 100644 --- a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -68,6 +68,18 @@ 15 01 00 00 00 00 02 4F 01]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp2-command = [ + 15 01 00 00 46 00 02 FE 00 + 05 01 00 00 00 00 01 39 + ]; + qcom,mdss-dsi-lp2-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 1f 00 01 38 /* Idle-Mode Off */ + 15 01 00 00 00 00 02 FE 00 + 29 01 00 00 00 00 05 2A 00 10 01 7F + 29 01 00 00 00 00 05 2B 00 00 01 BF + 05 01 00 00 00 00 02 12 00 + ]; }; }; }; From 159b34c32d708acef677de4a84959636a77c3c60 Mon Sep 17 00:00:00 2001 From: osaisruj Date: Mon, 26 Jul 2021 15:34:27 +0530 Subject: [PATCH 272/327] ARM: dts: msm: add panel dtsi for monaco WDP Add panel dtsi for RM6D030 1.41" amoled panel. Change-Id: Ide0d69cb6685b11910fea78f7c8f7f5e6042a3a5 --- display/dsi-panel-rm6d030-amoled-141-cmd.dtsi | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 display/dsi-panel-rm6d030-amoled-141-cmd.dtsi diff --git a/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi new file mode 100644 index 000000000000..4299f95bfbba --- /dev/null +++ b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi @@ -0,0 +1,86 @@ +&mdss_mdp { + dsi_rm6d030_amoled_cmd: qcom,mdss_dsi_rm6d030_amoled_141_cmd { + qcom,mdss-dsi-panel-name = + "RM6D030 1.41 amoled cmd mode"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <320>; + qcom,mdss-dsi-panel-height = <360>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 00 + 15 01 00 00 00 00 02 C4 80 + 39 01 00 00 00 00 05 2A 00 06 01 61 + 39 01 00 00 00 00 05 2B 00 00 01 B9 + 39 01 00 00 00 00 05 30 00 01 01 B8 + 39 01 00 00 00 00 05 31 00 07 01 60 + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 51 FF + 05 01 00 00 60 00 02 11 00 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 15 01 00 00 00 00 02 4F 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp2-command = [ + 15 01 00 00 00 00 02 FE 00 + 05 01 00 00 00 00 01 39 + ]; + qcom,mdss-dsi-lp2-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 1f 00 01 38 /* Idle-Mode Off */ + 15 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 05 2A 00 06 01 61 + 39 01 00 00 00 00 05 2B 00 00 01 B9 + 05 01 00 00 00 00 02 12 00 + ]; + }; + }; + }; +}; From 2a52a9997709ebd2c37f99b6f8c3b27df1bde165 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 29 Jul 2021 16:10:29 +0530 Subject: [PATCH 273/327] ARM: dts: msm: Add display support for Blair ATP platform Add DSI display support for the Blair ATP platform. Change-Id: I0fbd9e5548e065f12b07f1a070617899f9b0fbbc --- display/blair-sde-display-atp.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 display/blair-sde-display-atp.dtsi diff --git a/display/blair-sde-display-atp.dtsi b/display/blair-sde-display-atp.dtsi new file mode 100644 index 000000000000..70996f26740e --- /dev/null +++ b/display/blair-sde-display-atp.dtsi @@ -0,0 +1,59 @@ +/* Should extend holi-sde-display-atp.dtsi */ +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; +}; + +&dsi_sim_vid { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01 + 01 02 02 04 00 0a 11]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + /delete-property/ qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + /delete-property/ qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 18 17 08 + 08 08 02 04 00 1b 0d]; + }; + }; +}; + From ff15377cf2102069a9df6bedb18e2fa9950fbbeb Mon Sep 17 00:00:00 2001 From: Yu Wu Date: Thu, 12 Aug 2021 18:01:03 +0800 Subject: [PATCH 274/327] ARM: dts: msm: update vddio for r66451 panel Panel dead happen randomly because of high panel power consumption, increase max vddio for r66451 panel to fix panel dead issue. Change-Id: Ib091cbab6ba4e9e1dd3f8a9ca4b6ad9afc36c174 --- display/blair-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index a197818eee41..9d188f767321 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ /* Should extend holi-sde-display-qrd-pm6125.dtsi */ +&dsi_panel_pwr_supply_avdd { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; + &dsi_r66451_amoled_cmd { /delete-property/ qcom,mdss-dsi-t-clk-post; /delete-property/ qcom,mdss-dsi-t-clk-pre; From 5c85cb414fc2657feff83dc18a611156489927db Mon Sep 17 00:00:00 2001 From: Yu Wu Date: Thu, 12 Aug 2021 18:01:03 +0800 Subject: [PATCH 275/327] ARM: dts: msm: update vddio for r66451 panel Panel dead happen randomly because of high panel power consumption, increase max vddio for r66451 panel to fix panel dead issue. Change-Id: Ib091cbab6ba4e9e1dd3f8a9ca4b6ad9afc36c174 --- display/blair-sde-display-qrd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi index a197818eee41..9d188f767321 100644 --- a/display/blair-sde-display-qrd.dtsi +++ b/display/blair-sde-display-qrd.dtsi @@ -1,5 +1,12 @@ /* Should extend holi-sde-display-qrd-pm6125.dtsi */ +&dsi_panel_pwr_supply_avdd { + qcom,panel-supply-entry@0 { + qcom,supply-min-voltage = <1860000>; + qcom,supply-max-voltage = <1860000>; + }; +}; + &dsi_r66451_amoled_cmd { /delete-property/ qcom,mdss-dsi-t-clk-post; /delete-property/ qcom,mdss-dsi-t-clk-pre; From 4340f6f032b462c36c0e8f35a24907858074a432 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Tue, 24 Aug 2021 19:08:56 +0530 Subject: [PATCH 276/327] ARM: dts: qcom: update idle mode commands for RM69090 cmd panel Add idle commands to enter 24 bit mode. Change-Id: I3228636ae019e02c1ddc12e8393e31d5496db767 --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi index 9b5899fe751f..760cb09ee2f0 100644 --- a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -69,6 +69,8 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-lp2-command = [ + 15 01 00 00 00 00 02 FE 01 + 15 01 00 00 00 00 02 2A 03 15 01 00 00 46 00 02 FE 00 05 01 00 00 00 00 01 39 ]; From 85ec5ae92dd9b6d79ec556e4db3452a7bb04ebd3 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Fri, 27 Aug 2021 13:56:21 +0530 Subject: [PATCH 277/327] ARM: dts: msm: add cpu irq latency for display Add recommended QOS settings. Change-Id: I5e419f9355373aaf043c2b047424da720402f5b9 --- display/monaco-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 6a08b33837d0..1518a5165ba5 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -158,6 +158,7 @@ qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-secure-sid-mask = <0x0000421>; qcom,sde-num-mnoc-ports = <1>; From aa65e650f6c49ba93c1c14697cd4b82c17df8a67 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Fri, 16 Jul 2021 14:13:03 +0530 Subject: [PATCH 278/327] ARM: dts: msm: add dts of display for qrb2210-rb1 Add sde dts of display and HDMI panel dts for qrb2210-rb1. Change-Id: Iada831811666082ac934037fb1fca7b83263e197 --- display/dsi-panel-ext-bridge-1080p.dtsi | 4 +- display/qrb2210-rb1-sde-display.dtsi | 101 ++++++++ display/qrb2210-rb1-sde.dtsi | 322 ++++++++++++++++++++++++ 3 files changed, 425 insertions(+), 2 deletions(-) create mode 100644 display/qrb2210-rb1-sde-display.dtsi create mode 100644 display/qrb2210-rb1-sde.dtsi diff --git a/display/dsi-panel-ext-bridge-1080p.dtsi b/display/dsi-panel-ext-bridge-1080p.dtsi index 07d398e9e16c..38c25ef0d8fd 100644 --- a/display/dsi-panel-ext-bridge-1080p.dtsi +++ b/display/dsi-panel-ext-bridge-1080p.dtsi @@ -20,8 +20,8 @@ qcom,mdss-dsi-lane-3-state; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-t-clk-post = <0x03>; - qcom,mdss-dsi-t-clk-pre = <0x24>; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; diff --git a/display/qrb2210-rb1-sde-display.dtsi b/display/qrb2210-rb1-sde-display.dtsi new file mode 100644 index 000000000000..8d03ecffe89c --- /dev/null +++ b/display/qrb2210-rb1-sde-display.dtsi @@ -0,0 +1,101 @@ +#include +#include "dsi-panel-ext-bridge-1080p.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + vddio-supply = <&L15A>; + qcom,mdp = <&mdss_mdp>; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; diff --git a/display/qrb2210-rb1-sde.dtsi b/display/qrb2210-rb1-sde.dtsi new file mode 100644 index 000000000000..b37deff088c4 --- /dev/null +++ b/display/qrb2210-rb1-sde.dtsi @@ -0,0 +1,322 @@ +#include + +&soc { + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", + "div_clk", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <2700000>; + qcom,sde-max-bw-high-kbps = <2700000>; + qcom,sde-min-core-ib-kbps = <1300000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x00000000 + 0x00000000 0x00000000 0x00000000>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma"; + qcom,sde-limit-ids= <0x1 0x2>; + qcom,sde-limit-values = <0x1 2160>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2700000>, + <0x9 2700000>, + <0x2 2700000>, + <0xa 2700000>, + <0x4 2700000>, + <0xc 2700000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi0_ctrl { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L5A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1312000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>, + <0x5e94200 0x100>, + <0x5e94400 0x588>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + memory-region = <&dfps_data_memory>; + vdda-0p9-supply = <&VDD_MX_LEVEL>; + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; From 5573b357487cda33fb0d987d6352dea172bc118d Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Sat, 28 Aug 2021 01:13:18 +0530 Subject: [PATCH 279/327] ARM: dts: msm: update max clk rate for display clocks Update max clk rates for mdp clks. Change-Id: I1732f73d1646d8aa08ffbaebfd6afacda07baaaf --- display/monaco-sde.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 1518a5165ba5..aee56512a059 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -40,8 +40,8 @@ clock-names = "gcc_bus", "throttle_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk"; - clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; - clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>; + clock-rate = <0 0 0 300000000 19200000 192000000>; + clock-max-rate = <0 0 0 400000000 19200000 400000000>; sde-vdd-supply = <&mdss_core_gdsc>; From 1ff59a86b7fa50c20bd13dc219ba248c8ffc9a93 Mon Sep 17 00:00:00 2001 From: osaisruj Date: Tue, 17 Aug 2021 23:16:36 +0530 Subject: [PATCH 280/327] ARM: dts: msm: add panel support for monaco WDP Add RM6D030 1.41" amoled panel node for monaco. Change-Id: I4dbe5484ed4239a163d3b9d4653686624c5fdbff --- display/monaco-sde-display.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 96f16f6bede1..0bda2f93c0a0 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -1,5 +1,6 @@ #include #include "dsi-panel-rm69090-amoled-178-cmd.dtsi" +#include "dsi-panel-rm6d030-amoled-141-cmd.dtsi" &soc { dsi_panel_pwr_supply: dsi_panel_pwr_supply { @@ -132,3 +133,19 @@ }; }; +&dsi_rm6d030_amoled_cmd { + qcom,mdss-dsi-t-clk-post = <0x07>; + qcom,mdss-dsi-t-clk-pre = <0x0A>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0A 02 02 0F 1D 02 + 02 02 02 02 04 0A 07]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; From 7dd29cac8c7b73ceedc15880652d3e3e610a1f97 Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Tue, 8 Jun 2021 11:50:06 +0530 Subject: [PATCH 281/327] ARM: dts: msm: add video mode support for RM69090 panel Add video mode panel dtsi for RM69090 amoled panel. Change-Id: I0aec795eb2662f92566394586da74acb6f3a1f70 --- display/dsi-panel-rm69090-amoled-178-vid.dtsi | 77 +++++++++++++++++++ display/monaco-sde-display.dtsi | 17 ++++ 2 files changed, 94 insertions(+) create mode 100644 display/dsi-panel-rm69090-amoled-178-vid.dtsi diff --git a/display/dsi-panel-rm69090-amoled-178-vid.dtsi b/display/dsi-panel-rm69090-amoled-178-vid.dtsi new file mode 100644 index 000000000000..3b60514ab2f3 --- /dev/null +++ b/display/dsi-panel-rm69090-amoled-178-vid.dtsi @@ -0,0 +1,77 @@ +&mdss_mdp { + dsi_rm69090_amoled_vid: qcom,mdss_dsi_rm69090_amoled_178_vid { + qcom,mdss-dsi-panel-name = + "RM69090 1.78 amoled vid mode"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <368>; + qcom,mdss-dsi-panel-height = <448>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 01 + 15 01 00 00 00 00 02 0D 01 + 15 01 00 00 00 00 02 6A 03 + 15 01 00 00 00 00 02 FE 00 + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 05 2A 00 10 01 7F + 39 01 00 00 00 00 05 2B 00 00 01 BF + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 40 00 02 29 00 + ]; + + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 15 01 00 00 00 00 02 4F 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 0bda2f93c0a0..9c3d2a4c169f 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -1,5 +1,6 @@ #include #include "dsi-panel-rm69090-amoled-178-cmd.dtsi" +#include "dsi-panel-rm69090-amoled-178-vid.dtsi" #include "dsi-panel-rm6d030-amoled-141-cmd.dtsi" &soc { @@ -133,6 +134,22 @@ }; }; +&dsi_rm69090_amoled_vid { + qcom,mdss-dsi-t-clk-post = <0x07>; + qcom,mdss-dsi-t-clk-pre = <0x09>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 0E 1B 02 + 02 02 01 02 04 09 07]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_rm6d030_amoled_cmd { qcom,mdss-dsi-t-clk-post = <0x07>; qcom,mdss-dsi-t-clk-pre = <0x0A>; From 8d696c6662b9dfa88d5d0bad6b06911eac6214dd Mon Sep 17 00:00:00 2001 From: osaisruj Date: Thu, 23 Sep 2021 10:43:29 +0530 Subject: [PATCH 282/327] ARM: dts: msm: add dummy ibb regulator supply for amoled panel When the AMOLED panel is powered from the external power source, the IBB regulator is not needed. In the absence of ibb regulator node we are getting error message (non-fatal) for AMOLED panel's operation on ibb during change in the power states. Using stub regulator for ibb supply to fix this error. Change-Id: Id11164a846e0034801980b3e1417cf47ad996e70 --- display/monaco-sde-display.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 0bda2f93c0a0..8f36ad3febb5 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -76,6 +76,38 @@ }; }; + dsi_panel_pwr_supply_nolab_amoled: dsi_panel_pwr_supply_nolab_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; @@ -105,6 +137,7 @@ qcom,platform-te-gpio = <&tlmm 73 0>; qcom,panel-te-source = <0>; vddio-supply = <&L21A>; + ibb-supply = <&display_panel_ibb>; qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = From f5939a667d1d1e90ed6e573fa5c1d75b4aa8451b Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Mon, 13 Sep 2021 14:13:02 +0530 Subject: [PATCH 283/327] ARM: dts: msm: update init sequence for display panel Update init sequence for rm6d030 amoled panel. Change-Id: I6acf33e6e4af087e8a29773954b2fdb8cbdfbd86 --- display/dsi-panel-rm6d030-amoled-141-cmd.dtsi | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi index 4299f95bfbba..39cf853cf85e 100644 --- a/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi +++ b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi @@ -51,21 +51,27 @@ qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 20 + 15 01 00 00 00 00 02 5A 0E + 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 FE 00 - 15 01 00 00 00 00 02 C4 80 - 39 01 00 00 00 00 05 2A 00 06 01 61 - 39 01 00 00 00 00 05 2B 00 00 01 B9 - 39 01 00 00 00 00 05 30 00 01 01 B8 - 39 01 00 00 00 00 05 31 00 07 01 60 - 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2A 00 00 01 3F + 39 01 00 00 00 00 05 2B 00 00 01 67 + 39 01 00 00 00 00 05 30 00 00 01 67 + 39 01 00 00 00 00 05 31 00 00 01 3F + 15 01 00 00 00 00 02 35 02 + 15 01 00 00 00 00 02 53 20 15 01 00 00 00 00 02 51 FF - 05 01 00 00 60 00 02 11 00 + 15 01 00 00 00 00 02 63 FF + 05 01 00 00 00 00 02 12 00 + 05 01 00 00 32 00 02 11 00 05 01 00 00 00 00 02 29 00 ]; qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00 - 15 01 00 00 00 00 02 4F 01]; + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 53 00 02 10 00 + 15 01 00 00 00 00 02 4F 01 + ]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-lp2-command = [ @@ -76,8 +82,8 @@ qcom,mdss-dsi-nolp-command = [ 05 01 00 00 1f 00 01 38 /* Idle-Mode Off */ 15 01 00 00 00 00 02 FE 00 - 39 01 00 00 00 00 05 2A 00 06 01 61 - 39 01 00 00 00 00 05 2B 00 00 01 B9 + 39 01 00 00 00 00 05 2A 00 00 01 3F + 39 01 00 00 00 00 05 2B 00 00 01 67 05 01 00 00 00 00 02 12 00 ]; }; From 1cb4eba2c1eb991800823057c006831d02736cdf Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Mon, 27 Sep 2021 17:22:42 +0530 Subject: [PATCH 284/327] ARM: dts: msm: enable ulps for panels on monaco Enable ulps for rm69090 and rm6d030 panels. Change-Id: I77442d622061350d50150f04ade16e980e7c3cd7 --- display/monaco-sde-display.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 9c3d2a4c169f..b879b94f97c8 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -118,6 +118,7 @@ }; &dsi_rm69090_amoled_cmd { + qcom,ulps-enabled; qcom,mdss-dsi-t-clk-post = <0x08>; qcom,mdss-dsi-t-clk-pre = <0x0B>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", /*TODO: check these*/ @@ -135,6 +136,7 @@ }; &dsi_rm69090_amoled_vid { + qcom,ulps-enabled; qcom,mdss-dsi-t-clk-post = <0x07>; qcom,mdss-dsi-t-clk-pre = <0x09>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", @@ -151,6 +153,7 @@ }; &dsi_rm6d030_amoled_cmd { + qcom,ulps-enabled; qcom,mdss-dsi-t-clk-post = <0x07>; qcom,mdss-dsi-t-clk-pre = <0x0A>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", From 868c40ae4496a1107107dff665593f97fb801b31 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Tue, 28 Sep 2021 10:04:44 +0800 Subject: [PATCH 285/327] ARM: dts: msm: update interrupt type for QPIC display Update interrupt type from IRQ_TYPE_NONE to IRQ_TYPE_LEVEL_HIGH to avoid warning message for QPIC display. Change-Id: I378192aab8cdea76568f0a36867f299d743f48eb --- display/sdxlemur-qpic-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sdxlemur-qpic-display.dtsi b/display/sdxlemur-qpic-display.dtsi index b6ede6f9fbea..393b3444c44f 100644 --- a/display/sdxlemur-qpic-display.dtsi +++ b/display/sdxlemur-qpic-display.dtsi @@ -5,7 +5,7 @@ reg = <0x1b00000 0x24000>; reg-names = "qpic_base"; - interrupts = <0 75 0>; + interrupts = ; interrupt-names = "qpic_irq"; interconnect-names = "qpic-display-data-bus"; From 47f3a46f77a409b84c97ad5b8a6e2a8620c5785e Mon Sep 17 00:00:00 2001 From: Jayaprakash Madisetty Date: Fri, 1 Oct 2021 11:24:50 +0530 Subject: [PATCH 286/327] ARM: dts: msm: add sde-mixer-cwb-mask property This change adds cwb mixer_mask property for identifying compatible Layermixers during cwb usecase. Change-Id: I182a3ec723dfb5a994e9b616f5996952a6aaed93 --- display/lahaina-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 66182dd3bc09..af82cc4430e0 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -37,6 +37,7 @@ qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb", "cwb", "cwb"; + qcom,sde-mixer-cwb-mask = <0x0 0x0 0x5 0xa 0x11 0x22>; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; From c1e4afa7586416279df3b892549eebb237074c75 Mon Sep 17 00:00:00 2001 From: Jayaprakash Madisetty Date: Thu, 30 Sep 2021 22:07:23 +0530 Subject: [PATCH 287/327] bindings: Documentation: add property for cwb mixer mask Add documentation for the property to specify mixer_mask compatible for each mixer with cwb mux HW block present. Change-Id: I07b5e5a19a9896ed565440e0fa150fa92ae12c4c --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index e8ecd18f8ba1..5d233cb3168e 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -514,6 +514,9 @@ Optional properties: for CWB. Possible values: "cwb" - preferred for cwb "none" - no preference on display +-qcom,sde-mixer-cwb-mask: A u32 array of bitmask for each mixer which has CWB preference set. + The bitmask indicates the mux connections existed in HW from all + the mixers to the cwb mixer id in the list. - qcom,sde-ctl-display-pref: A string array indicating the preferred display type for the ctl block. Possible values: "primary" - preferred for primary display @@ -621,6 +624,7 @@ Example: "none", "none"; qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "none"; + qcom,sde-mixer-cwb-mask = <0x0 0x0 0x5 0xa 0x11 0x22>; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-off = <0x00055000 0x00057000>; qcom,sde-dspp-ad-off = <0x24000 0x22800>; From bbe50491eb38b10cd904943da0341b95c238871a Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Wed, 22 Sep 2021 09:28:40 +0530 Subject: [PATCH 288/327] ARM: dts: msm: update regulator load values Update panel regulator load values and ulp load values. Change-Id: Ibec9fd7d7830a94204781ea47ae6ea6f24ed816b --- display/monaco-sde-display.dtsi | 9 ++++++--- display/monaco-sde.dtsi | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 293ec4ce4a5e..fe7a8fc764e9 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -13,8 +13,9 @@ qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <2000000>; - qcom,supply-enable-load = <62000>; + qcom,supply-enable-load = <4000>; qcom,supply-disable-load = <80>; + qcom,supply-ulp-load = <100>; qcom,supply-post-on-sleep = <20>; }; @@ -47,8 +48,9 @@ qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <2000000>; - qcom,supply-enable-load = <62000>; + qcom,supply-enable-load = <4000>; qcom,supply-disable-load = <80>; + qcom,supply-ulp-load = <100>; qcom,supply-post-on-sleep = <20>; }; }; @@ -62,8 +64,9 @@ qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <2000000>; - qcom,supply-enable-load = <62000>; + qcom,supply-enable-load = <4000>; qcom,supply-disable-load = <80>; + qcom,supply-ulp-load = <100>; qcom,supply-post-on-sleep = <20>; }; diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index aee56512a059..4603e6161032 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -266,6 +266,7 @@ qcom,supply-max-voltage = <1312000>; qcom,supply-enable-load = <21800>; qcom,supply-disable-load = <0>; + qcom,supply-ulp-load = <0>; }; }; @@ -321,6 +322,7 @@ qcom,supply-max-voltage = <904000>; qcom,supply-enable-load = <37550>; qcom,supply-disable-load = <0>; + qcom,supply-ulp-load = <0>; }; }; }; From 2e3089913ebd1e96232fb308fb6879079f0d5ea7 Mon Sep 17 00:00:00 2001 From: osaisruj Date: Mon, 4 Oct 2021 12:39:31 +0530 Subject: [PATCH 289/327] ARM: dts: msm: update dsi commands for rm69090 panel Remove partial mode on command from nolp commands for rm69090 amoled panel. Also, update dsi init sequence to support 24-bit mode. Change-Id: I1e7b2ff5ff7080c108d866165ec2fe6769bb9c04 --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi index 760cb09ee2f0..57c46bde5b16 100644 --- a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -53,6 +53,7 @@ qcom,mdss-dsi-on-command = [ 15 01 00 00 00 00 02 FE 01 15 01 00 00 00 00 02 6A 03 + 15 01 00 00 00 00 02 2A 03 15 01 00 00 00 00 02 FE 00 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 FF @@ -69,8 +70,6 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-lp2-command = [ - 15 01 00 00 00 00 02 FE 01 - 15 01 00 00 00 00 02 2A 03 15 01 00 00 46 00 02 FE 00 05 01 00 00 00 00 01 39 ]; @@ -80,7 +79,6 @@ 15 01 00 00 00 00 02 FE 00 29 01 00 00 00 00 05 2A 00 10 01 7F 29 01 00 00 00 00 05 2B 00 00 01 BF - 05 01 00 00 00 00 02 12 00 ]; }; }; From 8dd9a17f202e7b02db543131c496cdf3e7fb4c2c Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Tue, 5 Oct 2021 17:31:58 +0530 Subject: [PATCH 290/327] ARM: dts: msm: enable esd check for rm69090 amoled panel Enable esd check dtsi entries for rm69090 amoled panel. Change-Id: Ia1dcb8fc213bd5215994c340d231a6f5976cc959 --- display/monaco-sde-display.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index fe7a8fc764e9..f9824059c770 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -161,6 +161,13 @@ "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0C 03 03 10 1D 03 @@ -178,6 +185,14 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 0E 1B 02 From fa234e27992e66ea93ebc2ee852dd18086ea730a Mon Sep 17 00:00:00 2001 From: lliu6 Date: Mon, 1 Nov 2021 18:50:08 +0800 Subject: [PATCH 291/327] ARM: dts: qcom: update idle mode commands for RM69090 cmd panel Revert idle commands to enter 24 bit mode to solve the issue of inconsistent color depth. Change-Id: Iabcef1277fc8e175fabc6186f9246d36e3fb6ef9 --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi index 57c46bde5b16..1a2db26c6873 100644 --- a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -70,6 +70,8 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-lp2-command = [ + 15 01 00 00 00 00 02 FE 01 + 15 01 00 00 00 00 02 2A 03 15 01 00 00 46 00 02 FE 00 05 01 00 00 00 00 01 39 ]; From 4218195c835f2705433dfc20a703c09854c0cf7b Mon Sep 17 00:00:00 2001 From: Srihitha Tangudu Date: Fri, 12 Nov 2021 20:09:44 +0530 Subject: [PATCH 292/327] ARM: dts: msm: add dispcc clock reference for blair dsi-dsiplay node Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes for cont_splash use case. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I5e8cc42aaf0a909eb23ef613216dd47de5586c55 --- display/blair-sde-display-atp.dtsi | 22 ++++++++++++++++++++-- display/blair-sde-display-cdp.dtsi | 22 ++++++++++++++++++++-- display/blair-sde-display-mtp.dtsi | 21 +++++++++++++++++++-- 3 files changed, 59 insertions(+), 6 deletions(-) diff --git a/display/blair-sde-display-atp.dtsi b/display/blair-sde-display-atp.dtsi index 70996f26740e..47a2e1f223de 100644 --- a/display/blair-sde-display-atp.dtsi +++ b/display/blair-sde-display-atp.dtsi @@ -1,5 +1,6 @@ /* Should extend holi-sde-display-atp.dtsi */ #include +#include &sde_dsi { clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, @@ -11,12 +12,29 @@ <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", + "mdp_core_clk"; }; &dsi_sim_vid { diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index c373b3910512..7ebe0dbf49b3 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -1,5 +1,6 @@ /* Should extend holi-sde-display-cdp-pm6125.dtsi */ #include +#include #include "dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi" &tlmm { @@ -56,12 +57,29 @@ <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; pinctrl-0 = <&sde_te_active &disp_pins_reset &lcd_bias_en_active>; diff --git a/display/blair-sde-display-mtp.dtsi b/display/blair-sde-display-mtp.dtsi index bab296d1f4a0..b351902a8330 100644 --- a/display/blair-sde-display-mtp.dtsi +++ b/display/blair-sde-display-mtp.dtsi @@ -1,5 +1,6 @@ /* Should extend holi-sde-display-mtp-pm6125.dtsi */ #include +#include &sde_dsi { clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, @@ -11,12 +12,28 @@ <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", + "mdp_core_clk"; }; &dsi_sim_vid { From 9916594f21befa56af45a6f8ff0c970839294be7 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Thu, 21 Oct 2021 19:24:06 +0530 Subject: [PATCH 293/327] ARM: dts: msm: delay backlight update until first frame on Blair If a DSI DMA command is triggered after enabling the timing engine and just before the first Vsync, it can result into DSI FIFO underflow/overflow errors. In the current case the backlight DCS command is the one that is getting triggered just before first vsync during bridge enable sequence. We can avoid this by delaying the backlight update command until first frame. Enable this on Blair and pm6125 variant of Holi target. Change-Id: Ic719a323e9b06839e2c729b128306b6d7d2f00a4 --- display/holi-sde-display-cdp-pm6125.dtsi | 2 ++ display/holi-sde-display-mtp-pm6125.dtsi | 2 ++ display/holi-sde-display-qrd-pm6125.dtsi | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index 964f8a8ff0d8..fc609eccdeb5 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -75,6 +75,7 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; @@ -83,6 +84,7 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; diff --git a/display/holi-sde-display-mtp-pm6125.dtsi b/display/holi-sde-display-mtp-pm6125.dtsi index 964f8a8ff0d8..fc609eccdeb5 100644 --- a/display/holi-sde-display-mtp-pm6125.dtsi +++ b/display/holi-sde-display-mtp-pm6125.dtsi @@ -75,6 +75,7 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; @@ -83,6 +84,7 @@ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; diff --git a/display/holi-sde-display-qrd-pm6125.dtsi b/display/holi-sde-display-qrd-pm6125.dtsi index 3ae08c2c7434..fe6395fc1847 100644 --- a/display/holi-sde-display-qrd-pm6125.dtsi +++ b/display/holi-sde-display-qrd-pm6125.dtsi @@ -71,6 +71,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; @@ -81,6 +82,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; @@ -92,6 +94,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; @@ -102,6 +105,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; @@ -113,6 +117,7 @@ qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; @@ -123,6 +128,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; From a931ca1a3fd8e46d45ec618acc19f9f1b2a19256 Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Wed, 17 Nov 2021 17:19:50 +0530 Subject: [PATCH 294/327] ARM: dts: msm: Add display support for idp-nopmi on Yupik Add display support for idp-nopmi platform of Yupik. Change-Id: Iecbce00882fdb308b8e4a2aa9e418e31b2b85e86 --- display/yupik-sde-display-idp-nopmi.dtsi | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 display/yupik-sde-display-idp-nopmi.dtsi diff --git a/display/yupik-sde-display-idp-nopmi.dtsi b/display/yupik-sde-display-idp-nopmi.dtsi new file mode 100644 index 000000000000..b7a6a831128c --- /dev/null +++ b/display/yupik-sde-display-idp-nopmi.dtsi @@ -0,0 +1,59 @@ +#include "yupik-sde-display.dtsi" + +&pm8350c_gpios { + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio8"; + function = "func1"; + input-disable; + output-low; + bias-disable; + power-source = <0>; + qcom,drive-strength = <3>; + }; + }; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + pinctrl-names = "panel_active", "panel_suspend", "pwm_pin"; + pinctrl-2 = <&lcd_backlight_ctrl_default>; + + qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>; +}; + +&dsi_nt36672e_fhd_plus_60_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + +&dsi_nt36672e_fhd_plus_120_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + +&dsi_nt36672e_fhd_plus_144_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm8350c_pwm_2 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 44 0>; + qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>; +}; + From fb014cf7bc99bf882f8ef65ed4a85bb0314a4d08 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Mon, 8 Nov 2021 14:51:09 +0530 Subject: [PATCH 295/327] ARM: dts: msm: Add video mode ILI988C LCD panel Add video mode ILI988C LCD panel dtsi. Change-Id: Ib753d1f061f7aab982033b9b3bd0bcbf9c449d4a --- display/dsi-panel-ili988c-dual-video.dtsi | 247 ++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 display/dsi-panel-ili988c-dual-video.dtsi diff --git a/display/dsi-panel-ili988c-dual-video.dtsi b/display/dsi-panel-ili988c-dual-video.dtsi new file mode 100644 index 000000000000..65ccd99b7599 --- /dev/null +++ b/display/dsi-panel-ili988c-dual-video.dtsi @@ -0,0 +1,247 @@ +&mdss_mdp { + dsi_ili9881c_720p_video: qcom,mdss_dsi_ili9881c_720p_video { + qcom,mdss-dsi-panel-name = "ILI988C video signal panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0x3ff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-pan-physical-width-dimension = <62>; + qcom,mdss-pan-physical-height-dimension = <110>; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <200>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <24>; + qcom,mdss-dsi-v-front-porch = <24>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 FF 98 81 03 + 39 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 02 02 00 + 39 01 00 00 00 00 02 03 73 + 39 01 00 00 00 00 02 04 00 + 39 01 00 00 00 00 02 05 00 + 39 01 00 00 00 00 02 06 0C + 39 01 00 00 00 00 02 07 00 + 39 01 00 00 00 00 02 08 00 + 39 01 00 00 00 00 02 09 01 + 39 01 00 00 00 00 02 0A 01 + 39 01 00 00 00 00 02 0B 01 + 39 01 00 00 00 00 02 0C 01 + 39 01 00 00 00 00 02 0D 01 + 39 01 00 00 00 00 02 0E 01 + 39 01 00 00 00 00 02 0F 00 + 39 01 00 00 00 00 02 10 00 + 39 01 00 00 00 00 02 11 00 + 39 01 00 00 00 00 02 12 00 + 39 01 00 00 00 00 02 13 00 + 39 01 00 00 00 00 02 14 00 + 39 01 00 00 00 00 02 15 00 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 00 + 39 01 00 00 00 00 02 18 00 + 39 01 00 00 00 00 02 19 00 + 39 01 00 00 00 00 02 1A 00 + 39 01 00 00 00 00 02 1B 00 + 39 01 00 00 00 00 02 1C 00 + 39 01 00 00 00 00 02 1D 00 + 39 01 00 00 00 00 02 1E 44 + 39 01 00 00 00 00 02 1F C0 + 39 01 00 00 00 00 02 20 0A + 39 01 00 00 00 00 02 21 03 + 39 01 00 00 00 00 02 22 0A + 39 01 00 00 00 00 02 23 00 + 39 01 00 00 00 00 02 24 8C + 39 01 00 00 00 00 02 25 8C + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 27 00 + 39 01 00 00 00 00 02 28 3B + 39 01 00 00 00 00 02 29 03 + 39 01 00 00 00 00 02 2A 00 + 39 01 00 00 00 00 02 2B 00 + 39 01 00 00 00 00 02 2C 00 + 39 01 00 00 00 00 02 2D 00 + 39 01 00 00 00 00 02 2E 00 + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 02 30 00 + 39 01 00 00 00 00 02 31 00 + 39 01 00 00 00 00 02 32 00 + 39 01 00 00 00 00 02 33 00 + 39 01 00 00 00 00 02 34 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 37 00 + 39 01 00 00 00 00 02 38 00 + 39 01 00 00 00 00 02 39 00 + 39 01 00 00 00 00 02 3A 00 + 39 01 00 00 00 00 02 3B 00 + 39 01 00 00 00 00 02 3C 00 + 39 01 00 00 00 00 02 3D 00 + 39 01 00 00 00 00 02 3E 00 + 39 01 00 00 00 00 02 3F 00 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 41 00 + 39 01 00 00 00 00 02 42 00 + 39 01 00 00 00 00 02 43 00 + 39 01 00 00 00 00 02 44 00 + 39 01 00 00 00 00 02 50 01 + 39 01 00 00 00 00 02 51 23 + 39 01 00 00 00 00 02 52 45 + 39 01 00 00 00 00 02 53 67 + 39 01 00 00 00 00 02 54 89 + 39 01 00 00 00 00 02 55 AB + 39 01 00 00 00 00 02 56 01 + 39 01 00 00 00 00 02 57 23 + 39 01 00 00 00 00 02 58 45 + 39 01 00 00 00 00 02 59 67 + 39 01 00 00 00 00 02 5A 89 + 39 01 00 00 00 00 02 5B AB + 39 01 00 00 00 00 02 5C CD + 39 01 00 00 00 00 02 5D EF + 39 01 00 00 00 00 02 5E 11 + 39 01 00 00 00 00 02 5F 0C + 39 01 00 00 00 00 02 60 0D + 39 01 00 00 00 00 02 61 0E + 39 01 00 00 00 00 02 62 0F + 39 01 00 00 00 00 02 63 06 + 39 01 00 00 00 00 02 64 07 + 39 01 00 00 00 00 02 65 02 + 39 01 00 00 00 00 02 66 02 + 39 01 00 00 00 00 02 67 02 + 39 01 00 00 00 00 02 68 02 + 39 01 00 00 00 00 02 69 02 + 39 01 00 00 00 00 02 6A 02 + 39 01 00 00 00 00 02 6B 02 + 39 01 00 00 00 00 02 6C 02 + 39 01 00 00 00 00 02 6D 02 + 39 01 00 00 00 00 02 6E 02 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 70 02 + 39 01 00 00 00 00 02 71 02 + 39 01 00 00 00 00 02 72 02 + 39 01 00 00 00 00 02 73 01 + 39 01 00 00 00 00 02 74 00 + 39 01 00 00 00 00 02 75 0C + 39 01 00 00 00 00 02 76 0D + 39 01 00 00 00 00 02 77 0E + 39 01 00 00 00 00 02 78 0F + 39 01 00 00 00 00 02 79 06 + 39 01 00 00 00 00 02 7A 07 + 39 01 00 00 00 00 02 7B 02 + 39 01 00 00 00 00 02 7C 02 + 39 01 00 00 00 00 02 7D 02 + 39 01 00 00 00 00 02 7E 02 + 39 01 00 00 00 00 02 7F 02 + 39 01 00 00 00 00 02 80 02 + 39 01 00 00 00 00 02 81 02 + 39 01 00 00 00 00 02 82 02 + 39 01 00 00 00 00 02 83 02 + 39 01 00 00 00 00 02 84 02 + 39 01 00 00 00 00 02 85 02 + 39 01 00 00 00 00 02 86 02 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 88 02 + 39 01 00 00 00 00 02 89 01 + 39 01 00 00 00 00 02 8A 00 + 39 01 00 00 00 00 04 FF 98 81 04 + 39 01 00 00 00 00 02 6C 15 + 39 01 00 00 00 00 02 6E 1A + 39 01 00 00 00 00 02 6F A5 + 39 01 00 00 00 00 02 3A 24 + 39 01 00 00 00 00 02 8D 1F + 39 01 00 00 00 00 02 87 BA + 39 01 00 00 00 00 02 26 76 + 39 01 00 00 00 00 02 B2 D1 + 39 01 00 00 00 00 04 FF 98 81 01 + 39 01 00 00 00 00 02 22 0A + 39 01 00 00 00 00 02 31 00 + 39 01 00 00 00 00 02 40 33 + 39 01 00 00 00 00 02 50 A6 + 39 01 00 00 00 00 02 51 A6 + 39 01 00 00 00 00 02 60 06 + 39 01 00 00 00 00 02 61 01 + 39 01 00 00 00 00 02 62 19 + 39 01 00 00 00 00 02 63 10 + 39 01 00 00 00 00 02 A0 1A + 39 01 00 00 00 00 02 A1 1D + 39 01 00 00 00 00 02 A2 2A + 39 01 00 00 00 00 02 A3 10 + 39 01 00 00 00 00 02 A4 13 + 39 01 00 00 00 00 02 A5 27 + 39 01 00 00 00 00 02 A6 1D + 39 01 00 00 00 00 02 A7 1E + 39 01 00 00 00 00 02 A8 84 + 39 01 00 00 00 00 02 A9 1C + 39 01 00 00 00 00 02 AA 27 + 39 01 00 00 00 00 02 AB 70 + 39 01 00 00 00 00 02 AC 16 + 39 01 00 00 00 00 02 AD 14 + 39 01 00 00 00 00 02 AE 49 + 39 01 00 00 00 00 02 AF 21 + 39 01 00 00 00 00 02 B0 28 + 39 01 00 00 00 00 02 B1 5D + 39 01 00 00 00 00 02 B2 6E + 39 01 00 00 00 00 02 B3 39 + 39 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 02 C1 1D + 39 01 00 00 00 00 02 C2 2A + 39 01 00 00 00 00 02 C3 10 + 39 01 00 00 00 00 02 C4 13 + 39 01 00 00 00 00 02 C5 27 + 39 01 00 00 00 00 02 C6 1D + 39 01 00 00 00 00 02 C7 1E + 39 01 00 00 00 00 02 C8 84 + 39 01 00 00 00 00 02 C9 1C + 39 01 00 00 00 00 02 CA 27 + 39 01 00 00 00 00 02 CB 70 + 39 01 00 00 00 00 02 CC 16 + 39 01 00 00 00 00 02 CD 14 + 39 01 00 00 00 00 02 CE 49 + 39 01 00 00 00 00 02 CF 21 + 39 01 00 00 00 00 02 D0 28 + 39 01 00 00 00 00 02 D1 5D + 39 01 00 00 00 00 02 D2 6E + 39 01 00 00 00 00 02 D3 39 + 39 01 00 00 00 00 04 FF 98 81 00 + 39 01 00 00 00 00 02 35 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 14 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; From 7e70bf4a6ba4a4eb8db76005b13ef188409489d9 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Mon, 22 Nov 2021 11:34:00 +0530 Subject: [PATCH 296/327] ARM: dts: msm: add sde dts of display for QCS610 Add sde dtsi of display for QCS610. Change-Id: I246107b16eb4d29a557deef76792d464c8c7fc32 --- display/sm6150-sde-display.dtsi | 185 +++++++++++ display/sm6150-sde.dtsi | 540 ++++++++++++++++++++++++++++++++ 2 files changed, 725 insertions(+) create mode 100644 display/sm6150-sde-display.dtsi create mode 100644 display/sm6150-sde.dtsi diff --git a/display/sm6150-sde-display.dtsi b/display/sm6150-sde-display.dtsi new file mode 100644 index 000000000000..d15671815cfe --- /dev/null +++ b/display/sm6150-sde-display.dtsi @@ -0,0 +1,185 @@ +#include +#include "dsi-panel-ili988c-dual-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + sde_dsi: qcom,dsi-display { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&pm6150_l13>; + vdda-3p3-supply = <&pm6150_l18>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; + qcom,mdp = <&mdss_mdp>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dp { + qcom,dp-usbpd-detection = <&pm6150_pdphy>; + hpd-pwr-supply = <&pm6150_l17>; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <975000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "hpd-pwr"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3230000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_rscc &sde_wb &sde_dp &sde_dsi>; +}; + +&dsi_ili9881c_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = + [1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 10 04 06 03 02 0a]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1b 08 09 05 03 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/sm6150-sde.dtsi b/display/sm6150-sde.dtsi new file mode 100644 index 000000000000..ddb27cb9fbcc --- /dev/null +++ b/display/sm6150-sde.dtsi @@ -0,0 +1,540 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84208>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x214>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 307000000 19200000 307000000>; + + /* Enable thermal cooling device */ + #cooling-cells = <2>; + + /* interrupt config */ + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x0 0x0 0x0>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x0 0x0 0x0>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "none", "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x3b8 24>; + + qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 + 0x6c800>; + + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi","none", "dp"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000>; + qcom,sde-pp-slave = <0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000 + 0x2b000>; + qcom,sde-sspp-src-size = <0x1f0>; + + qcom,sde-sspp-xin-id = <0 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <3 0 1 0 0 0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 + 4500000 4500000 + 4500000 4500000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, + <0x2c4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-wb-linewidth = <2160>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x1>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <4800000>; + qcom,sde-max-bw-high-kbps = <4800000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000000f 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010001>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + + qcom,sde-secure-sid-mask = <0x0000801>; + + /* data and reg bus scale settings */ + interconnects = + <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040001>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x1c44>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <2>; + + vdd-supply = <&mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + clock-rate = <0 0 0>; + + qcom,sde-dram-channels = <2>; + + mboxes = <&disp_rsc 0>; + mbox-names = "disp_rsc"; + + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus"; + }; + + mdss_rotator: qcom,mdss_rotator@ae00000 { + compatible = "qcom,sde_rotator"; + reg = <0x0ae00000 0xac000>, + <0x0aeb8000 0x3000>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x1>; + + interconnects = + <&mmss_noc MASTER_ROTATOR &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,rot-data-bus0", + "qcom,sde-reg-bus"; + qcom,msm-bus,active-only; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-vbif-memtype = <3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-rot-qos-cpu-mask = <0xf>; + qcom,mdss-rot-qos-cpu-dma-latency = <75>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + cache-slice-names = "rotator"; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0xc40 0x0>; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0xc41 0x0>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&pm6150l_l3>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + qcom,split-link-supported; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x588>, + <0xae01400 0x100>, + <0xae94200 0x100>, + <0xae94400 0x588>, + <0xaf03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + memory-region = <&dfps_data_memory>; + vdda-0p9-supply = <&pm6150_l4>; + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <975000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + cell-index = <0>; + }; + + sde_dp: qcom,dp_display@ae90000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + vdda-1p2-supply = <&pm6150l_l3>; + vdda-0p9-supply = <&pm6150_l4>; + reg = <0xae90000 0x0f4>, + <0xae90200 0x0c0>, + <0xae90400 0x5e0>, + <0xae90a00 0x098>, + <0x88e9000 0x17c>, + <0x88e9400 0x10c>, + <0x88e9800 0x10c>, + <0xaf02130 0x8>, + <0x780000 0x621c>, + <0x88e9c30 0x10>, + <0xaee1000 0x34>, + <0x1fcb24c 0x4>, + <0xae91000 0x098>; + + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pixel_mn", "qfprom_physical", "dp_pll", + "hdcp_physical", "dp_tcsr","dp_p1"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>, + <&dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>; + + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_ahb_clk", "core_usb_sec_ref_clk", + "link_clk", "link_iface_clk", + "strm0_pixel_clk","strm1_pixel_clk", "crypto_clk", + "pixel_clk_rcg", "pixel_parent","pixel1_clk_rcg", + "pixel1_parent"; + + + qcom,phy-version = <0x200>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13 23 1d]; + qcom,aux-cfg2-settings = [28 00]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 bb]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,logical2physical-lane-map = [03 02 00 01]; + + qcom,max-lclk-frequency-khz = <540000>; + qcom,max-pclk-frequency-khz = <195000>; + + qcom,max-hdisplay = <1920>; + qcom,max-vdisplay = <1200>; + + qcom,ext-disp = <&ext_disp>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,mux-sel-gpio = <&tlmm 49 0>; + qcom,usbplug-cc-gpio = <&tlmm 104 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep", + "mdss_dp_hpd_active", "mdss_dp_hpd_tlmm", + "mdss_dp_hpd_ctrl"; + pinctrl-0 = <&sde_dp_usbplug_cc_active &sde_dp_switch_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend &sde_dp_switch_suspend>; + pinctrl-2 = <&sde_dp_connector_enable &sde_dp_switch_suspend + &sde_dp_hotplug_tlmm>; + pinctrl-3 = <&sde_dp_hotplug_tlmm>; + pinctrl-4 = <&sde_dp_hotplug_ctrl>; + + qcom,msm-hdcp = <&qcom_msmhdcp>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-vmid = <0xa>; + }; + + smmu_sde_unsec:qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-earlymap; /* for cont-splash */ + }; +}; From d9cf461789faa686c7e6218e8de04843c5d57a5b Mon Sep 17 00:00:00 2001 From: Ke Du Date: Fri, 19 Nov 2021 17:57:37 +0530 Subject: [PATCH 297/327] ARM: dts: msm: add sde display dts for scuba Add sde display dts for scuba. Change-Id: Ibe872711442f2b809c9170c806acbc9cb662b5e0 --- display/scuba-sde-common.dtsi | 276 ++++++++++++++++++++++++++ display/scuba-sde-display-common.dtsi | 58 ++++++ display/scuba-sde-display-idp.dtsi | 9 + display/scuba-sde-display.dtsi | 27 +++ display/scuba-sde.dtsi | 57 ++++++ 5 files changed, 427 insertions(+) create mode 100644 display/scuba-sde-common.dtsi create mode 100644 display/scuba-sde-display-common.dtsi create mode 100644 display/scuba-sde-display-idp.dtsi create mode 100644 display/scuba-sde-display.dtsi create mode 100644 display/scuba-sde.dtsi diff --git a/display/scuba-sde-common.dtsi b/display/scuba-sde-common.dtsi new file mode 100644 index 000000000000..7656671b7126 --- /dev/null +++ b/display/scuba-sde-common.dtsi @@ -0,0 +1,276 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clock-rate = <0 0 0 300000000 19200000 192000000>; + clock-max-rate = <0 0 0 400000000 19200000 400000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* Enable thermal cooling device */ + #cooling-cells = <2>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <2700000>; + qcom,sde-max-bw-high-kbps = <2700000>; + qcom,sde-min-core-ib-kbps = <1300000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x00000000 + 0x00000000 0x00000000 0x00000000>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma"; + qcom,sde-limit-ids= <0x1 0x2>; + qcom,sde-limit-values = <0x1 2160>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2700000>, + <0x9 2700000>, + <0x2 2700000>, + <0xa 2700000>, + <0x4 2700000>, + <0xc 2700000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1312000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>, + <0x5e94200 0x100>, + <0x5e94400 0x588>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/scuba-sde-display-common.dtsi b/display/scuba-sde-display-common.dtsi new file mode 100644 index 000000000000..874322b1111e --- /dev/null +++ b/display/scuba-sde-display-common.dtsi @@ -0,0 +1,58 @@ +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ili988c-dual-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; +}; + +&dsi_ili9881c_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = [ + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 10 04 06 03 02 0a + ]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/scuba-sde-display-idp.dtsi b/display/scuba-sde-display-idp.dtsi new file mode 100644 index 000000000000..af2fa18ab86f --- /dev/null +++ b/display/scuba-sde-display-idp.dtsi @@ -0,0 +1,9 @@ +#include "scuba-sde-display.dtsi" + +&dsi_ili9881c_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 97 0>; +}; diff --git a/display/scuba-sde-display.dtsi b/display/scuba-sde-display.dtsi new file mode 100644 index 000000000000..a448b54798f4 --- /dev/null +++ b/display/scuba-sde-display.dtsi @@ -0,0 +1,27 @@ +#include "scuba-sde-display-common.dtsi" +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L15A>; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; diff --git a/display/scuba-sde.dtsi b/display/scuba-sde.dtsi new file mode 100644 index 000000000000..ee2f3c6e35c7 --- /dev/null +++ b/display/scuba-sde.dtsi @@ -0,0 +1,57 @@ +#include "scuba-sde-common.dtsi" +#include + +&soc { + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_bus", "throttle_clk", "iface_clk", + "core_clk", "vsync_clk", "lut_clk"; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L5A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&VDD_MX_LEVEL>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; +}; From b57f9ee75f8ce01b80d32e773dbcd212cecb27fb Mon Sep 17 00:00:00 2001 From: Ke Du Date: Fri, 19 Nov 2021 18:20:22 +0530 Subject: [PATCH 298/327] ARM: dts: msm: add sde display dts for bengal Add sde display dts for bengal. Change-Id: I94aeab8f31fa699f93f7776d860c42a8fcdef2a2 --- display/bengal-sde-common.dtsi | 279 +++++++++++++++++++++++++ display/bengal-sde-display-common.dtsi | 58 +++++ display/bengal-sde-display-idp.dtsi | 9 + display/bengal-sde-display.dtsi | 27 +++ display/bengal-sde.dtsi | 57 +++++ 5 files changed, 430 insertions(+) create mode 100644 display/bengal-sde-common.dtsi create mode 100644 display/bengal-sde-display-common.dtsi create mode 100644 display/bengal-sde-display-idp.dtsi create mode 100644 display/bengal-sde-display.dtsi create mode 100644 display/bengal-sde.dtsi diff --git a/display/bengal-sde-common.dtsi b/display/bengal-sde-common.dtsi new file mode 100644 index 000000000000..3ec22e548880 --- /dev/null +++ b/display/bengal-sde-common.dtsi @@ -0,0 +1,279 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clock-rate = <0 0 0 300000000 19200000 192000000>; + clock-max-rate = <0 0 0 400000000 19200000 400000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* Enable thermal cooling device */ + #cooling-cells = <2>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <3100000>; + qcom,sde-max-bw-high-kbps = <4000000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <1>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma", "scale"; + qcom,sde-limit-ids= <0x1 0x2 0x4>; + qcom,sde-limit-values = <0x1 4096>, + <0x5 2560>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2600000>, + <0x9 2600000>, + <0x2 2600000>, + <0xa 2600000>, + <0x4 4000000>, + <0xc 3100000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94400 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>, + <0x5e94200 0x100>, + <0x5e94400 0x588>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/bengal-sde-display-common.dtsi b/display/bengal-sde-display-common.dtsi new file mode 100644 index 000000000000..9bad96b9fd90 --- /dev/null +++ b/display/bengal-sde-display-common.dtsi @@ -0,0 +1,58 @@ +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ili988c-dual-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; +}; + +&dsi_ili9881c_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = [ + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 10 04 06 03 02 0a + ]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/bengal-sde-display-idp.dtsi b/display/bengal-sde-display-idp.dtsi new file mode 100644 index 000000000000..20833de7e864 --- /dev/null +++ b/display/bengal-sde-display-idp.dtsi @@ -0,0 +1,9 @@ +#include "bengal-sde-display.dtsi" + +&dsi_ili9881c_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 97 0>; +}; diff --git a/display/bengal-sde-display.dtsi b/display/bengal-sde-display.dtsi new file mode 100644 index 000000000000..582b8e9c125c --- /dev/null +++ b/display/bengal-sde-display.dtsi @@ -0,0 +1,27 @@ +#include "bengal-sde-display-common.dtsi" +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L9A>; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; diff --git a/display/bengal-sde.dtsi b/display/bengal-sde.dtsi new file mode 100644 index 000000000000..700bfc2cf3a9 --- /dev/null +++ b/display/bengal-sde.dtsi @@ -0,0 +1,57 @@ +#include "bengal-sde-common.dtsi" +#include + +&soc { + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_bus", "throttle_clk", "iface_clk", + "core_clk", "vsync_clk", "lut_clk"; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L18A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&VDD_MX_LEVEL>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; +}; From 23bc1a0fcf76cc4b52f1c89a20623fc11f34262e Mon Sep 17 00:00:00 2001 From: Ke Du Date: Thu, 2 Dec 2021 15:16:00 +0530 Subject: [PATCH 299/327] ARM: dts: msm: add pll dts of display for QCS610 Add pll dts of display for QCS610. Change-Id: I91b314f6da814ae0a0e94f8a96b9115ae33ded00 --- display/sm6150-sde-pll.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 display/sm6150-sde-pll.dtsi diff --git a/display/sm6150-sde-pll.dtsi b/display/sm6150-sde-pll.dtsi new file mode 100644 index 000000000000..cfd39040a95e --- /dev/null +++ b/display/sm6150-sde-pll.dtsi @@ -0,0 +1,11 @@ +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94400 { + status = "disabled"; + compatible = "qcom,dsi-phy-v2.0"; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@88e9000 { + status = "disabled"; + compatible = "qcom,dp-display"; + }; +}; From e46d9d672c918f6d2c55b06fe1ee0fb9175ebb0c Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Thu, 2 Dec 2021 20:55:32 +0530 Subject: [PATCH 300/327] ARM: dts: msm: enable dsi phy clamps Add dtsi entry to enable dsi phy clamps during 0p9 collapse Change-Id: Ib0f20ce18ad14dba00539a95f66b5b194b8e2248 --- display/monaco-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 4603e6161032..2dad4e902bfc 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -309,6 +309,7 @@ 00 00 0a 0a 00 00 8a 8a]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-clamp-enable; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; From b88ab66f487ccf909b91a81c55c55869156c955b Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Fri, 3 Dec 2021 03:43:07 +0530 Subject: [PATCH 301/327] ARM: dts: msm: Add 120fps panel support for r66451 on Blair CDP Add 120fps panel support on Blair CDP for r66451. Change-Id: Id9fc229ace2316ce1cf364d0c419762fcaa87f34 --- display/blair-sde-display-cdp.dtsi | 32 ++++++++++++++++++++++++ display/holi-sde-display-cdp-pm6125.dtsi | 23 +++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 7ebe0dbf49b3..658b7d8ab9f9 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -111,6 +111,38 @@ }; }; +&dsi_r66451_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + }; + }; +}; + +&dsi_r66451_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_cmd { /delete-property/ qcom,mdss-dsi-t-clk-post; /delete-property/ qcom,mdss-dsi-t-clk-pre; diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index fc609eccdeb5..b79ffe749e83 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -88,3 +88,26 @@ qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; From 8b323adf9721e621b7cfd8ecb369405bdc4177b8 Mon Sep 17 00:00:00 2001 From: Vishnuvardhan Prodduturi Date: Thu, 16 Dec 2021 17:15:28 +0530 Subject: [PATCH 302/327] ARM: dts: msm: add dispcc clock reference for holi dsi-dsiplay node Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes for cont_splash use case. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I18f0f89174bdf49492b5d9aef1fce3ad90801aa3 --- display/holi-sde-display.dtsi | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 19d406208854..0caafb882c4c 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,4 +1,5 @@ #include "holi-sde-display-common.dtsi" +#include &sde_dsi { clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, @@ -6,10 +7,26 @@ <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; + "shadow_byte_clk0", "shadow_pixel_clk0", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_te_active &disp_pins_default>; From b2c30df35908c996e4491f5d4cc5143f7ded83b0 Mon Sep 17 00:00:00 2001 From: Wanghao Wei Date: Sun, 12 Dec 2021 13:34:25 +0800 Subject: [PATCH 303/327] ARM: dts: msm: change target for bengal/scuba use qrd instead of idp for bengal/scuba according to cdt. Change-Id: I8966e38e5a5f3cc4e2e8c7bba86c5c1959fa2951 --- .../{bengal-sde-display-idp.dtsi => bengal-sde-display-qrd.dtsi} | 0 .../{scuba-sde-display-idp.dtsi => scuba-sde-display-qrd.dtsi} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename display/{bengal-sde-display-idp.dtsi => bengal-sde-display-qrd.dtsi} (100%) rename display/{scuba-sde-display-idp.dtsi => scuba-sde-display-qrd.dtsi} (100%) diff --git a/display/bengal-sde-display-idp.dtsi b/display/bengal-sde-display-qrd.dtsi similarity index 100% rename from display/bengal-sde-display-idp.dtsi rename to display/bengal-sde-display-qrd.dtsi diff --git a/display/scuba-sde-display-idp.dtsi b/display/scuba-sde-display-qrd.dtsi similarity index 100% rename from display/scuba-sde-display-idp.dtsi rename to display/scuba-sde-display-qrd.dtsi From a4ffdd68df823b8723b2648c1b008597a694574b Mon Sep 17 00:00:00 2001 From: Wanghao Wei Date: Sun, 12 Dec 2021 13:38:23 +0800 Subject: [PATCH 304/327] ARM: dts: msm: add support panel ili9881c for bengal/scuba corret power supply, pwm settings and pin control. choice ili9881c as default panel. Change-Id: I526533ac76311d7f0f98cbcb92836ce7ece6c95e --- display/bengal-sde-display-qrd.dtsi | 16 +++++++++++++--- display/scuba-sde-display-qrd.dtsi | 16 +++++++++++++--- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/display/bengal-sde-display-qrd.dtsi b/display/bengal-sde-display-qrd.dtsi index 20833de7e864..3c9f24f0a771 100644 --- a/display/bengal-sde-display-qrd.dtsi +++ b/display/bengal-sde-display-qrd.dtsi @@ -1,9 +1,19 @@ #include "bengal-sde-display.dtsi" &dsi_ili9881c_720p_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 97 0>; + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,platform-reset-gpio = <&ioexp21 2 0>; + qcom,platform-reset-gpio-always-on; + qcom,platform-bklight-en-gpio = <&ioexp21 3 0>; + qcom,platform-en-gpio = <&ioexp22 6 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; }; diff --git a/display/scuba-sde-display-qrd.dtsi b/display/scuba-sde-display-qrd.dtsi index af2fa18ab86f..f3b10fc36965 100644 --- a/display/scuba-sde-display-qrd.dtsi +++ b/display/scuba-sde-display-qrd.dtsi @@ -1,9 +1,19 @@ #include "scuba-sde-display.dtsi" &dsi_ili9881c_720p_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm2250_pwm3 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 97 0>; + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,platform-reset-gpio = <&ioexp21 2 0>; + qcom,platform-reset-gpio-always-on; + qcom,platform-bklight-en-gpio = <&ioexp21 3 0>; + qcom,platform-en-gpio = <&ioexp22 6 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; }; From 8488413598009caffafa8ed4b51c525022c5b9dd Mon Sep 17 00:00:00 2001 From: Ke Du Date: Tue, 28 Dec 2021 09:24:51 +0530 Subject: [PATCH 305/327] ARM: dts: msm: add video mode panel for prairie-iot Add video mode panel hx83112a for prairie-iot. Change-Id: I6080db936f25756fbb936e9e28ac2b7934c9a4af --- ...i-panel-hx83112a-truly-singlemipi-fhd-video.dtsi | 2 +- display/sm6150-sde-display.dtsi | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi b/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi index 9dc1a26207f3..781e3f043b2c 100644 --- a/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi +++ b/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi @@ -1,5 +1,5 @@ &mdss_mdp { - dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video { + dsi_hx83112a_truly_video: dsi_hx83112a_truly_vid_display { qcom,mdss-dsi-panel-name = "hx83112a video mode dsi truly panel"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; diff --git a/display/sm6150-sde-display.dtsi b/display/sm6150-sde-display.dtsi index d15671815cfe..bf200b9e8b81 100644 --- a/display/sm6150-sde-display.dtsi +++ b/display/sm6150-sde-display.dtsi @@ -1,6 +1,7 @@ #include #include "dsi-panel-ili988c-dual-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi" &soc { dsi_panel_pwr_supply: dsi_panel_pwr_supply { @@ -183,3 +184,15 @@ }; }; }; + +&dsi_hx83112a_truly_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; From 6db5cd679aa85e2c601df67336e5a547c8499b5c Mon Sep 17 00:00:00 2001 From: lliu6 Date: Fri, 7 Jan 2022 17:09:27 +0800 Subject: [PATCH 306/327] ARM: dts: msm: optimize panel turn on time Optimize panel turn on time. Change-Id: I7ba614b182ff7e36955ac27b3a52726bdd695ec3 --- display/dsi-panel-rm69090-amoled-178-cmd.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi index 1a2db26c6873..d37841474ebe 100644 --- a/display/dsi-panel-rm69090-amoled-178-cmd.dtsi +++ b/display/dsi-panel-rm69090-amoled-178-cmd.dtsi @@ -59,8 +59,10 @@ 15 01 00 00 00 00 02 51 FF 39 01 00 00 00 00 05 2A 00 10 01 7F 39 01 00 00 00 00 05 2B 00 00 01 BF - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 40 00 02 29 00 + 05 01 00 00 3c 00 02 11 00 + 05 01 00 00 00 00 02 29 00 + 15 01 00 00 00 00 02 FE 00 + 15 01 00 00 00 00 02 53 20 ]; qcom,mdss-dsi-off-command = [ From 1a25a9acd6f65fab7e495b5970f22ebb1e880b6b Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Mon, 24 Jan 2022 12:58:51 +0530 Subject: [PATCH 307/327] ARM: dts: msm: update clocks list for display Add xo clocks in the link clock list and select these clocks for the panel. Change-Id: Ie3e9412e5eb9c4f2064160a75a70990091a2411c --- display/monaco-sde-display.dtsi | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index f9824059c770..9ad8852c98f3 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -1,3 +1,4 @@ +#include #include #include "dsi-panel-rm69090-amoled-178-cmd.dtsi" #include "dsi-panel-rm69090-amoled-178-vid.dtsi" @@ -127,13 +128,15 @@ <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>; - /*TODO: check if MDP clock WA is required*/ + <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0"; + "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", + "xo_byte_clk0", "xo_pixel_clk0"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; @@ -157,9 +160,10 @@ qcom,ulps-enabled; qcom,mdss-dsi-t-clk-post = <0x08>; qcom,mdss-dsi-t-clk-pre = <0x0B>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", /*TODO: check these*/ + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; + "shadow_byte_clk0", "shadow_pixel_clk0", + "xo_byte_clk0", "xo_pixel_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -184,7 +188,8 @@ qcom,mdss-dsi-t-clk-pre = <0x09>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; + "shadow_byte_clk0", "shadow_pixel_clk0", + "xo_byte_clk0", "xo_pixel_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -209,7 +214,8 @@ qcom,mdss-dsi-t-clk-pre = <0x0A>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; + "shadow_byte_clk0", "shadow_pixel_clk0", + "xo_byte_clk0", "xo_pixel_clk0"; qcom,mdss-dsi-display-timings { timing@0 { From 23224c5b83e863408128c6ac7bb953aa17e91de7 Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Mon, 14 Feb 2022 15:57:28 +0530 Subject: [PATCH 308/327] ARM: dts: msm: update clocks list for display Add xo clocks in the link clocks list and select these clocks for the panel. Change-Id: If3fb0e5933ac62dcd166568fd6b6bac005bf318b --- display/sm6150-sde-display.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/display/sm6150-sde-display.dtsi b/display/sm6150-sde-display.dtsi index bf200b9e8b81..2bd78bb00cf2 100644 --- a/display/sm6150-sde-display.dtsi +++ b/display/sm6150-sde-display.dtsi @@ -1,3 +1,4 @@ +#include #include #include "dsi-panel-ili988c-dual-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" @@ -89,10 +90,13 @@ <&mdss_dsi_phy0 BYTE0_SRC_CLK>, <&mdss_dsi_phy0 PIX0_SRC_CLK>, <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, - <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; + "shadow_byte_clk0", "shadow_pixel_clk0", + "xo_byte_clk0", "xo_pixel_clk0"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; @@ -148,7 +152,8 @@ &dsi_ili9881c_720p_video { qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; + "shadow_byte_clk0", "shadow_pixel_clk0", + "xo_byte_clk0", "xo_pixel_clk0"; qcom,mdss-dsi-t-clk-post = <0x0a>; qcom,mdss-dsi-t-clk-pre = <0x21>; qcom,mdss-dsi-display-timings { From 6c89f9cb5e88bf78f0c7b28d7bf771546b72452a Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Wed, 23 Feb 2022 22:09:12 +0530 Subject: [PATCH 309/327] ARM: dts: msm: remove post sleep for ibb regulator Remove post sleep for dummy ibb regulator. Change-Id: I7232ad9ff36b0d32cdf7ba02aac75c6be0612196 --- display/monaco-sde-display.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 9ad8852c98f3..10c048f5e236 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -102,7 +102,6 @@ qcom,supply-max-voltage = <6000000>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <20>; }; }; From 7524b1b53738c887c833fe46e6f5d69ff25a22ba Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Wed, 23 Feb 2022 13:20:05 +0530 Subject: [PATCH 310/327] ARM: dts: msm: disable esd check for rm69090 amoled panel Disable esd check for rm69090 amoled panel. Change-Id: I4c318742877631836977f54e33e1962cf01a2d82 --- display/monaco-sde-display.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 9ad8852c98f3..19aaa06dd81b 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -170,7 +170,6 @@ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,esd-check-enabled; qcom,mdss-dsi-display-timings { timing@0 { From fbe1c5860814cfd782d38f793fa723f15151d2c7 Mon Sep 17 00:00:00 2001 From: Yojana Juadi Date: Tue, 15 Mar 2022 18:14:40 +0530 Subject: [PATCH 311/327] ARM: dts: msm: release excess memory reserved for ramdump in yupik This change reserves 8 MB memory for ramdump and releases 28MB. Change-Id: Ie3d7530be37b75821add3ec7b57cef7ca1fea986 --- display/yupik-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 43f616b8e540..ec6310d01efd 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -3,7 +3,7 @@ &soc { disp_rdump_memory: disp_rdump_region@e1000000 { - reg = <0xe1000000 0x02300000>; + reg = <0xe1000000 0x00800000>; label = "disp_rdump_region"; }; From 1ea116df72ee040a4852a0692e16d92c88ec53c4 Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Tue, 15 Mar 2022 00:23:38 +0530 Subject: [PATCH 312/327] ARM: dts: msm: enable rsc hibernation Add dtsi entry to enable rsc hibernate support. Change-Id: I0ff9b37e8d7621234afd27f3103bb3defb97cbb8 --- bindings/sde-rsc.txt | 2 +- display/sm6150-sde.dtsi | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/sde-rsc.txt b/bindings/sde-rsc.txt index 3af5629ca467..9b9fdbd3ec4e 100644 --- a/bindings/sde-rsc.txt +++ b/bindings/sde-rsc.txt @@ -26,7 +26,7 @@ Optional properties: for particular chipset. These paths must be defined after rt-paths in "qcom,msm-bus,vectors-KBps" vector request. - +- qcom,sde-rsc-need-hw-reinit: Boolean used to enable hw reinit. Bus Scaling Subnodes: - qcom,sde-data-bus: Property to provide Bus scaling for data bus access for sde blocks. diff --git a/display/sm6150-sde.dtsi b/display/sm6150-sde.dtsi index ddb27cb9fbcc..1ba217fbf89f 100644 --- a/display/sm6150-sde.dtsi +++ b/display/sm6150-sde.dtsi @@ -207,6 +207,7 @@ <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <2>; + qcom,sde-rsc-need-hw-reinit; vdd-supply = <&mdss_core_gdsc>; clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, From c77fa7bf045dfb8662c3db6f4770285811165a94 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Thu, 14 Apr 2022 02:22:43 +0530 Subject: [PATCH 313/327] ARM: dts: msm: add needs-clk-src-reset flag for monaco This will enable resetting of dsi clock source, while entering and resuming from pm_suspend. Change-Id: Ia92f4664529c23b5ff6e61df060f6c0a3e7ceb5c --- bindings/sde-dsi.txt | 1 + display/monaco-sde-display.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt index 56d13ad81bb2..c8e86b637ddc 100644 --- a/bindings/sde-dsi.txt +++ b/bindings/sde-dsi.txt @@ -129,3 +129,4 @@ Optional properties: to be programmed for the SSC. - qcom,ssc-ppm: Integer property to specify the Parts per Million value of SSC. +- qcom,needs-clk-src-reset: Do clk src reset during pm_suspend and pm_resume. diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 74a8505cbf3c..84db77eb7c22 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -142,6 +142,7 @@ qcom,platform-te-gpio = <&tlmm 73 0>; qcom,panel-te-source = <0>; + qcom,needs-clk-src-reset; vddio-supply = <&L21A>; ibb-supply = <&display_panel_ibb>; qcom,mdp = <&mdss_mdp>; From 321be6451bb5f06662cc29985be7fb25e01c2c0f Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Thu, 21 Apr 2022 18:09:36 +0530 Subject: [PATCH 314/327] ARM: dts: msm: skip panel power off for rm6d030 amoled panel Add dtsi entry to skip panel power off for rm6d030 amoled panel. Change-Id: I57f2186fbf54f2686f2d4eabe9a778ab1e5d093f --- bindings/mdss-dsi-panel.txt | 1 + display/monaco-sde-display.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index f2554a75ed98..8a5815f701e3 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -445,6 +445,7 @@ Optional properties: height values. This property is specified per timing node to support resolution's alignment restrictions. - qcom,esd-check-enabled: Boolean used to enable ESD recovery feature. +- qcom,skip-panel-power-off: Boolean used to skip panel power off. - qcom,mdss-dsi-panel-status-command: A byte stream formed by multiple dcs packets based on qcom dsi controller protocol, to read the panel status. This value is used to kick in the ESD recovery. diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 84db77eb7c22..0f664b456090 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -209,6 +209,7 @@ &dsi_rm6d030_amoled_cmd { qcom,ulps-enabled; + qcom,skip-panel-power-off; qcom,mdss-dsi-t-clk-post = <0x07>; qcom,mdss-dsi-t-clk-pre = <0x0A>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", From 00d6964d82acf65918aecc9bd404d554f740591c Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Fri, 20 May 2022 18:07:13 +0530 Subject: [PATCH 315/327] ARM: dts: msm: update panel regulator load values Update panel regulator enable load and ulp load values. Change-Id: I51f78729e06cd8c9b1b1b18505a0eaa7403b6515 --- display/monaco-sde-display.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 0f664b456090..2b29909e7765 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -90,8 +90,9 @@ qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <2000000>; - qcom,supply-enable-load = <62000>; + qcom,supply-enable-load = <4000>; qcom,supply-disable-load = <80>; + qcom,supply-ulp-load = <100>; qcom,supply-post-on-sleep = <20>; }; From b848b4731b3eed5ca607277135df28d72770d695 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Thu, 28 Apr 2022 01:06:47 +0530 Subject: [PATCH 316/327] ARM: dts: msm: add needs-ctrl-vreg-disable for monaco This will disable DSI ctrl regulator during pm_suspend and enables back during pm_resume. Change-Id: I3a00b412485b85339ccc8a3f6f11c6a9380ecfd5 --- bindings/sde-dsi.txt | 1 + display/monaco-sde-display.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt index c8e86b637ddc..62fcf1b125ba 100644 --- a/bindings/sde-dsi.txt +++ b/bindings/sde-dsi.txt @@ -130,3 +130,4 @@ Optional properties: - qcom,ssc-ppm: Integer property to specify the Parts per Million value of SSC. - qcom,needs-clk-src-reset: Do clk src reset during pm_suspend and pm_resume. +- qcom,needs-ctrl-vreg-disable: Disable dsi ctrl regulator pm_suspend. diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi index 2b29909e7765..1b044cc465cd 100644 --- a/display/monaco-sde-display.dtsi +++ b/display/monaco-sde-display.dtsi @@ -144,6 +144,7 @@ qcom,platform-te-gpio = <&tlmm 73 0>; qcom,panel-te-source = <0>; qcom,needs-clk-src-reset; + qcom,needs-ctrl-vreg-disable; vddio-supply = <&L21A>; ibb-supply = <&display_panel_ibb>; qcom,mdp = <&mdss_mdp>; From f7acea5720b96fb24fb5bcbcb2f56eafd0e96105 Mon Sep 17 00:00:00 2001 From: Kai Xing Date: Wed, 18 May 2022 08:21:18 +0530 Subject: [PATCH 317/327] ARM: dts: msm: update display node in kona update pll dts of display for kona Change-Id: I56c66af2c2f83f6427fa2f92cd88ab8c82c19324 --- display/kona-sde-display.dtsi | 42 ++++++----- display/kona-sde.dtsi | 130 ++++++++++++++-------------------- 2 files changed, 78 insertions(+), 94 deletions(-) diff --git a/display/kona-sde-display.dtsi b/display/kona-sde-display.dtsi index 00c36cf8e166..aa612e99cbb1 100644 --- a/display/kona-sde-display.dtsi +++ b/display/kona-sde-display.dtsi @@ -37,6 +37,14 @@ }; }; +&qupv3_se15_i2c { + status = "ok"; + fsa4480: fsa4480@43 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x43>; + }; +}; + &soc { ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; @@ -168,18 +176,18 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll PCLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>, - <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, - <&mdss_dsi1_pll PCLK_SRC_1_CLK>, - <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", @@ -198,8 +206,6 @@ vddio-supply = <&pm8150_l14>; vdd-supply = <&pm8150a_l11>; avdd-supply = <&display_panel_avdd>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; @@ -212,10 +218,10 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, + <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1"; diff --git a/display/kona-sde.dtsi b/display/kona-sde.dtsi index 7c332fb5b40e..c2b758b8ac14 100644 --- a/display/kona-sde.dtsi +++ b/display/kona-sde.dtsi @@ -30,6 +30,9 @@ clock-max-rate = <0 0 0 0 460000000 19200000 460000000 460000000>; + /* Enable thermal cooling device */ + #cooling-cells = <2>; + mmcx-supply = <&VDD_MMCX_LEVEL>; /* interrupt config */ @@ -216,6 +219,16 @@ qcom,sde-secure-sid-mask = <0x4000821>; + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; @@ -268,43 +281,6 @@ }; }; - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&apps_smmu 0x820 0x402>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-earlymap; /* for cont-splash */ - }; - - smmu_sde_sec: qcom,smmu_sde_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x400>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-vmid = <0xa>; - }; - - /* data and reg bus scale settings */ - qcom,sde-data-bus { - qcom,msm-bus,name = "mdss_sde"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>; - }; - - qcom,sde-reg-bus { - qcom,msm-bus,name = "mdss_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 150000>, - <1 590 0 300000>; - }; }; sde_dp: qcom,dp_display@ae90000 { @@ -341,9 +317,9 @@ <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&sde_dp DP_VCO_DIVIDED_CLK_SRC_MUX>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&sde_dp DP_VCO_DIVIDED_CLK_SRC_MUX>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", @@ -432,39 +408,10 @@ <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; - /* data and reg bus scale settings */ - qcom,sde-data-bus { - qcom,msm-bus,name = "disp_rsc_mnoc_llcc"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <20003 20513 0 0>, <20004 20513 0 0>, - <20003 20513 0 6400000>, <20004 20513 0 6400000>, - <20003 20513 0 6400000>, <20004 20513 0 6400000>; - }; - - qcom,sde-ebi-bus { - qcom,msm-bus,name = "disp_rsc_ebi"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <20000 20512 0 0>, - <20000 20512 0 6400000>, - <20000 20512 0 6400000>; - }; - - qcom,sde-reg-bus { - qcom,msm-bus,name = "disp_rsc_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 150000>, - <1 590 0 300000>; - }; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0","qcom,sde-ebi-bus"; }; mdss_rotator: qcom,mdss_rotator@aea8800 { @@ -639,9 +586,15 @@ compatible = "qcom,dsi-phy-v4.1"; label = "dsi-phy-0"; cell-index = <0>; + #clock-cells = <1>; reg = <0xae94400 0x7c0>, - <0xae94200 0x100>; - reg-names = "dsi_phy", "dyn_refresh_base"; + <0xae94200 0x100>, + <0xae94900 0x260>, + <0xae94400 0x800>, + <0xaf03000 0x8>; + reg-names = "dsi_phy", "dyn_refresh_base", "pll_base", "phy_base", "gdsc_base"; + pll-label = "dsi_pll_7nm_v4_1"; + memory-region = <&dfps_data_memory>; vdda-0p9-supply = <&pm8150_l5>; qcom,platform-strength-ctrl = [55 03 55 03 @@ -654,6 +607,8 @@ 00 00 0a 0a 00 00 8a 8a]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; @@ -672,9 +627,14 @@ compatible = "qcom,dsi-phy-v4.1"; label = "dsi-phy-1"; cell-index = <1>; + #clock-cells = <1>; reg = <0xae96400 0x7c0>, - <0xae96200 0x100>; - reg-names = "dsi_phy", "dyn_refresh_base"; + <0xae96200 0x100>, + <0xae96900 0x260>, + <0xae96400 0x800>, + <0xaf03000 0x8>; + reg-names = "dsi_phy", "dyn_refresh_base", "pll_base", "phy_base", "gdsc_base"; + pll-label = "dsi_pll_7nm_v4_1"; vdda-0p9-supply = <&pm8150_l5>; qcom,platform-strength-ctrl = [55 03 55 03 @@ -687,6 +647,8 @@ 00 00 0a 0a 00 00 0a 0a 00 00 8a 8a]; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; @@ -701,4 +663,20 @@ }; }; + smmu_sde_sec: qcom,smmu_sde_sec_cb { + status = "ok"; + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x821 0x400>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x820 0x402>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; }; From 5615244fe7d5dcd131016ccb702e4cf7424f60da Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Fri, 16 Sep 2022 12:37:42 +0530 Subject: [PATCH 318/327] ARM: dts: msm: split mdp interconnect path for proper ib votes The following change will split the interconnect path to accommodate sperate ib votes for mnoc and ebi_ib path. Change-Id: Ie374c8ef6e28b8339c425b8085a51998fca9f483 --- display/yupik-sde.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index ec6310d01efd..5b36e34752a2 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -179,10 +179,11 @@ "lut_clk", "rot_clk"; /* data and reg bus scale settings */ - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + interconnects = <&mmss_noc MASTER_MDP0 &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-dspp-ltm-version = <0x00010001>; From 9cff5d1be57b27b955a1a6bae75cc31fd9cbcc64 Mon Sep 17 00:00:00 2001 From: Zhiqiang Liu Date: Thu, 4 Aug 2022 17:29:53 +0800 Subject: [PATCH 319/327] ARM: dts: msm: add display device tree for kernel-fe Add display device tree for kernel frontend. Change-Id: Ib8ad42d69e35046c6e25d5a9c39eaa1a97cadb84 --- display/quin-vm-display-la.dtsi | 18 +++++++++++++ display/quin-vm-display-la1.dtsi | 18 +++++++++++++ display/quin-vm-display-lv.dtsi | 11 ++++++++ display/quin-vm-display-lxc.dtsi | 45 ++++++++++++++++++++++++++++++++ display/quin-vm-display.dtsi | 18 +++++++++++++ 5 files changed, 110 insertions(+) create mode 100644 display/quin-vm-display-la.dtsi create mode 100644 display/quin-vm-display-la1.dtsi create mode 100644 display/quin-vm-display-lv.dtsi create mode 100644 display/quin-vm-display-lxc.dtsi create mode 100644 display/quin-vm-display.dtsi diff --git a/display/quin-vm-display-la.dtsi b/display/quin-vm-display-la.dtsi new file mode 100644 index 000000000000..bd5879cc988c --- /dev/null +++ b/display/quin-vm-display-la.dtsi @@ -0,0 +1,18 @@ +&soc { + sde_cfg: qcom,sde-cfg { + compatible = "qcom,sde-cfg"; + + qcom,sde-sub-cfg@0 { + reg = <0>; + wfd_kms: qcom,wfd_kms@0 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7815"; + }; + + qcom,sde_kms_hyp@ae00000 { + compatible = "qcom,sde-kms-hyp"; + qcom,kms = <&wfd_kms>; + }; + }; + }; +}; diff --git a/display/quin-vm-display-la1.dtsi b/display/quin-vm-display-la1.dtsi new file mode 100644 index 000000000000..ac331033dbcb --- /dev/null +++ b/display/quin-vm-display-la1.dtsi @@ -0,0 +1,18 @@ +&soc { + sde_cfg: qcom,sde-cfg { + compatible = "qcom,sde-cfg"; + + qcom,sde-sub-cfg@0 { + reg = <0>; + wfd_kms: qcom,wfd_kms@0 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7816"; + }; + + qcom,sde_kms_hyp@ae00000 { + compatible = "qcom,sde-kms-hyp"; + qcom,kms = <&wfd_kms>; + }; + }; + }; +}; diff --git a/display/quin-vm-display-lv.dtsi b/display/quin-vm-display-lv.dtsi new file mode 100644 index 000000000000..a67b269801aa --- /dev/null +++ b/display/quin-vm-display-lv.dtsi @@ -0,0 +1,11 @@ +&soc { + wfd_kms: qcom,wfd_kms@0 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7816"; + }; + + sde_kms_hyp: qcom,sde_kms_hyp@ae00000 { + compatible = "qcom,sde-kms-hyp"; + qcom,kms = <&wfd_kms>; + }; +}; diff --git a/display/quin-vm-display-lxc.dtsi b/display/quin-vm-display-lxc.dtsi new file mode 100644 index 000000000000..3d387bf24d7c --- /dev/null +++ b/display/quin-vm-display-lxc.dtsi @@ -0,0 +1,45 @@ +&soc { + wfd_kms: qcom,wfd_kms@0 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7816"; + }; + + sde_kms_hyp: qcom,sde_kms_hyp@ae00000 { + compatible = "qcom,sde-kms-hyp"; + qcom,dev-name = "msm_drm"; + qcom,kms = <&wfd_kms>; + }; + + wfd_kms1: qcom,wfd_kms@1 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7818"; + }; + + sde_kms_hyp1: qcom,sde_kms_hyp@ae10000 { + compatible = "qcom,sde-kms-hyp"; + qcom,dev-name = "msm_drm1"; + qcom,kms = <&wfd_kms1>; + }; + + wfd_kms2: qcom,wfd_kms@2 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7819"; + }; + + sde_kms_hyp2: qcom,sde_kms_hyp@ae20000 { + compatible = "qcom,sde-kms-hyp"; + qcom,dev-name = "msm_drm2"; + qcom,kms = <&wfd_kms2>; + }; + + wfd_kms3: qcom,wfd_kms@3 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7815"; + }; + + sde_kms_hyp3: qcom,sde_kms_hyp@ae30000 { + compatible = "qcom,sde-kms-hyp"; + qcom,dev-name = "msm_drm3"; + qcom,kms = <&wfd_kms3>; + }; +}; diff --git a/display/quin-vm-display.dtsi b/display/quin-vm-display.dtsi new file mode 100644 index 000000000000..bd5879cc988c --- /dev/null +++ b/display/quin-vm-display.dtsi @@ -0,0 +1,18 @@ +&soc { + sde_cfg: qcom,sde-cfg { + compatible = "qcom,sde-cfg"; + + qcom,sde-sub-cfg@0 { + reg = <0>; + wfd_kms: qcom,wfd_kms@0 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7815"; + }; + + qcom,sde_kms_hyp@ae00000 { + compatible = "qcom,sde-kms-hyp"; + qcom,kms = <&wfd_kms>; + }; + }; + }; +}; From 8b3390956ca15606ac993a1369c4e099779d46de Mon Sep 17 00:00:00 2001 From: Yao Zhao Date: Thu, 29 Sep 2022 12:20:33 +0530 Subject: [PATCH 320/327] ARM: dts: msm: Add the qrd-v3 LCD support for qrb4210 Add new and old LCd support with qrd-v3 dts. Change-Id: I99f6a6c14b2eafc98c8ac7ee5cd219c7766eff28 --- display/bengal-sde-display-common-v3.dtsi | 25 +++++++++++++++++++++++ display/bengal-sde-display-qrd-v3.dtsi | 19 +++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 display/bengal-sde-display-common-v3.dtsi create mode 100644 display/bengal-sde-display-qrd-v3.dtsi diff --git a/display/bengal-sde-display-common-v3.dtsi b/display/bengal-sde-display-common-v3.dtsi new file mode 100644 index 000000000000..3a6d87a27d43 --- /dev/null +++ b/display/bengal-sde-display-common-v3.dtsi @@ -0,0 +1,25 @@ +#include "dsi-panel-ili9881p-720-video.dtsi" + +&soc { + sde_dsi: qcom,dsi-display-primary { + qcom,dsi-default-panel = <&dsi_ili9881p_720p_video>; + }; +}; + +&dsi_ili9881p_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x12>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = [ + 00 14 05 05 13 1F 05 + 05 06 02 04 00 12 0A + ]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/bengal-sde-display-qrd-v3.dtsi b/display/bengal-sde-display-qrd-v3.dtsi new file mode 100644 index 000000000000..d548f012f26f --- /dev/null +++ b/display/bengal-sde-display-qrd-v3.dtsi @@ -0,0 +1,19 @@ +#include "bengal-sde-display-common-v3.dtsi" + +&dsi_ili9881p_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,platform-reset-gpio = <&ioexp21 2 0>; + qcom,platform-reset-gpio-always-on; + qcom,platform-bklight-en-gpio = <&ioexp21 3 0>; + qcom,platform-en-gpio = <&ioexp22 6 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ili9881p_720p_video>; +}; From 545c589f4a08d37db770fb68d9ef736a97d44af7 Mon Sep 17 00:00:00 2001 From: Yao Zhao Date: Tue, 18 Oct 2022 12:53:12 +0530 Subject: [PATCH 321/327] ARM: dts: msm: Add the qrd-v3 LCD support for qrb2210 Add new and old LCD support with qrd-v3 dts. Change-Id: I5bf0988ee7618e9ca2306cab7b53b68d881b352f --- display/scuba-sde-display-common-v3.dtsi | 25 ++++++++++++++++++++++++ display/scuba-sde-display-qrd-v3.dtsi | 19 ++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 display/scuba-sde-display-common-v3.dtsi create mode 100644 display/scuba-sde-display-qrd-v3.dtsi diff --git a/display/scuba-sde-display-common-v3.dtsi b/display/scuba-sde-display-common-v3.dtsi new file mode 100644 index 000000000000..dfe3ee08f340 --- /dev/null +++ b/display/scuba-sde-display-common-v3.dtsi @@ -0,0 +1,25 @@ +#include "dsi-panel-ili9881p-720-video.dtsi" + +&soc { + sde_dsi: qcom,dsi-display-primary { + qcom,dsi-default-panel = <&dsi_ili9881p_720p_video>; + }; +}; + +&dsi_ili9881p_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = [ + 00 14 05 05 13 1F 05 + 05 06 02 04 00 12 0A + ]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/scuba-sde-display-qrd-v3.dtsi b/display/scuba-sde-display-qrd-v3.dtsi new file mode 100644 index 000000000000..ac3a39f0c811 --- /dev/null +++ b/display/scuba-sde-display-qrd-v3.dtsi @@ -0,0 +1,19 @@ +#include "scuba-sde-display-common-v3.dtsi" + +&dsi_ili9881p_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm2250_pwm3 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,platform-reset-gpio = <&ioexp21 2 0>; + qcom,platform-reset-gpio-always-on; + qcom,platform-bklight-en-gpio = <&ioexp21 3 0>; + qcom,platform-en-gpio = <&ioexp22 6 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ili9881p_720p_video>; +}; From 64bd324989b856a867bea7c0669adbab5a7cc6b2 Mon Sep 17 00:00:00 2001 From: Yao Zhao Date: Tue, 18 Oct 2022 13:05:32 +0530 Subject: [PATCH 322/327] ARM: dts: msm: Add a new file about LCD support for qrbx210 Add new file dsi-panel-ili9881p-720-video.dtsi about qrd-v3 LCD support for qrbx210. Change-Id: I2585e8d1be8ea9ef7f3cddce7d1fd0d6c844a05c --- display/dsi-panel-ili9881p-720-video.dtsi | 236 ++++++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 display/dsi-panel-ili9881p-720-video.dtsi diff --git a/display/dsi-panel-ili9881p-720-video.dtsi b/display/dsi-panel-ili9881p-720-video.dtsi new file mode 100644 index 000000000000..960e05a2b482 --- /dev/null +++ b/display/dsi-panel-ili9881p-720-video.dtsi @@ -0,0 +1,236 @@ +&mdss_mdp { + dsi_ili9881p_720p_video: qcom,mdss_dsi_ili9881c_720p_video { + qcom,mdss-dsi-panel-name = "ILI9881P 720p video signal panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0x3ff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-pan-physical-width-dimension = <62>; + qcom,mdss-pan-physical-height-dimension = <110>; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <200>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <24>; + qcom,mdss-dsi-v-front-porch = <24>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 FF 98 81 05 + 39 01 00 00 00 00 02 B2 70 + 39 01 00 00 00 00 02 03 00 + 39 01 00 00 00 00 02 04 2c + 39 01 00 00 00 00 02 4C 11 + 39 01 00 00 00 00 02 1A 50 + 39 01 00 00 00 00 02 38 A0 + 39 01 00 00 00 00 02 4D 22 + 39 01 00 00 00 00 02 54 28 + 39 01 00 00 00 00 02 55 25 + 39 01 00 00 00 00 02 1B 09 + 39 01 00 00 00 00 02 26 0E + 39 01 00 00 00 00 02 78 01 + 39 01 00 00 00 00 02 A9 C0 + 39 01 00 00 00 00 02 B1 70 + 39 01 00 00 00 00 02 1E 11 + 39 01 00 00 00 00 04 FF 98 81 02 + 39 01 00 00 00 00 02 01 50 + 39 01 00 00 00 00 02 15 10 + 39 01 00 00 00 00 02 42 01 + 39 01 00 00 00 00 02 44 01 + 39 01 00 00 00 00 15 57 00 1B 2B 13 16 29 1E 1F 90 1E 2B 79 18 12 41 1E 26 4E 5D 2C + 39 01 00 00 00 00 15 6B 00 1B 2B 13 16 29 1E 1F 90 1E 2B 79 18 12 41 1E 26 4E 5D 2C + 39 01 00 00 00 00 04 FF 98 81 01 + 39 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 02 02 00 + 39 01 00 00 00 00 02 03 56 + 39 01 00 00 00 00 02 04 13 + 39 01 00 00 00 00 02 05 13 + 39 01 00 00 00 00 02 06 0a + 39 01 00 00 00 00 02 07 05 + 39 01 00 00 00 00 02 08 05 + 39 01 00 00 00 00 02 09 1D + 39 01 00 00 00 00 02 0a 01 + 39 01 00 00 00 00 02 0b 00 + 39 01 00 00 00 00 02 0c 3F + 39 01 00 00 00 00 02 0d 29 + 39 01 00 00 00 00 02 0e 29 + 39 01 00 00 00 00 02 0f 1D + 39 01 00 00 00 00 02 10 1D + 39 01 00 00 00 00 02 11 00 + 39 01 00 00 00 00 02 12 00 + 39 01 00 00 00 00 02 13 08 + 39 01 00 00 00 00 02 14 08 + 39 01 00 00 00 00 02 15 00 + 39 01 00 00 00 00 02 16 00 + 39 01 00 00 00 00 02 17 00 + 39 01 00 00 00 00 02 18 00 + 39 01 00 00 00 00 02 19 00 + 39 01 00 00 00 00 02 1a 00 + 39 01 00 00 00 00 02 1b 00 + 39 01 00 00 00 00 02 1c 00 + 39 01 00 00 00 00 02 1d 00 + 39 01 00 00 00 00 02 1e 40 + 39 01 00 00 00 00 02 1f 88 + 39 01 00 00 00 00 02 20 08 + 39 01 00 00 00 00 02 21 01 + 39 01 00 00 00 00 02 22 00 + 39 01 00 00 00 00 02 23 00 + 39 01 00 00 00 00 02 24 00 + 39 01 00 00 00 00 02 25 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 27 00 + 39 01 00 00 00 00 02 28 33 + 39 01 00 00 00 00 02 29 03 + 39 01 00 00 00 00 02 2a 00 + 39 01 00 00 00 00 02 2b 00 + 39 01 00 00 00 00 02 2c 00 + 39 01 00 00 00 00 02 2d 00 + 39 01 00 00 00 00 02 2e 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 30 00 + 39 01 00 00 00 00 02 31 00 + 39 01 00 00 00 00 02 32 00 + 39 01 00 00 00 00 02 33 00 + 39 01 00 00 00 00 02 34 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 37 00 + 39 01 00 00 00 00 02 38 00 + 39 01 00 00 00 00 02 39 0f + 39 01 00 00 00 00 02 3a 2a + 39 01 00 00 00 00 02 3b 00 + 39 01 00 00 00 00 02 3c 00 + 39 01 00 00 00 00 02 3d 00 + 39 01 00 00 00 00 02 3e 00 + 39 01 00 00 00 00 02 3f 00 + 39 01 00 00 00 00 02 40 00 + 39 01 00 00 00 00 02 41 e0 + 39 01 00 00 00 00 02 42 40 + 39 01 00 00 00 00 02 43 0f + 39 01 00 00 00 00 02 44 11 + 39 01 00 00 00 00 02 45 a8 + 39 01 00 00 00 00 02 46 00 + 39 01 00 00 00 00 02 47 08 + 39 01 00 00 00 00 02 48 00 + 39 01 00 00 00 00 02 49 01 + 39 01 00 00 00 00 02 4a 00 + 39 01 00 00 00 00 02 4b 00 + 39 01 00 00 00 00 02 4c b2 + 39 01 00 00 00 00 02 4d 22 + 39 01 00 00 00 00 02 4e 01 + 39 01 00 00 00 00 02 4f f7 + 39 01 00 00 00 00 02 50 29 + 39 01 00 00 00 00 02 51 72 + 39 01 00 00 00 00 02 52 25 + 39 01 00 00 00 00 02 53 b2 + 39 01 00 00 00 00 02 54 22 + 39 01 00 00 00 00 02 55 22 + 39 01 00 00 00 00 02 56 22 + 39 01 00 00 00 00 02 57 a2 + 39 01 00 00 00 00 02 58 22 + 39 01 00 00 00 00 02 59 01 + 39 01 00 00 00 00 02 5a e6 + 39 01 00 00 00 00 02 5b 28 + 39 01 00 00 00 00 02 5c 62 + 39 01 00 00 00 00 02 5d 24 + 39 01 00 00 00 00 02 5e a2 + 39 01 00 00 00 00 02 5f 22 + 39 01 00 00 00 00 02 60 22 + 39 01 00 00 00 00 02 61 22 + 39 01 00 00 00 00 02 62 ee + 39 01 00 00 00 00 02 63 02 + 39 01 00 00 00 00 02 64 0b + 39 01 00 00 00 00 02 65 02 + 39 01 00 00 00 00 02 66 02 + 39 01 00 00 00 00 02 67 01 + 39 01 00 00 00 00 02 68 00 + 39 01 00 00 00 00 02 69 0f + 39 01 00 00 00 00 02 6a 07 + 39 01 00 00 00 00 02 6b 55 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 02 + 39 01 00 00 00 00 02 6e 5b + 39 01 00 00 00 00 02 6f 59 + 39 01 00 00 00 00 02 70 02 + 39 01 00 00 00 00 02 71 02 + 39 01 00 00 00 00 02 72 57 + 39 01 00 00 00 00 02 73 02 + 39 01 00 00 00 00 02 74 02 + 39 01 00 00 00 00 02 75 02 + 39 01 00 00 00 00 02 76 02 + 39 01 00 00 00 00 02 77 02 + 39 01 00 00 00 00 02 78 02 + 39 01 00 00 00 00 02 79 02 + 39 01 00 00 00 00 02 7a 0a + 39 01 00 00 00 00 02 7b 02 + 39 01 00 00 00 00 02 7c 02 + 39 01 00 00 00 00 02 7d 01 + 39 01 00 00 00 00 02 7e 00 + 39 01 00 00 00 00 02 7f 0e + 39 01 00 00 00 00 02 80 06 + 39 01 00 00 00 00 02 81 54 + 39 01 00 00 00 00 02 82 02 + 39 01 00 00 00 00 02 83 02 + 39 01 00 00 00 00 02 84 5a + 39 01 00 00 00 00 02 85 58 + 39 01 00 00 00 00 02 86 02 + 39 01 00 00 00 00 02 87 02 + 39 01 00 00 00 00 02 88 56 + 39 01 00 00 00 00 02 89 02 + 39 01 00 00 00 00 02 8a 02 + 39 01 00 00 00 00 02 8b 02 + 39 01 00 00 00 00 02 8c 02 + 39 01 00 00 00 00 02 8d 02 + 39 01 00 00 00 00 02 8e 02 + 39 01 00 00 00 00 02 8f 44 + 39 01 00 00 00 00 02 90 44 + 39 01 00 00 00 00 04 FF 98 81 06 + 39 01 00 00 00 00 02 01 03 + 39 01 00 00 00 00 02 2B 0A + 39 01 00 00 00 00 02 04 70 + 39 01 00 00 00 00 02 C0 CF + 39 01 00 00 00 00 02 C1 2A + 39 01 00 00 00 00 04 FF 98 81 00 + 05 01 00 00 FF 00 01 11 + 05 01 00 00 28 00 01 29 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 36 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; + From da9856204e547d7161d645647c945ee9501d5cb7 Mon Sep 17 00:00:00 2001 From: jinjlei Date: Tue, 13 Dec 2022 00:45:32 +0800 Subject: [PATCH 323/327] bindings: Documentation: add sde-cfg sde-hyp bindings documentation Add sde-cfg sde-hyp bindings documentation. Change-Id: I0062be46ce4c3097aa99156cef1f06717b1192fd --- bindings/sde-cfg.txt | 76 ++++++++++++++++++++++++++++++++++++++++++++ bindings/sde-hyp.txt | 30 +++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 bindings/sde-cfg.txt create mode 100644 bindings/sde-hyp.txt diff --git a/bindings/sde-cfg.txt b/bindings/sde-cfg.txt new file mode 100644 index 000000000000..34a467b8d7bd --- /dev/null +++ b/bindings/sde-cfg.txt @@ -0,0 +1,76 @@ +QTI Snapdragon Display Engine (SDE) configuration driver + +Required properties: +- compatible: "qcom,sde-cfg" + +Each child node represents a configuration, with properties: +- reg: A u32 property defines the configuration id. +- connectors: A phandle array property defines sub devices to be added. + +Each child node can have multiple sub-child nodes. Each sub-child node +represents a device to be created for that configuration. + +Configuration N will be selected by boot paramerter msm_cfg.cfg_sel=. +Default configuration is child node with reg = <0>. + +Example: + +/ { + ... + + sde_cfg: qcom,sde-cfg { + compatible = "qcom,sde-cfg"; + + qcom,sde-sub-cfg@0 { + reg = <0>; + connectors = <&dsi_dp1>; + + dsi_dp1: qcom,dsi-display@1 { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", "xo_clk"; + + qcom,dsi-display-list = + <&dsi_anx_7625_1>; + }; + }; + + qcom,sde-sub-cfg@1 { + reg = <1>; + connectors = ; + + dsi_dp2: qcom,dsi-display@2 { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", "xo_clk"; + + qcom,dsi-display-list = + <&dsi_anx_7625_2>; + }; + }; + }; +}; + +&mdss_mdp { + connectors = <&sde_cfg>; +}; diff --git a/bindings/sde-hyp.txt b/bindings/sde-hyp.txt new file mode 100644 index 000000000000..aed30e128be8 --- /dev/null +++ b/bindings/sde-hyp.txt @@ -0,0 +1,30 @@ +Qualcomm Technologies, Inc. SDE KMS HYP + +Snapdragon Display Engine HYP registers with the Linux DRM/KMS framework to +facilitate DRM driver creation, publishing /dev/dri/card0, and sending +VBlank and Page Flip events to User Space listeners. + +Required properties +- compatible: Must be "qcom,sde-kms-hyp" +- qcom,kms: Component phandle list + +Component phandle list must include one KMS backend. In the driver WFD KMS +is provided as OpenWFD backend. + +Required properties for OpenWFD backend: +- compatible: Must be "qcom,wfd-kms" +- qcom,client-id: A four character string that is converted to a u32. It's + understood as a hex value, if compatible (i.e. "7816"). + Otherwise, it is treated as a FourCC sequence code + (i.e. "LV01"). + +Example: + wfd_kms: qcom,wfd_kms@0 { + compatible = "qcom,wfd-kms"; + qcom,client-id = "7816"; + }; + + sde_kms_hyp: qcom,sde_kms_hyp@900000 { + compatible = "qcom,sde-kms-hyp"; + qcom,kms = <&wfd_kms>; + }; From 8bf9953e5597b0201c95850c186a4d24ad0dffc5 Mon Sep 17 00:00:00 2001 From: Shudan Liu Date: Tue, 7 Feb 2023 20:33:22 +0800 Subject: [PATCH 324/327] ARM: dts: msm: Add HDMI display support for yupik QCS6490 DK Add display support for yupik QCS6490 Open Dev Kit. Change-Id: I5ea650d6fb4686ac6c2253bdc633e26eb4681fcb --- display/yupik-sde-display-common.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index dc79e9e90769..4d54db9686ed 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -10,6 +10,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd-cphy.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi" #include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" #include &soc { @@ -349,3 +350,9 @@ }; }; }; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; +}; From c4391c92bd194223d59117d8e13bc78100b6f639 Mon Sep 17 00:00:00 2001 From: Zhenbin Tan Date: Wed, 24 Aug 2022 16:39:03 +0800 Subject: [PATCH 325/327] ARM: dts: msm: Add 4k HDMI display support for RB5 Add 4k resolution for MIPI-HDMI ext bridge IC on RB5. Change-Id: I46343889c068f54abf87ae9d2ee36a13c2a19f93 --- display/dsi-panel-ext-bridge-4k-video.dtsi | 45 ++++++++++++++++++++++ display/kona-sde-display.dtsi | 13 +++++++ 2 files changed, 58 insertions(+) create mode 100644 display/dsi-panel-ext-bridge-4k-video.dtsi diff --git a/display/dsi-panel-ext-bridge-4k-video.dtsi b/display/dsi-panel-ext-bridge-4k-video.dtsi new file mode 100644 index 000000000000..03eb7681920d --- /dev/null +++ b/display/dsi-panel-ext-bridge-4k-video.dtsi @@ -0,0 +1,45 @@ +&mdss_mdp { + dsi_ext_bridge_4k_vid: qcom,mdss_dsi_ext_bridge_4k_video { + qcom,mdss-dsi-panel-name = "ext 4k video mode dsi bridge"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-t-clk-post = <0x1e>; + qcom,mdss-dsi-t-clk-pre = <0x2e>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,mdss-dsi-ext-bridge-mode; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <400>; + qcom,mdss-dsi-h-pulse-width = <88>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <72>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; + }; +}; diff --git a/display/kona-sde-display.dtsi b/display/kona-sde-display.dtsi index aa612e99cbb1..5d515d2ef3c9 100644 --- a/display/kona-sde-display.dtsi +++ b/display/kona-sde-display.dtsi @@ -11,6 +11,7 @@ #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ext-bridge-4k-video.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-sim-dsc375-cmd.dtsi" @@ -275,6 +276,18 @@ }; }; +&dsi_ext_bridge_4k_vid { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0f 2e 2b 0f + 10 0b 02 04 00 2e 1e]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sw43404_amoled_cmd { qcom,ulps-enabled; qcom,esd-check-enabled; From 74b2418df7f1ce55a0c86baf29ef636fb8d8de08 Mon Sep 17 00:00:00 2001 From: Zun Qiao Date: Thu, 9 Mar 2023 15:49:29 +0530 Subject: [PATCH 326/327] ARM: dts: msm: Add HDMI display support for QCS6490 IOT ODK Add HDMI display support for QCS6490 IOT ODK Change-Id: I4b469a00ec1428b9df1e241500fb2f206b2662e8 --- display/yupik-sde-display-common.dtsi | 26 ++++++++++++++++ display/yupik-sde-display-iot-pm7250b.dtsi | 36 ++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 display/yupik-sde-display-iot-pm7250b.dtsi diff --git a/display/yupik-sde-display-common.dtsi b/display/yupik-sde-display-common.dtsi index 4d54db9686ed..75c2696af682 100644 --- a/display/yupik-sde-display-common.dtsi +++ b/display/yupik-sde-display-common.dtsi @@ -11,6 +11,7 @@ #include "dsi-panel-r66451-dsc-fhd-plus-144hz-video-cphy.dtsi" #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ili9881p-720-video.dtsi" #include &soc { @@ -356,3 +357,28 @@ "src_byte_clk0", "src_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0"; }; + +&dsi_ili9881p_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio-always-on; + + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x12>; + qcom,dsi-display-active; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { + + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1F 05 + 05 06 02 04 00 12 0A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/yupik-sde-display-iot-pm7250b.dtsi b/display/yupik-sde-display-iot-pm7250b.dtsi new file mode 100644 index 000000000000..e889360c1c35 --- /dev/null +++ b/display/yupik-sde-display-iot-pm7250b.dtsi @@ -0,0 +1,36 @@ +#include "yupik-sde-display.dtsi" + +&pm7250b_gpios { + disp_lcd_bias_en { + disp_lcd_bias_en_default: disp_lcd_bias_en_default { + pins = "gpio2"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&pm8350c_gpios { + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio8"; + function = "func1"; + input-disable; + output-low; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + + qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>; +}; From 892195b346022620d50c45b8cc9e115f37dcdcc0 Mon Sep 17 00:00:00 2001 From: Nilesh Laad Date: Tue, 10 Jan 2023 15:39:45 +0530 Subject: [PATCH 327/327] ARM: dts: msm: add support for eDP on yupik target Add eDP devicetree node for yupik target. Change-Id: I8b974b12cacc7e89a92cd86e12fc269a115c4703 --- bindings/sde-dp.txt | 5 +- display/yupik-sde.dtsi | 142 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 146 insertions(+), 1 deletion(-) diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt index 5f0c5fc4fba9..14cfd1cf131f 100644 --- a/bindings/sde-dp.txt +++ b/bindings/sde-dp.txt @@ -1,7 +1,9 @@ Qualcomm Technologies, Inc. sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. DP Controller: Required properties: -- compatible: Should be "qcom,dp-display". +- compatible: one of the following + "qcom,edp-display" + "qcom,dp-display" - reg: Base address and length of DP hardware's memory mapped regions. - reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. "dp_ahb" - AHB memory region. @@ -117,6 +119,7 @@ Optional properties: device node. Refer to pinctrl-bindings.txt - qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. - qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one +- qcom,display-type: A property to make the edp or dp display as primary. [Optional child nodes]: These nodes are for devices which are dependent on msm_ext_disp. If msm_ext_disp is disabled then diff --git a/display/yupik-sde.dtsi b/display/yupik-sde.dtsi index 5b36e34752a2..c5e834a18938 100644 --- a/display/yupik-sde.dtsi +++ b/display/yupik-sde.dtsi @@ -1,5 +1,9 @@ #include "yupik-sde-common.dtsi" +#include #include +#include +#include +#include &soc { disp_rdump_memory: disp_rdump_region@e1000000 { @@ -19,6 +23,144 @@ compatible = "qcom,msm-hdcp"; }; + sde_edp: qcom,edp_display@aea0000 { + status = "disabled"; + cell-index = <1>; + qcom,intf-index = <1>; + compatible = "qcom,edp-display"; + label = "drm_edp"; + + reg = <0xaea0000 0x0fc>, + <0xaea0200 0x0c0>, + <0xaea0400 0x770>, + <0xaea1000 0x098>, + <0xaec2a00 0x200>, + <0xaec2200 0x200>, + <0xaec2600 0x200>, + <0xaf01188 0x1f>, + <0xaec2000 0x200>, + <0xaee4000 0x034>, + <0xaf01004 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", + "hdcp_physical", "gdsc"; + + qcom,pixel-base-off = <0>; + interrupt-parent = <&mdss_mdp>; + interrupts = <14 0>; + + qcom,dp-aux-switch = <&sde_edp>; + qcom,dp-low-power-hw-hpd; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&sde_edp 0>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>, + <&sde_edp 1>, + <&rpmhcc RPMH_CXO_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_edp_refclk", + "link_clk", "link_clk_src", "link_iface_clk", + "link_parent", + "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", + "strm0_pixel_clk"; + + qcom,pll-revision = "edp-7nm"; + qcom,phy-version = <0x500>; + qcom,phy-mode = "edp"; + qcom,aux-cfg0-settings = [24 00]; + qcom,aux-cfg1-settings = [28 13]; + qcom,aux-cfg2-settings = [2c 24]; + qcom,aux-cfg3-settings = [30 00]; + qcom,aux-cfg4-settings = [34 0a]; + qcom,aux-cfg5-settings = [38 26]; + qcom,aux-cfg6-settings = [3c 0a]; + qcom,aux-cfg7-settings = [40 03]; + qcom,aux-cfg8-settings = [44 37]; + qcom,aux-cfg9-settings = [4c 03]; + + qcom,max-pclk-frequency-khz = <675000>; + qcom,display-type = "primary"; + + qcom,widebus-enable; + qcom,ssc-feature-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L10C>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + refgen-supply = <&refgen>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <30100>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + sde_dp: qcom,dp_display@ae90000 { cell-index = <0>; compatible = "qcom,dp-display";