pinctrl: qcom: setup GPIO chip in hierarchy
Some GPIOs are marked as wakeup capable and are routed to another interrupt controller that is an always-domain and can detect interrupts even most of the SoC is powered off. The wakeup interrupt controller wakes up the GIC and replays the interrupt at the GIC. Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller and ensure the wakeup GPIOs are handled correctly. Change-Id: Idc2003d14d0f93f390b976cdf1e0214bad6173d2 Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
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Lina Iyer
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@ -24,6 +24,8 @@
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#include <linux/log2.h>
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#include <linux/bitmap.h>
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#include <linux/soc/qcom/irq.h>
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#include "../core.h"
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#include "../pinconf.h"
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#include "pinctrl-msm.h"
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@ -46,6 +48,7 @@
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* @enabled_irqs: Bitmap of currently enabled irqs.
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* @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
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* detection.
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* @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt contrroller
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* @soc; Reference to soc_data of platform specific data.
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* @regs: Base addresses for the TLMM tiles.
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*/
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@ -63,6 +66,7 @@ struct msm_pinctrl {
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
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DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
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const struct msm_pinctrl_soc_data *soc;
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void __iomem *regs[MAX_NR_TILES];
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@ -715,6 +719,12 @@ static void msm_gpio_irq_mask(struct irq_data *d)
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unsigned long flags;
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u32 val;
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if (d->parent_data)
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irq_chip_mask_parent(d);
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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g = &pctrl->soc->groups[d->hwirq];
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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@ -759,6 +769,12 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
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unsigned long flags;
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u32 val;
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if (d->parent_data)
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irq_chip_unmask_parent(d);
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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g = &pctrl->soc->groups[d->hwirq];
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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@ -786,10 +802,43 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
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static void msm_gpio_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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/*
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* Clear the interrupt that may be pending before we enable
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* the line.
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* This is especially a problem with the GPIOs routed to the
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* PDC. These GPIOs are direct-connect interrupts to the GIC.
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* Disabling the interrupt line at the PDC does not prevent
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* the interrupt from being latched at the GIC. The state at
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* GIC needs to be cleared before enabling.
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*/
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if (d->parent_data) {
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irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0);
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irq_chip_enable_parent(d);
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}
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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msm_gpio_irq_clear_unmask(d, true);
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}
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static void msm_gpio_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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if (d->parent_data)
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irq_chip_disable_parent(d);
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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msm_gpio_irq_mask(d);
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}
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static void msm_gpio_irq_unmask(struct irq_data *d)
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{
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msm_gpio_irq_clear_unmask(d, false);
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@ -803,6 +852,9 @@ static void msm_gpio_irq_ack(struct irq_data *d)
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unsigned long flags;
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u32 val;
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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g = &pctrl->soc->groups[d->hwirq];
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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@ -828,6 +880,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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unsigned long flags;
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u32 val;
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if (d->parent_data)
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irq_chip_set_type_parent(d, type);
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return 0;
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g = &pctrl->soc->groups[d->hwirq];
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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@ -920,6 +978,15 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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unsigned long flags;
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if (d->parent_data)
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irq_chip_set_wake_parent(d, on);
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/*
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* While they may not wake up when the TLMM is powered off,
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* some GPIOs would like to wakeup the system from suspend
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* when TLMM is powered on. To allow that, enable the GPIO
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* summary line to be wakeup capable at GIC.
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*/
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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irq_set_irq_wake(pctrl->irq, on);
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@ -998,6 +1065,30 @@ static void msm_gpio_irq_handler(struct irq_desc *desc)
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chained_irq_exit(chip, desc);
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}
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static int msm_gpio_wakeirq(struct gpio_chip *gc,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct msm_gpio_wakeirq_map *map;
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int i;
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*parent = GPIO_NO_WAKE_IRQ;
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*parent_type = IRQ_TYPE_EDGE_RISING;
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for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
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map = &pctrl->soc->wakeirq_map[i];
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if (map->gpio == child) {
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*parent = map->wakeirq;
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break;
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}
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}
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return 0;
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}
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static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
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{
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if (pctrl->soc->reserved_gpios)
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@ -1012,6 +1103,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
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struct gpio_irq_chip *girq;
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int ret;
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unsigned ngpio = pctrl->soc->ngpios;
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struct device_node *dn;
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if (WARN_ON(ngpio > MAX_NR_GPIO))
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return -EINVAL;
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@ -1028,14 +1120,36 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
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pctrl->irq_chip.name = "msmgpio";
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pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
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pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
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pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
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pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
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pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
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pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
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pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
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pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
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pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
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pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
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dn = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
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if (dn) {
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int i;
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bool skip;
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unsigned int gpio;
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chip->irq.parent_domain = irq_find_matching_host(dn,
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DOMAIN_BUS_WAKEUP);
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of_node_put(dn);
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if (!chip->irq.parent_domain)
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return -EPROBE_DEFER;
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chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
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skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
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for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
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gpio = pctrl->soc->wakeirq_map[i].gpio;
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set_bit(gpio, pctrl->skip_wake_irqs);
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}
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}
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girq = &chip->irq;
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girq->chip = &pctrl->irq_chip;
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girq->parent_handler = msm_gpio_irq_handler;
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@ -1074,6 +1188,16 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
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}
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}
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/*
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* Since we are chained to the GIC using the TLMM summary line
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* and in hierarchy with the wakeup parent interrupt controller,
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* explicitly set the chained summary line. We need to do this because
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* the summary line is not routed to the wakeup parent but directly
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* to the GIC.
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*/
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gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
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msm_gpio_irq_handler);
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return 0;
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}
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@ -6,6 +6,7 @@
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#define __PINCTRL_MSM_H__
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#include <linux/pinctrl/qcom-pinctrl.h>
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#include <linux/gpio/driver.h>
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struct pinctrl_pin_desc;
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@ -110,6 +111,16 @@ struct pinctrl_qup {
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u32 offset;
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};
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/**
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* struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
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* @gpio: The GPIOs that are wakeup capable
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* @wakeirq: The interrupt at the always-on interrupt controller
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*/
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struct msm_gpio_wakeirq_map {
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unsigned int gpio;
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unsigned int wakeirq;
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};
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/**
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* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
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* @pins: An array describing all pins the pin controller affects.
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@ -120,6 +131,8 @@ struct pinctrl_qup {
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* @ngroups: The numbmer of entries in @groups.
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* @ngpio: The number of pingroups the driver should expose as GPIOs.
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* @pull_no_keeper: The SoC does not support keeper bias.
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* @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM
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* @nwakeirq_map: The number of entries in @hierarchy_map
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*/
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struct msm_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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@ -135,6 +148,8 @@ struct msm_pinctrl_soc_data {
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const int *reserved_gpios;
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struct pinctrl_qup *qup_regs;
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unsigned int nqup_regs;
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const struct msm_gpio_wakeirq_map *wakeirq_map;
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unsigned int nwakeirq_map;
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};
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extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
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