lisa/android_kernel_xiaomi_sm8350
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: qcom: Add IPQ806X's HFPLLs

Browse Source 
Describe the HFPLLs present on IPQ806X devices.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Stephen Boyd 2018-08-14 17:42:25 +05:30 committed by Stephen Boyd
parent 72ad720795
commit 1f79131bfd
1 changed files with 82 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

82
drivers/clk/qcom/gcc-ipq806x.c
View File

@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll0 = {
@ -113,6 +114,84 @@ static struct clk_regmap pll8_vote = {
},
};
static struct hfpll_data hfpll0_data = {
.mode_reg = 0x3200,
.l_reg = 0x3208,
.m_reg = 0x320c,
.n_reg = 0x3210,
.config_reg = 0x3204,
.status_reg = 0x321c,
.config_val = 0x7845c665,
.droop_reg = 0x3214,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll0 = {
.d = &hfpll0_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "pxo" },
.num_parents = 1,
.name = "hfpll0",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
};
static struct hfpll_data hfpll1_data = {
.mode_reg = 0x3240,
.l_reg = 0x3248,
.m_reg = 0x324c,
.n_reg = 0x3250,
.config_reg = 0x3244,
.status_reg = 0x325c,
.config_val = 0x7845c665,
.droop_reg = 0x3314,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll1 = {
.d = &hfpll1_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "pxo" },
.num_parents = 1,
.name = "hfpll1",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
};
static struct hfpll_data hfpll_l2_data = {
.mode_reg = 0x3300,
.l_reg = 0x3308,
.m_reg = 0x330c,
.n_reg = 0x3310,
.config_reg = 0x3304,
.status_reg = 0x331c,
.config_val = 0x7845c665,
.droop_reg = 0x3314,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll_l2 = {
.d = &hfpll_l2_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_names = (const char *[]){ "pxo" },
.num_parents = 1,
.name = "hfpll_l2",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
};
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@ -2797,6 +2876,9 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
[NSSTCM_CLK] = &nss_tcm_clk.clkr,
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {