From 20c0591c0ed41cfd8aa044e539bd7bdc526188e5 Mon Sep 17 00:00:00 2001 From: Arian Date: Sat, 29 Jan 2022 16:18:18 +0100 Subject: [PATCH] arm64: dts: lahaina: configure gpio47 as qupv3_se10_spi_sleep_cs Change-Id: I7496e7eb517a48a77ff9999dd5db8ce3d4e85e71 --- .../boot/dts/vendor/qcom/lahaina-pinctrl.dtsi | 15 +++++++++++++-- .../arm64/boot/dts/vendor/qcom/lahaina-qupv3.dtsi | 2 +- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/vendor/qcom/lahaina-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/lahaina-pinctrl.dtsi index 251886975683..228aac96cc05 100644 --- a/arch/arm64/boot/dts/vendor/qcom/lahaina-pinctrl.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lahaina-pinctrl.dtsi @@ -831,13 +831,24 @@ qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { mux { pins = "gpio44", "gpio45", - "gpio46", "gpio47"; + "gpio46"; function = "gpio"; }; config { pins = "gpio44", "gpio45", - "gpio46", "gpio47"; + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + qupv3_se10_spi_sleep_cs: qupv3_se10_spi_sleep_cs { + mux { + pins = "gpio47"; + function = "gpio"; + }; + config { + pins = "gpio47"; drive-strength = <6>; bias-disable; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/lahaina-qupv3.dtsi b/arch/arm64/boot/dts/vendor/qcom/lahaina-qupv3.dtsi index 159c0977f21e..c45adc31790d 100644 --- a/arch/arm64/boot/dts/vendor/qcom/lahaina-qupv3.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lahaina-qupv3.dtsi @@ -557,7 +557,7 @@ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se10_spi_active>; - pinctrl-1 = <&qupv3_se10_spi_sleep>; + pinctrl-1 = <&qupv3_se10_spi_sleep &qupv3_se10_spi_sleep_cs>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>;