misc: xilinx_sdfec: Add ability to configure LDPC
Add the capability to configure LDPC mode via the ioctl XSDFEC_ADD_LDPC_CODE_PARAMS. Tested-by: Dragan Cvetic <dragan.cvetic@xilinx.com> Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Dragan Cvetic <dragan.cvetic@xilinx.com> Link: https://lore.kernel.org/r/1564216438-322406-4-git-send-email-dragan.cvetic@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dragan Cvetic
Greg Kroah-Hartman
parent
6f86ed8201
commit
20ec628e80
@ -20,6 +20,7 @@
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/compat.h>
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#include <linux/highmem.h>
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#include <uapi/misc/xilinx_sdfec.h>
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@ -113,6 +114,57 @@ static struct mutex dev_idr_lock;
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#define XSDFEC_TURBO_SCALE_BIT_POS (8)
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#define XSDFEC_TURBO_SCALE_MAX (15)
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/* REG0 Register */
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#define XSDFEC_LDPC_CODE_REG0_ADDR_BASE (0x2000)
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#define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH (0x27F0)
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#define XSDFEC_REG0_N_MIN (4)
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#define XSDFEC_REG0_N_MAX (32768)
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#define XSDFEC_REG0_N_MUL_P (256)
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#define XSDFEC_REG0_N_LSB (0)
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#define XSDFEC_REG0_K_MIN (2)
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#define XSDFEC_REG0_K_MAX (32766)
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#define XSDFEC_REG0_K_MUL_P (256)
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#define XSDFEC_REG0_K_LSB (16)
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/* REG1 Register */
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#define XSDFEC_LDPC_CODE_REG1_ADDR_BASE (0x2004)
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#define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH (0x27f4)
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#define XSDFEC_REG1_PSIZE_MIN (2)
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#define XSDFEC_REG1_PSIZE_MAX (512)
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#define XSDFEC_REG1_NO_PACKING_MASK (0x400)
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#define XSDFEC_REG1_NO_PACKING_LSB (10)
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#define XSDFEC_REG1_NM_MASK (0xFF800)
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#define XSDFEC_REG1_NM_LSB (11)
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#define XSDFEC_REG1_BYPASS_MASK (0x100000)
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/* REG2 Register */
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#define XSDFEC_LDPC_CODE_REG2_ADDR_BASE (0x2008)
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#define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH (0x27f8)
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#define XSDFEC_REG2_NLAYERS_MIN (1)
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#define XSDFEC_REG2_NLAYERS_MAX (256)
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#define XSDFEC_REG2_NNMQC_MASK (0xFFE00)
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#define XSDFEC_REG2_NMQC_LSB (9)
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#define XSDFEC_REG2_NORM_TYPE_MASK (0x100000)
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#define XSDFEC_REG2_NORM_TYPE_LSB (20)
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#define XSDFEC_REG2_SPECIAL_QC_MASK (0x200000)
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#define XSDFEC_REG2_SPEICAL_QC_LSB (21)
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#define XSDFEC_REG2_NO_FINAL_PARITY_MASK (0x400000)
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#define XSDFEC_REG2_NO_FINAL_PARITY_LSB (22)
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#define XSDFEC_REG2_MAX_SCHEDULE_MASK (0x1800000)
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#define XSDFEC_REG2_MAX_SCHEDULE_LSB (23)
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/* REG3 Register */
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#define XSDFEC_LDPC_CODE_REG3_ADDR_BASE (0x200C)
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#define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH (0x27FC)
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#define XSDFEC_REG3_LA_OFF_LSB (8)
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#define XSDFEC_REG3_QC_OFF_LSB (16)
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#define XSDFEC_LDPC_REG_JUMP (0x10)
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#define XSDFEC_REG_WIDTH_JUMP (4)
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/* The maximum number of pinned pages */
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#define MAX_NUM_PAGES ((XSDFEC_QC_TABLE_DEPTH / PAGE_SIZE) + 1)
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/**
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* struct xsdfec_clks - For managing SD-FEC clocks
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* @core_clk: Main processing clock for core
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@ -270,6 +322,275 @@ static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg)
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return err;
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}
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static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize,
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u32 offset)
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{
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u32 wdata;
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if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX ||
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(n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) {
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dev_dbg(xsdfec->dev, "N value is not in range");
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return -EINVAL;
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}
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n <<= XSDFEC_REG0_N_LSB;
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if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX ||
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(k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) {
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dev_dbg(xsdfec->dev, "K value is not in range");
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return -EINVAL;
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}
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k = k << XSDFEC_REG0_K_LSB;
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wdata = k | n;
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if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
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XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) {
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dev_dbg(xsdfec->dev, "Writing outside of LDPC reg0 space 0x%x",
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XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP));
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return -EINVAL;
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}
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xsdfec_regwrite(xsdfec,
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XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP),
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wdata);
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return 0;
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}
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static int xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize,
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u32 no_packing, u32 nm, u32 offset)
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{
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u32 wdata;
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if (psize < XSDFEC_REG1_PSIZE_MIN || psize > XSDFEC_REG1_PSIZE_MAX) {
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dev_dbg(xsdfec->dev, "Psize is not in range");
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return -EINVAL;
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}
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if (no_packing != 0 && no_packing != 1)
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dev_dbg(xsdfec->dev, "No-packing bit register invalid");
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no_packing = ((no_packing << XSDFEC_REG1_NO_PACKING_LSB) &
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XSDFEC_REG1_NO_PACKING_MASK);
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if (nm & ~(XSDFEC_REG1_NM_MASK >> XSDFEC_REG1_NM_LSB))
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dev_dbg(xsdfec->dev, "NM is beyond 10 bits");
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nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK;
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wdata = nm | no_packing | psize;
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if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
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XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) {
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dev_dbg(xsdfec->dev, "Writing outside of LDPC reg1 space 0x%x",
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XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP));
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return -EINVAL;
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}
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xsdfec_regwrite(xsdfec,
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XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP),
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wdata);
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return 0;
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}
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static int xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc,
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u32 norm_type, u32 special_qc, u32 no_final_parity,
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u32 max_schedule, u32 offset)
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{
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u32 wdata;
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if (nlayers < XSDFEC_REG2_NLAYERS_MIN ||
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nlayers > XSDFEC_REG2_NLAYERS_MAX) {
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dev_dbg(xsdfec->dev, "Nlayers is not in range");
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return -EINVAL;
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}
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if (nmqc & ~(XSDFEC_REG2_NNMQC_MASK >> XSDFEC_REG2_NMQC_LSB))
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dev_dbg(xsdfec->dev, "NMQC exceeds 11 bits");
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nmqc = (nmqc << XSDFEC_REG2_NMQC_LSB) & XSDFEC_REG2_NNMQC_MASK;
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if (norm_type > 1)
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dev_dbg(xsdfec->dev, "Norm type is invalid");
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norm_type = ((norm_type << XSDFEC_REG2_NORM_TYPE_LSB) &
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XSDFEC_REG2_NORM_TYPE_MASK);
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if (special_qc > 1)
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dev_dbg(xsdfec->dev, "Special QC in invalid");
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special_qc = ((special_qc << XSDFEC_REG2_SPEICAL_QC_LSB) &
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XSDFEC_REG2_SPECIAL_QC_MASK);
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if (no_final_parity > 1)
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dev_dbg(xsdfec->dev, "No final parity check invalid");
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no_final_parity =
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((no_final_parity << XSDFEC_REG2_NO_FINAL_PARITY_LSB) &
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XSDFEC_REG2_NO_FINAL_PARITY_MASK);
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if (max_schedule &
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~(XSDFEC_REG2_MAX_SCHEDULE_MASK >> XSDFEC_REG2_MAX_SCHEDULE_LSB))
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dev_dbg(xsdfec->dev, "Max Schdule exceeds 2 bits");
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max_schedule = ((max_schedule << XSDFEC_REG2_MAX_SCHEDULE_LSB) &
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XSDFEC_REG2_MAX_SCHEDULE_MASK);
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wdata = (max_schedule | no_final_parity | special_qc | norm_type |
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nmqc | nlayers);
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if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
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XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) {
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dev_dbg(xsdfec->dev, "Writing outside of LDPC reg2 space 0x%x",
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XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP));
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return -EINVAL;
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}
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xsdfec_regwrite(xsdfec,
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XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP),
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wdata);
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return 0;
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}
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static int xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off, u8 la_off,
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u16 qc_off, u32 offset)
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{
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u32 wdata;
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wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) |
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(la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off);
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if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
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XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) {
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dev_dbg(xsdfec->dev, "Writing outside of LDPC reg3 space 0x%x",
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XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP));
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return -EINVAL;
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}
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xsdfec_regwrite(xsdfec,
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XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
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(offset * XSDFEC_LDPC_REG_JUMP),
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wdata);
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return 0;
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}
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static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset,
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u32 *src_ptr, u32 len, const u32 base_addr,
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const u32 depth)
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{
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u32 reg = 0;
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u32 res;
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u32 n, i;
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u32 *addr = NULL;
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struct page *page[MAX_NUM_PAGES];
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/*
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* Writes that go beyond the length of
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* Shared Scale(SC) table should fail
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*/
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if ((XSDFEC_REG_WIDTH_JUMP * (offset + len)) > depth) {
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dev_dbg(xsdfec->dev, "Write exceeds SC table length");
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return -EINVAL;
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}
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n = (len * XSDFEC_REG_WIDTH_JUMP) / PAGE_SIZE;
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if ((len * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)
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n += 1;
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res = get_user_pages_fast((unsigned long)src_ptr, n, 0, page);
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if (res < n) {
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for (i = 0; i < res; i++)
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put_page(page[i]);
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return -EINVAL;
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}
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for (i = 0; i < n; i++) {
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addr = kmap(page[i]);
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do {
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xsdfec_regwrite(xsdfec,
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base_addr + ((offset + reg) *
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XSDFEC_REG_WIDTH_JUMP),
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addr[reg]);
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reg++;
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} while ((reg < len) &&
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((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE));
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put_page(page[i]);
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}
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return reg;
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}
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static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg)
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{
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struct xsdfec_ldpc_params *ldpc;
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int ret, n;
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ldpc = kzalloc(sizeof(*ldpc), GFP_KERNEL);
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if (!ldpc)
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return -ENOMEM;
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ret = copy_from_user(ldpc, arg, sizeof(*ldpc));
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if (ret)
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goto err_out;
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if (xsdfec->config.code == XSDFEC_TURBO_CODE) {
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ret = -EIO;
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goto err_out;
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}
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/* Verify Device has not started */
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if (xsdfec->state == XSDFEC_STARTED) {
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ret = -EIO;
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goto err_out;
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}
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if (xsdfec->config.code_wr_protect) {
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ret = -EIO;
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goto err_out;
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}
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/* Write Reg 0 */
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ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize,
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ldpc->code_id);
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if (ret)
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goto err_out;
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/* Write Reg 1 */
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ret = xsdfec_reg1_write(xsdfec, ldpc->psize, ldpc->no_packing, ldpc->nm,
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ldpc->code_id);
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if (ret)
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goto err_out;
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/* Write Reg 2 */
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ret = xsdfec_reg2_write(xsdfec, ldpc->nlayers, ldpc->nmqc,
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ldpc->norm_type, ldpc->special_qc,
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ldpc->no_final_parity, ldpc->max_schedule,
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ldpc->code_id);
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if (ret)
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goto err_out;
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/* Write Reg 3 */
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ret = xsdfec_reg3_write(xsdfec, ldpc->sc_off, ldpc->la_off,
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ldpc->qc_off, ldpc->code_id);
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if (ret)
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goto err_out;
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/* Write Shared Codes */
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n = ldpc->nlayers / 4;
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if (ldpc->nlayers % 4)
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n++;
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ret = xsdfec_table_write(xsdfec, ldpc->sc_off, ldpc->sc_table, n,
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XSDFEC_LDPC_SC_TABLE_ADDR_BASE,
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XSDFEC_SC_TABLE_DEPTH);
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if (ret < 0)
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goto err_out;
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ret = xsdfec_table_write(xsdfec, 4 * ldpc->la_off, ldpc->la_table,
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ldpc->nlayers, XSDFEC_LDPC_LA_TABLE_ADDR_BASE,
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XSDFEC_LA_TABLE_DEPTH);
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if (ret < 0)
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goto err_out;
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ret = xsdfec_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table,
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ldpc->nqc, XSDFEC_LDPC_QC_TABLE_ADDR_BASE,
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XSDFEC_QC_TABLE_DEPTH);
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if (ret > 0)
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ret = 0;
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err_out:
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kfree(ldpc);
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return ret;
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}
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static u32
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xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg)
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{
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@ -366,6 +687,9 @@ static long xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd,
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case XSDFEC_GET_TURBO:
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rval = xsdfec_get_turbo(xsdfec, arg);
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break;
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case XSDFEC_ADD_LDPC_CODE_PARAMS:
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rval = xsdfec_add_ldpc(xsdfec, arg);
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break;
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default:
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/* Should not get here */
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break;
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@ -13,6 +13,22 @@
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#include <linux/types.h>
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/* Shared LDPC Tables */
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#define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
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#define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x10400)
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#define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
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#define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x19000)
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#define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
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#define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x28000)
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/* LDPC tables depth */
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#define XSDFEC_SC_TABLE_DEPTH \
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(XSDFEC_LDPC_SC_TABLE_ADDR_HIGH - XSDFEC_LDPC_SC_TABLE_ADDR_BASE)
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#define XSDFEC_LA_TABLE_DEPTH \
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(XSDFEC_LDPC_LA_TABLE_ADDR_HIGH - XSDFEC_LDPC_LA_TABLE_ADDR_BASE)
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#define XSDFEC_QC_TABLE_DEPTH \
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(XSDFEC_LDPC_QC_TABLE_ADDR_HIGH - XSDFEC_LDPC_QC_TABLE_ADDR_BASE)
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/**
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* enum xsdfec_code - Code Type.
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* @XSDFEC_TURBO_CODE: Driver is configured for Turbo mode.
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@ -126,6 +142,53 @@ struct xsdfec_turbo {
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__u8 scale;
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};
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/**
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* struct xsdfec_ldpc_params - User data for LDPC codes.
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* @n: Number of code word bits
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* @k: Number of information bits
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* @psize: Size of sub-matrix
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* @nlayers: Number of layers in code
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* @nqc: Quasi Cyclic Number
|
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* @nmqc: Number of M-sized QC operations in parity check matrix
|
||||
* @nm: Number of M-size vectors in N
|
||||
* @norm_type: Normalization required or not
|
||||
* @no_packing: Determines if multiple QC ops should be performed
|
||||
* @special_qc: Sub-Matrix property for Circulant weight > 0
|
||||
* @no_final_parity: Decide if final parity check needs to be performed
|
||||
* @max_schedule: Experimental code word scheduling limit
|
||||
* @sc_off: SC offset
|
||||
* @la_off: LA offset
|
||||
* @qc_off: QC offset
|
||||
* @sc_table: Pointer to SC Table which must be page aligned
|
||||
* @la_table: Pointer to LA Table which must be page aligned
|
||||
* @qc_table: Pointer to QC Table which must be page aligned
|
||||
* @code_id: LDPC Code
|
||||
*
|
||||
* This structure describes the LDPC code that is passed to the driver by the
|
||||
* application.
|
||||
*/
|
||||
struct xsdfec_ldpc_params {
|
||||
__u32 n;
|
||||
__u32 k;
|
||||
__u32 psize;
|
||||
__u32 nlayers;
|
||||
__u32 nqc;
|
||||
__u32 nmqc;
|
||||
__u32 nm;
|
||||
__u32 norm_type;
|
||||
__u32 no_packing;
|
||||
__u32 special_qc;
|
||||
__u32 no_final_parity;
|
||||
__u32 max_schedule;
|
||||
__u32 sc_off;
|
||||
__u32 la_off;
|
||||
__u32 qc_off;
|
||||
__u32 *sc_table;
|
||||
__u32 *la_table;
|
||||
__u32 *qc_table;
|
||||
__u16 code_id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct xsdfec_status - Status of SD-FEC core.
|
||||
* @state: State of the SD-FEC core
|
||||
@ -170,6 +233,20 @@ struct xsdfec_config {
|
||||
__s8 code_wr_protect;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct xsdfec_ldpc_param_table_sizes - Used to store sizes of SD-FEC table
|
||||
* entries for an individual LPDC code
|
||||
* parameter.
|
||||
* @sc_size: Size of SC table used
|
||||
* @la_size: Size of LA table used
|
||||
* @qc_size: Size of QC table used
|
||||
*/
|
||||
struct xsdfec_ldpc_param_table_sizes {
|
||||
__u32 sc_size;
|
||||
__u32 la_size;
|
||||
__u32 qc_size;
|
||||
};
|
||||
|
||||
/*
|
||||
* XSDFEC IOCTL List
|
||||
*/
|
||||
@ -189,6 +266,27 @@ struct xsdfec_config {
|
||||
* This can only be used when the driver is in the XSDFEC_STOPPED state
|
||||
*/
|
||||
#define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 4, struct xsdfec_turbo)
|
||||
/**
|
||||
* DOC: XSDFEC_ADD_LDPC_CODE_PARAMS
|
||||
* @Parameters
|
||||
*
|
||||
* @struct xsdfec_ldpc_params *
|
||||
* Pointer to the &struct xsdfec_ldpc_params that contains the LDPC code
|
||||
* parameters to be added to the SD-FEC Block
|
||||
*
|
||||
* @Description
|
||||
* ioctl to add an LDPC code to the SD-FEC LDPC codes
|
||||
*
|
||||
* This can only be used when:
|
||||
*
|
||||
* - Driver is in the XSDFEC_STOPPED state
|
||||
*
|
||||
* - SD-FEC core is configured as LPDC
|
||||
*
|
||||
* - SD-FEC Code Write Protection is disabled
|
||||
*/
|
||||
#define XSDFEC_ADD_LDPC_CODE_PARAMS \
|
||||
_IOW(XSDFEC_MAGIC, 5, struct xsdfec_ldpc_params)
|
||||
/**
|
||||
* DOC: XSDFEC_GET_TURBO
|
||||
* @Parameters
|
||||
|
||||
Loading…
Reference in New Issue
Block a user