Merge "cnss2: Properly send adsp power collapse enable/disable cmds"
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20fbe1a9a1
@ -3053,6 +3053,10 @@ static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
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plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
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plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
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plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
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/* Set adsp_pc_enabled default value to true as ADSP pc is always
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* enabled by default
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*/
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plat_priv->adsp_pc_enabled = true;
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}
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static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
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@ -505,6 +505,7 @@ struct cnss_plat_data {
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u32 is_converged_dt;
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struct device_node *dev_node;
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u64 feature_list;
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bool adsp_pc_enabled;
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};
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#ifdef CONFIG_ARCH_QCOM
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@ -1802,6 +1802,13 @@ static int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
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struct pci_dev *pci_dev = pci_priv->pci_dev;
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int ret = 0;
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u32 pm_options = PM_OPTIONS_DEFAULT;
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struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
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if (plat_priv->adsp_pc_enabled == control) {
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cnss_pr_dbg("ADSP power collapse already %s\n",
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control ? "Enabled" : "Disabled");
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return 0;
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}
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if (control)
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pm_options &= ~MSM_PCIE_CONFIG_NO_DRV_PC;
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@ -1814,6 +1821,7 @@ static int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
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return ret;
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cnss_pr_dbg("%s ADSP power collapse\n", control ? "Enable" : "Disable");
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plat_priv->adsp_pc_enabled = control;
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return 0;
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}
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#else
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