lisa/android_kernel_xiaomi_sm8350
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge "coresight-tmc: increase qdss pcie sw path throughput"

Browse Source
This commit is contained in:
qctecmdr 2023-04-20 04:34:07 -07:00 committed by Gerrit - the friendly Code Review server
commit 460f325dcb
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/hwtracing/coresight/coresight-tmc-etr.c
View File

@ -1129,9 +1129,11 @@ tmc_etr_setup_sysfs_buf(struct tmc_drvdata *drvdata)
&& drvdata->byte_cntr->sw_usb)
new_buf = tmc_alloc_etr_buf(drvdata, TMC_ETR_SW_USB_BUF_SIZE,
0, cpu_to_node(0), NULL);
else if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE)
else if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) {
new_buf = tmc_alloc_etr_buf(drvdata, TMC_ETR_PCIE_MEM_SIZE,
0, cpu_to_node(0), NULL);
drvdata->size = TMC_ETR_PCIE_MEM_SIZE;
}
else
new_buf = tmc_alloc_etr_buf(drvdata, drvdata->size,
0, cpu_to_node(0), NULL);

2
drivers/hwtracing/coresight/coresight-tmc.h
View File

@ -104,7 +104,7 @@
#define TMC_ETR_BAM_PIPE_INDEX 0
#define TMC_ETR_BAM_NR_PIPES 2
#define TMC_ETR_PCIE_MEM_SIZE 0x400000
#define TMC_ETR_PCIE_MEM_SIZE 0x2000000
#define TMC_AUTH_NSID_MASK GENMASK(1, 0)