diff --git a/techpack/audio/asoc/codecs/cs35l45/Kbuild b/techpack/audio/asoc/codecs/cs35l45/Kbuild new file mode 100644 index 0000000000000..2c3db0ab56498 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/Kbuild @@ -0,0 +1,110 @@ +# We can build either as part of a standalone Kernel build or as +# an external module. Determine which mechanism is being used +ifeq ($(MODNAME),) + KERNEL_BUILD := 1 +else + KERNEL_BUILD := 0 +endif + +ifeq ($(KERNEL_BUILD), 1) +# These are configurable via Kconfig for kernel-based builds +# Need to explicitly configure for Android-based builds + AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4 + AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio +endif + +ifeq ($(KERNEL_BUILD), 0) + ifeq ($(CONFIG_ARCH_KONA), y) + include $(AUDIO_ROOT)/config/konaauto.conf + INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h + endif + ifeq ($(CONFIG_ARCH_LITO), y) + include $(AUDIO_ROOT)/config/litoauto.conf + export + INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h + endif + +endif + +# As per target team, build is done as follows: +# Defconfig : build with default flags +# Slub : defconfig + CONFIG_SLUB_DEBUG := y + +# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y +# Perf : Using appropriate msmXXXX-perf_defconfig +# +# Shipment builds (user variants) should not have any debug feature +# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds +# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since +# there is no other way to identify defconfig builds, QTI internal +# representation of perf builds (identified using the string 'perf'), +# is used to identify if the build is a slub or defconfig one. This +# way no critical debug feature will be enabled for perf and shipment +# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT +# config. + +############ UAPI ############ +UAPI_DIR := uapi/audio +UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR) + +############ COMMON ############ +COMMON_DIR := include +COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR) + +############ CS35L45 ############ + +# for CS35L45 Codec +ifdef CONFIG_SND_SOC_CS35L45 +CS35L45_OBJS += cs35l45.o +CS35L45_OBJS += cs35l45-i2c.o +CS35L45_OBJS += cs35l45-tables.o +CS35L45_OBJS += wm_adsp.o +endif + +LINUX_INC += -Iinclude/linux + +INCS += $(COMMON_INC) \ + $(UAPI_INC) + +EXTRA_CFLAGS += $(INCS) + + CDEFINES += -DCONFIG_AUDIO_SMARTPA_STEREO + + CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ + -DANI_LITTLE_BIT_ENDIAN \ + -DDOT11F_LITTLE_ENDIAN_HOST \ + -DANI_COMPILER_TYPE_GCC \ + -DANI_OS_TYPE_ANDROID=6 \ + -DPTT_SOCK_SVC_ENABLE \ + -Wall\ + -Werror\ + -D__linux__ + +KBUILD_CPPFLAGS += $(CDEFINES) + +# Currently, for versions of gcc which support it, the kernel Makefile +# is disabling the maybe-uninitialized warning. Re-enable it for the +# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it +# will override the kernel settings. +ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y) + EXTRA_CFLAGS += -Wmaybe-uninitialized +endif +#EXTRA_CFLAGS += -Wmissing-prototypes + +ifeq ($(call cc-option-yn, -Wheader-guard),y) + EXTRA_CFLAGS += -Wheader-guard +endif + +ifeq ($(KERNEL_BUILD), 0) + KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers + KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers + KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers + KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers + KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers +endif + +# Module information used by KBuild framework +obj-$(CONFIG_SND_SOC_CS35L45) += cs35l45_dlkm.o +cs35l45_dlkm-y := $(CS35L45_OBJS) + +# inject some build related information +DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/cs35l45/cs35l45-i2c.c b/techpack/audio/asoc/codecs/cs35l45/cs35l45-i2c.c new file mode 100644 index 0000000000000..f915f5f45dbf7 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/cs35l45-i2c.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * cs35l45-i2c.c -- CS35L45 I2C driver + * + * Copyright 2019 Cirrus Logic, Inc. + * + * Author: James Schulman + * + */ +#define DEBUG +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l45.h" +#include "cs35l45_user.h" + +static struct regmap_config cs35l45_regmap = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = CS35L45_REGSTRIDE, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + .max_register = CS35L45_LASTREG, + .reg_defaults = cs35l45_reg, + .num_reg_defaults = ARRAY_SIZE(cs35l45_reg), + .volatile_reg = cs35l45_volatile_reg, + .readable_reg = cs35l45_readable_reg, + .cache_type = REGCACHE_RBTREE, +}; + +static int cs35l45_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct cs35l45_private *cs35l45; + struct device *dev = &client->dev; + int ret; + + cs35l45 = devm_kzalloc(dev, sizeof(struct cs35l45_private), GFP_KERNEL); + if (cs35l45 == NULL) + return -ENOMEM; + + i2c_set_clientdata(client, cs35l45); + cs35l45->regmap = devm_regmap_init_i2c(client, &cs35l45_regmap); + if (IS_ERR(cs35l45->regmap)) { + ret = PTR_ERR(cs35l45->regmap); + dev_err(dev, "Failed to allocate register map: %d\n", ret); + return ret; + } + + cs35l45->dev = dev; + cs35l45->irq = client->irq; + cs35l45->wksrc = CS35L45_WKSRC_I2C; + cs35l45->i2c_addr = client->addr; + + ret = cs35l45_probe(cs35l45); + if (ret < 0) { + dev_err(dev, "Failed device probe: %d\n", ret); + return ret; + } + + usleep_range(2000, 2100); + + ret = cs35l45_initialize(cs35l45); + if (ret < 0) { + dev_err(dev, "Failed device initialization: %d\n", ret); + return ret; + } + + return 0; +} + +static int cs35l45_i2c_remove(struct i2c_client *client) +{ + struct cs35l45_private *cs35l45 = i2c_get_clientdata(client); + + return cs35l45_remove(cs35l45); +} + +static const struct of_device_id cs35l45_of_match[] = { + {.compatible = "cirrus,cs35l45"}, + {}, +}; +MODULE_DEVICE_TABLE(of, cs35l45_of_match); + +static const struct i2c_device_id cs35l45_id_i2c[] = { + {"cs35l45", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, cs35l45_id_i2c); + +static struct i2c_driver cs35l45_i2c_driver = { + .driver = { + .name = "cs35l45", + .of_match_table = cs35l45_of_match, + }, + .id_table = cs35l45_id_i2c, + .probe = cs35l45_i2c_probe, + .remove = cs35l45_i2c_remove, +}; +module_i2c_driver(cs35l45_i2c_driver); + +MODULE_DESCRIPTION("I2C CS35L45 driver"); +MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l45/cs35l45-spi.c b/techpack/audio/asoc/codecs/cs35l45/cs35l45-spi.c new file mode 100644 index 0000000000000..27efb627655c6 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/cs35l45-spi.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * cs35l45-spi.c -- CS35L45 SPI driver + * + * Copyright 2019 Cirrus Logic, Inc. + * + * Author: James Schulman + * + */ + +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l45.h" +#include "cs35l45_user.h" + +static struct regmap_config cs35l45_regmap = { + .reg_bits = 32, + .val_bits = 32, + .pad_bits = 16, + .reg_stride = CS35L45_REGSTRIDE, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + .max_register = CS35L45_LASTREG, + .reg_defaults = cs35l45_reg, + .num_reg_defaults = ARRAY_SIZE(cs35l45_reg), + .volatile_reg = cs35l45_volatile_reg, + .readable_reg = cs35l45_readable_reg, + .cache_type = REGCACHE_RBTREE, +}; + +static int cs35l45_spi_probe(struct spi_device *spi) +{ + struct cs35l45_private *cs35l45; + struct device *dev = &spi->dev; + int ret; + + cs35l45 = devm_kzalloc(dev, sizeof(struct cs35l45_private), GFP_KERNEL); + if (cs35l45 == NULL) + return -ENOMEM; + + spi_set_drvdata(spi, cs35l45); + cs35l45->regmap = devm_regmap_init_spi(spi, &cs35l45_regmap); + if (IS_ERR(cs35l45->regmap)) { + ret = PTR_ERR(cs35l45->regmap); + dev_err(dev, "Failed to allocate register map: %d\n", ret); + return ret; + } + + cs35l45->dev = dev; + cs35l45->irq = spi->irq; + cs35l45->wksrc = CS35L45_WKSRC_SPI; + + ret = cs35l45_probe(cs35l45); + if (ret < 0) { + dev_err(dev, "Failed device probe: %d\n", ret); + return ret; + } + + usleep_range(2000, 2100); + + ret = cs35l45_initialize(cs35l45); + if (ret < 0) { + dev_err(dev, "Failed device initialization: %d\n", ret); + return ret; + } + + return 0; +} + +static int cs35l45_spi_remove(struct spi_device *spi) +{ + struct cs35l45_private *cs35l45 = spi_get_drvdata(spi); + + return cs35l45_remove(cs35l45); +} + +static const struct of_device_id cs35l45_of_match[] = { + {.compatible = "cirrus,cs35l45"}, + {}, +}; +MODULE_DEVICE_TABLE(of, cs35l45_of_match); + +static const struct spi_device_id cs35l45_id_spi[] = { + {"cs35l45", 0}, + {} +}; +MODULE_DEVICE_TABLE(spi, cs35l45_id_spi); + +static struct spi_driver cs35l45_spi_driver = { + .driver = { + .name = "cs35l45", + .of_match_table = cs35l45_of_match, + }, + .id_table = cs35l45_id_spi, + .probe = cs35l45_spi_probe, + .remove = cs35l45_spi_remove, +}; +module_spi_driver(cs35l45_spi_driver); + +MODULE_DESCRIPTION("SPI CS35L45 driver"); +MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l45/cs35l45-tables.c b/techpack/audio/asoc/codecs/cs35l45/cs35l45-tables.c new file mode 100644 index 0000000000000..9551c4b49faca --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/cs35l45-tables.c @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * cs35l45-tables.c -- CS35L45 ALSA SoC audio driver + * + * Copyright 2019 Cirrus Logic, Inc. + * + * Author: James Schulman + * + */ + +#include +#include + +#include "wm_adsp.h" +#include "cs35l45.h" +#include "cs35l45_user.h" + +const struct reg_default cs35l45_reg[CS35L45_MAX_CACHE_REG] = { + {CS35L45_BLOCK_ENABLES, 0x00003323}, + {CS35L45_BLOCK_ENABLES2, 0x00000010}, + {CS35L45_GLOBAL_OVERRIDES, 0x00000002}, + {CS35L45_GLOBAL_SYNC, 0x00000000}, + {CS35L45_ERROR_RELEASE, 0x00000000}, + {CS35L45_SYNC_GPIO1, 0x00000007}, + {CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005}, + {CS35L45_GPIO3, 0x00000005}, + {CS35L45_GPIO_GLOBAL_ENABLE_CONTROL, 0x00000000}, + {CS35L45_PWRMGT_CTL, 0x00000000}, + {CS35L45_WAKESRC_CTL, 0x00000008}, + {CS35L45_WKI2C_CTL, 0x00000030}, + {CS35L45_PWRMGT_STS, 0x00000000}, + {CS35L45_REFCLK_INPUT, 0x00000510}, + {CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003}, + {CS35L45_SWIRE_CLK_CTRL, 0x00000000}, + {CS35L45_BOOST_VOLTAGE_CFG, 0x000001BE}, + {CS35L45_BOOST_CCM_CFG, 0xF0000001}, + {CS35L45_BOOST_DCM_CFG, 0x08710200}, + {CS35L45_BOOST_LPMODE_CFG, 0x00000002}, + {CS35L45_BOOST_RAMP_CFG, 0x0000004A}, + {CS35L45_BOOST_STARTUP_CFG, 0x0000831D}, + {CS35L45_BOOST_OV_CFG, 0x005400D0}, + {CS35L45_BOOST_UV_CFG, 0x00000570}, + {CS35L45_BOOST_STATUS, 0x00000001}, + {CS35L45_BST_BPE_INST_THLD, 0x5A46321E}, + {CS35L45_BST_BPE_INST_ILIM, 0x3C140C04}, + {CS35L45_BST_BPE_INST_SS_ILIM, 0x1C080400}, + {CS35L45_BST_BPE_INST_ATK_RATE, 0x06060600}, + {CS35L45_BST_BPE_INST_HOLD_TIME, 0x02020202}, + {CS35L45_BST_BPE_INST_RLS_RATE, 0x06060606}, + {CS35L45_BST_BPE_MISC_CONFIG, 0x00000000}, + {CS35L45_BST_BPE_IL_LIM_THLD, 0x0006022C}, + {CS35L45_BST_BPE_IL_LIM_DLY, 0x0000040C}, + {CS35L45_BST_BPE_IL_LIM_ATK_RATE, 0x00000000}, + {CS35L45_BST_BPE_IL_LIM_RLS_RATE, 0x00000000}, + {CS35L45_BST_BPE_INST_STATUS, 0x0000005A}, + {CS35L45_MONITOR_FILT, 0x00000000}, + {CS35L45_IMON_COMP, 0x00000036}, + {CS35L45_STATUS, 0x00000010}, + {CS35L45_MON_VALUE, 0x00000000}, + {CS35L45_ASP_ENABLES1, 0x00000000}, + {CS35L45_ASP_CONTROL1, 0x00000028}, + {CS35L45_ASP_CONTROL2, 0x18180200}, + {CS35L45_ASP_CONTROL3, 0x00000002}, + {CS35L45_ASP_FRAME_CONTROL1, 0x03020100}, + {CS35L45_ASP_FRAME_CONTROL2, 0x00000004}, + {CS35L45_ASP_FRAME_CONTROL5, 0x00000100}, + {CS35L45_ASP_DATA_CONTROL1, 0x00000018}, + {CS35L45_ASP_DATA_CONTROL5, 0x00000018}, + {CS35L45_DACPCM1_INPUT, 0x00000008}, + {CS35L45_ASPTX1_INPUT, 0x00000018}, + {CS35L45_ASPTX2_INPUT, 0x00000019}, + {CS35L45_ASPTX3_INPUT, 0x00000020}, + {CS35L45_ASPTX4_INPUT, 0x00000021}, + {CS35L45_ASPTX5_INPUT, 0x00000048}, + {CS35L45_DSP1RX1_INPUT, 0x00000008}, + {CS35L45_DSP1RX2_INPUT, 0x00000009}, + {CS35L45_DSP1RX3_INPUT, 0x00000018}, + {CS35L45_DSP1RX4_INPUT, 0x00000019}, + {CS35L45_DSP1RX5_INPUT, 0x00000020}, + {CS35L45_DSP1RX6_INPUT, 0x00000028}, + {CS35L45_DSP1RX7_INPUT, 0x0000003A}, + {CS35L45_DSP1RX8_INPUT, 0x00000028}, + {CS35L45_NGATE1_INPUT, 0x00000008}, + {CS35L45_NGATE2_INPUT, 0x00000009}, + {CS35L45_SWIRE_PORT1_CH1_INPUT, 0x00000018}, + {CS35L45_SWIRE_PORT1_CH2_INPUT, 0x00000019}, + {CS35L45_SWIRE_PORT1_CH3_INPUT, 0x00000020}, + {CS35L45_SWIRE_PORT1_CH4_INPUT, 0x00000021}, + {CS35L45_SWIRE_PORT1_CH5_INPUT, 0x00000048}, + {CS35L45_AMP_ERR_VOL_SEL, 0x00000001}, + {CS35L45_TEMP_WARN_THRESHOLD, 0x00000003}, + {CS35L45_TEMP_WARN_CONFIG, 0x00522183}, + {CS35L45_TEMP_WARN_TRIG_AUTO, 0x00000010}, + {CS35L45_TEMP_WARN_STATUS, 0x00000000}, + {CS35L45_BPE_INST_THLD, 0x5A46321E}, + {CS35L45_BPE_INST_ATTN, 0x060C1218}, + {CS35L45_BPE_INST_ATK_RATE, 0x06060606}, + {CS35L45_BPE_INST_HOLD_TIME, 0x02020202}, + {CS35L45_BPE_INST_RLS_RATE, 0x05050505}, + {CS35L45_BPE_MISC_CONFIG, 0x00008000}, + {CS35L45_BPE_INST_STATUS, 0x0000005A}, + {CS35L45_HVLV_CONFIG, 0x00440017}, + {CS35L45_LDPM_CONFIG, 0x00013636}, + {CS35L45_CLASSH_CONFIG1, 0x02000B04}, + {CS35L45_CLASSH_CONFIG2, 0x009600FA}, + {CS35L45_CLASSH_CONFIG3, 0x00000000}, + {CS35L45_AUD_MEM, 0x00000007}, + {CS35L45_AMP_PCM_CONTROL, 0x00100000}, + {CS35L45_AMP_GAIN, 0x00002300}, + {CS35L45_DAC_MSM_CONFIG, 0x00000020}, + {CS35L45_AMP_OUTPUT_MUTE, 0x00000000}, + {CS35L45_AMP_OUTPUT_DRV, 0x00000040}, + {CS35L45_ALIVE_DCIN_WD, 0x00000263}, + {CS35L45_IRQ1_CFG, 0x00000000}, + {CS35L45_IRQ2_CFG, 0x00000000}, + {CS35L45_GPIO1_CTRL1, 0x81000001}, + {CS35L45_GPIO2_CTRL1, 0x81000001}, + {CS35L45_GPIO3_CTRL1, 0x81000001}, + {CS35L45_MIXER_NGATE_CH1_CFG, 0x00000303}, + {CS35L45_MIXER_NGATE_CH2_CFG, 0x00000303}, + {CS35L45_CLOCK_DETECT_1, 0x00000030}, +}; + +bool cs35l45_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L45_DEVID: + case CS35L45_REVID: + case CS35L45_RELID: + case CS35L45_OTPID: + case CS35L45_SFT_RESET: + case CS35L45_GLOBAL_ENABLES: + case CS35L45_BLOCK_ENABLES: + case CS35L45_BLOCK_ENABLES2: + case CS35L45_GLOBAL_OVERRIDES: + case CS35L45_GLOBAL_SYNC: + case CS35L45_ERROR_RELEASE: + case CS35L45_CHIP_STATUS: + case CS35L45_REG_2114: + case CS35L45_REG_225C: + case CS35L45_SYNC_GPIO1: + case CS35L45_INTB_GPIO2_MCLK_REF: + case CS35L45_GPIO3: + case CS35L45_GPIO_GLOBAL_ENABLE_CONTROL: + case CS35L45_PWRMGT_CTL: + case CS35L45_WAKESRC_CTL: + case CS35L45_WKI2C_CTL: + case CS35L45_PWRMGT_STS: + case CS35L45_REFCLK_INPUT: + case CS35L45_REG_2C08: + case CS35L45_GLOBAL_SAMPLE_RATE: + case CS35L45_SWIRE_CLK_CTRL: + case CS35L45_SYNC_TX_RX_ENABLES: + case CS35L45_SYNC_SW_TX_ID: + case CS35L45_BOOST_VOLTAGE_CFG: + case CS35L45_BOOST_CCM_CFG: + case CS35L45_BOOST_DCM_CFG: + case CS35L45_BOOST_LPMODE_CFG: + case CS35L45_BOOST_RAMP_CFG: + case CS35L45_BOOST_STARTUP_CFG: + case CS35L45_BOOST_OV_CFG: + case CS35L45_BOOST_UV_CFG: + case CS35L45_BOOST_STATUS: + case CS35L45_BST_BPE_INST_THLD: + case CS35L45_BST_BPE_INST_ILIM: + case CS35L45_BST_BPE_INST_SS_ILIM: + case CS35L45_BST_BPE_INST_ATK_RATE: + case CS35L45_BST_BPE_INST_HOLD_TIME: + case CS35L45_BST_BPE_INST_RLS_RATE: + case CS35L45_BST_BPE_MISC_CONFIG: + case CS35L45_BST_BPE_IL_LIM_THLD: + case CS35L45_BST_BPE_IL_LIM_DLY: + case CS35L45_BST_BPE_IL_LIM_ATK_RATE: + case CS35L45_BST_BPE_IL_LIM_RLS_RATE: + case CS35L45_BST_BPE_INST_STATUS: + case CS35L45_MONITOR_FILT: + case CS35L45_IMON_COMP: + case CS35L45_STATUS: + case CS35L45_MON_VALUE: + case CS35L45_ASP_ENABLES1: + case CS35L45_ASP_CONTROL1: + case CS35L45_ASP_CONTROL2: + case CS35L45_ASP_CONTROL3: + case CS35L45_ASP_FRAME_CONTROL1: + case CS35L45_ASP_FRAME_CONTROL2: + case CS35L45_ASP_FRAME_CONTROL5: + case CS35L45_ASP_DATA_CONTROL1: + case CS35L45_ASP_DATA_CONTROL5: + case CS35L45_DACPCM1_INPUT: + case CS35L45_MIXER_PILOT0_INPUT: + case CS35L45_ASPTX1_INPUT: + case CS35L45_ASPTX2_INPUT: + case CS35L45_ASPTX3_INPUT: + case CS35L45_ASPTX4_INPUT: + case CS35L45_ASPTX5_INPUT: + case CS35L45_DSP1RX1_INPUT: + case CS35L45_DSP1RX2_INPUT: + case CS35L45_DSP1RX3_INPUT: + case CS35L45_DSP1RX4_INPUT: + case CS35L45_DSP1RX5_INPUT: + case CS35L45_DSP1RX6_INPUT: + case CS35L45_DSP1RX7_INPUT: + case CS35L45_DSP1RX8_INPUT: + case CS35L45_NGATE1_INPUT: + case CS35L45_NGATE2_INPUT: + case CS35L45_SWIRE_PORT1_CH1_INPUT: + case CS35L45_SWIRE_PORT1_CH2_INPUT: + case CS35L45_SWIRE_PORT1_CH3_INPUT: + case CS35L45_SWIRE_PORT1_CH4_INPUT: + case CS35L45_SWIRE_PORT1_CH5_INPUT: + case CS35L45_AMP_ERR_VOL_SEL: + case CS35L45_TEMP_WARN_THRESHOLD: + case CS35L45_TEMP_WARN_CONFIG: + case CS35L45_TEMP_WARN_TRIG_AUTO: + case CS35L45_TEMP_WARN_STATUS: + case CS35L45_BPE_INST_THLD: + case CS35L45_BPE_INST_ATTN: + case CS35L45_BPE_INST_ATK_RATE: + case CS35L45_BPE_INST_HOLD_TIME: + case CS35L45_BPE_INST_RLS_RATE: + case CS35L45_BPE_MISC_CONFIG: + case CS35L45_BPE_INST_STATUS: + case CS35L45_HVLV_CONFIG: + case CS35L45_LDPM_CONFIG: + case CS35L45_CLASSH_CONFIG1: + case CS35L45_CLASSH_CONFIG2: + case CS35L45_CLASSH_CONFIG3: + case CS35L45_AUD_MEM: + case CS35L45_AMP_PCM_CONTROL: + case CS35L45_AMP_GAIN: + case CS35L45_DAC_MSM_CONFIG: + case CS35L45_AMP_OUTPUT_MUTE: + case CS35L45_AMP_OUTPUT_DRV: + case CS35L45_ALIVE_DCIN_WD: + case CS35L45_IRQ1_CFG: + case CS35L45_IRQ1_STATUS: + case CS35L45_IRQ1_EINT_1: + case CS35L45_IRQ1_EINT_2: + case CS35L45_IRQ1_EINT_3: + case CS35L45_IRQ1_EINT_4: + case CS35L45_IRQ1_EINT_5: + case CS35L45_IRQ1_EINT_7: + case CS35L45_IRQ1_EINT_8: + case CS35L45_IRQ1_EINT_18: + case CS35L45_IRQ1_STS_1: + case CS35L45_IRQ1_STS_2: + case CS35L45_IRQ1_STS_3: + case CS35L45_IRQ1_STS_4: + case CS35L45_IRQ1_STS_5: + case CS35L45_IRQ1_STS_7: + case CS35L45_IRQ1_STS_8: + case CS35L45_IRQ1_STS_18: + case CS35L45_IRQ1_MASK_1: + case CS35L45_IRQ1_MASK_2: + case CS35L45_IRQ1_MASK_3: + case CS35L45_IRQ1_MASK_4: + case CS35L45_IRQ1_MASK_5: + case CS35L45_IRQ1_MASK_7: + case CS35L45_IRQ1_MASK_8: + case CS35L45_IRQ1_MASK_18: + case CS35L45_IRQ1_EDGE_1: + case CS35L45_IRQ1_EDGE_4: + case CS35L45_IRQ1_POL_1: + case CS35L45_IRQ1_POL_2: + case CS35L45_IRQ1_POL_4: + case CS35L45_IRQ1_DB_3: + case CS35L45_IRQ2_CFG: + case CS35L45_IRQ2_STATUS: + case CS35L45_IRQ2_EINT_1: + case CS35L45_IRQ2_EINT_2: + case CS35L45_IRQ2_EINT_3: + case CS35L45_IRQ2_EINT_4: + case CS35L45_IRQ2_EINT_5: + case CS35L45_IRQ2_EINT_7: + case CS35L45_IRQ2_EINT_8: + case CS35L45_IRQ2_EINT_18: + case CS35L45_IRQ2_STS_1: + case CS35L45_IRQ2_STS_2: + case CS35L45_IRQ2_STS_3: + case CS35L45_IRQ2_STS_4: + case CS35L45_IRQ2_STS_5: + case CS35L45_IRQ2_STS_7: + case CS35L45_IRQ2_STS_8: + case CS35L45_IRQ2_STS_18: + case CS35L45_IRQ2_MASK_1: + case CS35L45_IRQ2_MASK_2: + case CS35L45_IRQ2_MASK_3: + case CS35L45_IRQ2_MASK_4: + case CS35L45_IRQ2_MASK_5: + case CS35L45_IRQ2_MASK_7: + case CS35L45_IRQ2_MASK_8: + case CS35L45_IRQ2_MASK_18: + case CS35L45_IRQ2_EDGE_1: + case CS35L45_IRQ2_EDGE_4: + case CS35L45_IRQ2_POL_1: + case CS35L45_IRQ2_POL_2: + case CS35L45_IRQ2_POL_4: + case CS35L45_IRQ2_DB_3: + case CS35L45_GPIO_STATUS1: + case CS35L45_GPIO1_CTRL1: + case CS35L45_GPIO2_CTRL1: + case CS35L45_GPIO3_CTRL1: + case CS35L45_MIXER_NGATE_CH1_CFG: + case CS35L45_MIXER_NGATE_CH2_CFG: + case CS35L45_DSP_MBOX_1: + case CS35L45_DSP_MBOX_2: + case CS35L45_DSP_MBOX_3: + case CS35L45_DSP_MBOX_4: + case CS35L45_DSP_MBOX_5: + case CS35L45_DSP_MBOX_6: + case CS35L45_DSP_MBOX_7: + case CS35L45_DSP_MBOX_8: + case CS35L45_DSP_VIRT1_MBOX_1: + case CS35L45_DSP_VIRT1_MBOX_2: + case CS35L45_DSP_VIRT1_MBOX_3: + case CS35L45_DSP_VIRT1_MBOX_4: + case CS35L45_DSP_VIRT1_MBOX_5: + case CS35L45_DSP_VIRT1_MBOX_6: + case CS35L45_DSP_VIRT1_MBOX_7: + case CS35L45_DSP_VIRT1_MBOX_8: + case CS35L45_DSP_VIRT2_MBOX_1: + case CS35L45_DSP_VIRT2_MBOX_2: + case CS35L45_DSP_VIRT2_MBOX_3: + case CS35L45_DSP_VIRT2_MBOX_4: + case CS35L45_DSP_VIRT2_MBOX_5: + case CS35L45_DSP_VIRT2_MBOX_6: + case CS35L45_DSP_VIRT2_MBOX_7: + case CS35L45_DSP_VIRT2_MBOX_8: + case CS35L45_CLOCK_DETECT_1: + case CS35L45_DSP1_SYS_ID: + case CS35L45_DSP1_CLOCK_FREQ: + case CS35L45_DSP1_RX1_RATE: + case CS35L45_DSP1_RX2_RATE: + case CS35L45_DSP1_RX3_RATE: + case CS35L45_DSP1_RX4_RATE: + case CS35L45_DSP1_RX5_RATE: + case CS35L45_DSP1_RX6_RATE: + case CS35L45_DSP1_RX7_RATE: + case CS35L45_DSP1_RX8_RATE: + case CS35L45_DSP1_TX1_RATE: + case CS35L45_DSP1_TX2_RATE: + case CS35L45_DSP1_TX3_RATE: + case CS35L45_DSP1_TX4_RATE: + case CS35L45_DSP1_TX5_RATE: + case CS35L45_DSP1_TX6_RATE: + case CS35L45_DSP1_TX7_RATE: + case CS35L45_DSP1_TX8_RATE: + case CS35L45_DSP1_SCRATCH1: + case CS35L45_DSP1_SCRATCH2: + case CS35L45_DSP1_SCRATCH3: + case CS35L45_DSP1_SCRATCH4: + case CS35L45_DSP1_CCM_CORE_CONTROL: + case CS35L45_DSP1_STREAM_ARB_MSTR1_CONFIG_0: + case CS35L45_DSP1_STREAM_ARB_TX1_CONFIG_0: + case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607: + case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071: + case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143: + case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532: + case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022: + case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043: + case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834: + return true; + default: + return false; + } +} + +bool cs35l45_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L45_DEVID: + case CS35L45_SFT_RESET: + case CS35L45_REVID: + case CS35L45_GLOBAL_ENABLES: + case CS35L45_BLOCK_ENABLES: + case CS35L45_BLOCK_ENABLES2: + case CS35L45_GLOBAL_OVERRIDES: + case CS35L45_CHIP_STATUS: + case CS35L45_PWRMGT_STS: + case CS35L45_SYNC_TX_RX_ENABLES: + case CS35L45_SYNC_SW_TX_ID: + case CS35L45_BOOST_CCM_CFG: + case CS35L45_BOOST_DCM_CFG: + case CS35L45_BOOST_OV_CFG: + case CS35L45_BOOST_STATUS: + case CS35L45_BST_BPE_INST_STATUS: + case CS35L45_STATUS: + case CS35L45_REG_2114: + case CS35L45_REG_225C: + case CS35L45_REG_2C08: + case CS35L45_MON_VALUE: + case CS35L45_LDPM_CONFIG: + case CS35L45_IRQ1_STATUS: + case CS35L45_IRQ1_EINT_1: + case CS35L45_IRQ1_EINT_2: + case CS35L45_IRQ1_EINT_3: + case CS35L45_IRQ1_EINT_4: + case CS35L45_IRQ1_EINT_5: + case CS35L45_IRQ1_EINT_7: + case CS35L45_IRQ1_EINT_8: + case CS35L45_IRQ1_EINT_18: + case CS35L45_IRQ1_STS_1: + case CS35L45_IRQ1_STS_2: + case CS35L45_IRQ1_STS_3: + case CS35L45_IRQ1_STS_4: + case CS35L45_IRQ1_STS_5: + case CS35L45_IRQ1_STS_7: + case CS35L45_IRQ1_STS_8: + case CS35L45_IRQ1_STS_18: + case CS35L45_IRQ2_STATUS: + case CS35L45_IRQ2_EINT_1: + case CS35L45_IRQ2_EINT_2: + case CS35L45_IRQ2_EINT_3: + case CS35L45_IRQ2_EINT_4: + case CS35L45_IRQ2_EINT_5: + case CS35L45_IRQ2_EINT_7: + case CS35L45_IRQ2_EINT_8: + case CS35L45_IRQ2_EINT_18: + case CS35L45_IRQ2_STS_1: + case CS35L45_IRQ2_STS_2: + case CS35L45_IRQ2_STS_3: + case CS35L45_IRQ2_STS_4: + case CS35L45_IRQ2_STS_5: + case CS35L45_IRQ2_STS_7: + case CS35L45_IRQ2_STS_8: + case CS35L45_IRQ2_STS_18: + case CS35L45_GPIO_STATUS1: + case CS35L45_DSP_MBOX_1: + case CS35L45_DSP_MBOX_2: + case CS35L45_DSP_MBOX_3: + case CS35L45_DSP_MBOX_4: + case CS35L45_DSP_MBOX_5: + case CS35L45_DSP_MBOX_6: + case CS35L45_DSP_MBOX_7: + case CS35L45_DSP_MBOX_8: + case CS35L45_DSP_VIRT1_MBOX_1: + case CS35L45_DSP_VIRT1_MBOX_2: + case CS35L45_DSP_VIRT1_MBOX_3: + case CS35L45_DSP_VIRT1_MBOX_4: + case CS35L45_DSP_VIRT1_MBOX_5: + case CS35L45_DSP_VIRT1_MBOX_6: + case CS35L45_DSP_VIRT1_MBOX_7: + case CS35L45_DSP_VIRT1_MBOX_8: + case CS35L45_DSP_VIRT2_MBOX_1: + case CS35L45_DSP_VIRT2_MBOX_2: + case CS35L45_DSP_VIRT2_MBOX_3: + case CS35L45_DSP_VIRT2_MBOX_4: + case CS35L45_DSP_VIRT2_MBOX_5: + case CS35L45_DSP_VIRT2_MBOX_6: + case CS35L45_DSP_VIRT2_MBOX_7: + case CS35L45_DSP_VIRT2_MBOX_8: + case CS35L45_DSP1_SCRATCH1: + case CS35L45_DSP1_SCRATCH2: + case CS35L45_DSP1_SCRATCH3: + case CS35L45_DSP1_SCRATCH4: + case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607: + case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071: + case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143: + case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532: + case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022: + case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043: + case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834: + return true; + default: + return false; + } +} + +const struct cs35l45_pll_sysclk_config + cs35l45_pll_sysclk[CS35L45_MAX_PLL_CONFIGS] = { + { 32768, 0x00 }, + { 8000, 0x01 }, + { 11025, 0x02 }, + { 12000, 0x03 }, + { 16000, 0x04 }, + { 22050, 0x05 }, + { 24000, 0x06 }, + { 32000, 0x07 }, + { 44100, 0x08 }, + { 48000, 0x09 }, + { 88200, 0x0A }, + { 96000, 0x0B }, + { 128000, 0x0C }, + { 176400, 0x0D }, + { 192000, 0x0E }, + { 256000, 0x0F }, + { 352800, 0x10 }, + { 384000, 0x11 }, + { 512000, 0x12 }, + { 705600, 0x13 }, + { 750000, 0x14 }, + { 768000, 0x15 }, + { 1000000, 0x16 }, + { 1024000, 0x17 }, + { 1200000, 0x18 }, + { 1411200, 0x19 }, + { 1500000, 0x1A }, + { 1536000, 0x1B }, + { 2000000, 0x1C }, + { 2048000, 0x1D }, + { 2400000, 0x1E }, + { 2822400, 0x1F }, + { 3000000, 0x20 }, + { 3072000, 0x21 }, + { 3200000, 0x22 }, + { 4000000, 0x23 }, + { 4096000, 0x24 }, + { 4800000, 0x25 }, + { 5644800, 0x26 }, + { 6000000, 0x27 }, + { 6144000, 0x28 }, + { 6250000, 0x29 }, + { 6400000, 0x2A }, + { 6500000, 0x2B }, + { 6750000, 0x2C }, + { 7526400, 0x2D }, + { 8000000, 0x2E }, + { 8192000, 0x2F }, + { 9600000, 0x30 }, + { 11289600, 0x31 }, + { 12000000, 0x32 }, + { 12288000, 0x33 }, + { 12500000, 0x34 }, + { 12800000, 0x35 }, + { 13000000, 0x36 }, + { 13500000, 0x37 }, + { 19200000, 0x38 }, + { 22579200, 0x39 }, + { 24000000, 0x3A }, + { 24576000, 0x3B }, + { 25000000, 0x3C }, + { 25600000, 0x3D }, + { 26000000, 0x3E }, + { 27000000, 0x3F }, +}; + +const struct of_entry bst_bpe_inst_thld_map[BST_BPE_INST_LEVELS] = { + [L0] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD, + CS35L45_BST_BPE_INST_L0_THLD_MASK, + CS35L45_BST_BPE_INST_L0_THLD_SHIFT}, + [L1] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD, + CS35L45_BST_BPE_INST_L1_THLD_MASK, + CS35L45_BST_BPE_INST_L1_THLD_SHIFT}, + [L2] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD, + CS35L45_BST_BPE_INST_L2_THLD_MASK, + CS35L45_BST_BPE_INST_L2_THLD_SHIFT}, + [L3] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD, + CS35L45_BST_BPE_INST_L3_THLD_MASK, + CS35L45_BST_BPE_INST_L3_THLD_SHIFT}, + [L4] = {"bst-bpe-inst-thld", 0, 0, 0}, +}; + +const struct of_entry bst_bpe_inst_ilim_map[BST_BPE_INST_LEVELS] = { + [L0] = {"bst-bpe-inst-ilim", 0, 0, 0}, + [L1] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM, + CS35L45_BST_BPE_INST_L1_ILIM_MASK, + CS35L45_BST_BPE_INST_L1_ILIM_SHIFT}, + [L2] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM, + CS35L45_BST_BPE_INST_L2_ILIM_MASK, + CS35L45_BST_BPE_INST_L2_ILIM_SHIFT}, + [L3] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM, + CS35L45_BST_BPE_INST_L3_ILIM_MASK, + CS35L45_BST_BPE_INST_L3_ILIM_SHIFT}, + [L4] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM, + CS35L45_BST_BPE_INST_L4_ILIM_MASK, + CS35L45_BST_BPE_INST_L4_ILIM_SHIFT}, +}; + +const struct of_entry bst_bpe_inst_ss_ilim_map[BST_BPE_INST_LEVELS] = { + [L0] = {"bst-bpe-inst-ss-ilim", 0, 0, 0}, + [L1] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM, + CS35L45_BST_BPE_INST_L1_SS_ILIM_MASK, + CS35L45_BST_BPE_INST_L1_SS_ILIM_SHIFT}, + [L2] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM, + CS35L45_BST_BPE_INST_L2_SS_ILIM_MASK, + CS35L45_BST_BPE_INST_L2_SS_ILIM_SHIFT}, + [L3] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM, + CS35L45_BST_BPE_INST_L3_SS_ILIM_MASK, + CS35L45_BST_BPE_INST_L3_SS_ILIM_SHIFT}, + [L4] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM, + CS35L45_BST_BPE_INST_L4_SS_ILIM_MASK, + CS35L45_BST_BPE_INST_L4_SS_ILIM_SHIFT}, +}; + +const struct of_entry bst_bpe_inst_atk_rate_map[BST_BPE_INST_LEVELS] = { + [L0] = {"bst-bpe-inst-atk-rate", 0, 0, 0}, + [L1] = {"bst-bpe-inst-atk-rate", CS35L45_BST_BPE_INST_ATK_RATE, + CS35L45_BST_BPE_INST_L1_ATK_RATE_MASK, + CS35L45_BST_BPE_INST_L1_ATK_RATE_SHIFT}, + [L2] = {"bst-bpe-inst-atk-rate", CS35L45_BST_BPE_INST_ATK_RATE, + CS35L45_BST_BPE_INST_L2_ATK_RATE_MASK, + CS35L45_BST_BPE_INST_L2_ATK_RATE_SHIFT}, + [L3] = {"bst-bpe-inst-atk-rate", CS35L45_BST_BPE_INST_ATK_RATE, + CS35L45_BST_BPE_INST_L3_ATK_RATE_MASK, + CS35L45_BST_BPE_INST_L3_ATK_RATE_SHIFT}, + [L4] = {"bst-bpe-inst-atk-rate", 0, 0, 0}, +}; + +const struct of_entry bst_bpe_inst_hold_time_map[BST_BPE_INST_LEVELS] = { + [L0] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME, + CS35L45_BST_BPE_INST_L0_HOLD_TIME_MASK, + CS35L45_BST_BPE_INST_L0_HOLD_TIME_SHIFT}, + [L1] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME, + CS35L45_BST_BPE_INST_L1_HOLD_TIME_MASK, + CS35L45_BST_BPE_INST_L1_HOLD_TIME_SHIFT}, + [L2] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME, + CS35L45_BST_BPE_INST_L2_HOLD_TIME_MASK, + CS35L45_BST_BPE_INST_L2_HOLD_TIME_SHIFT}, + [L3] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME, + CS35L45_BST_BPE_INST_L3_HOLD_TIME_MASK, + CS35L45_BST_BPE_INST_L3_HOLD_TIME_SHIFT}, + [L4] = {"bst-bpe-inst-hold-time", 0, 0, 0}, +}; + +const struct of_entry bst_bpe_inst_rls_rate_map[BST_BPE_INST_LEVELS] = { + [L0] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE, + CS35L45_BST_BPE_INST_L0_RLS_RATE_MASK, + CS35L45_BST_BPE_INST_L0_RLS_RATE_SHIFT}, + [L1] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE, + CS35L45_BST_BPE_INST_L1_RLS_RATE_MASK, + CS35L45_BST_BPE_INST_L1_RLS_RATE_SHIFT}, + [L2] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE, + CS35L45_BST_BPE_INST_L2_RLS_RATE_MASK, + CS35L45_BST_BPE_INST_L2_RLS_RATE_SHIFT}, + [L3] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE, + CS35L45_BST_BPE_INST_L3_RLS_RATE_MASK, + CS35L45_BST_BPE_INST_L3_RLS_RATE_SHIFT}, + [L4] = {"bst-bpe-inst-rls-rate", 0, 0, 0}, +}; + +const struct of_entry bst_bpe_misc_map[BST_BPE_MISC_PARAMS] = { + [BST_BPE_INST_INF_HOLD_RLS] = {"bst-bpe-inst-inf-hold-rls", + CS35L45_BST_BPE_MISC_CONFIG, + CS35L45_BST_BPE_INST_INF_HOLD_RLS_MASK, + CS35L45_BST_BPE_INST_INF_HOLD_RLS_SHIFT}, + [BST_BPE_IL_LIM_MODE] = {"bst-bpe-il-lim-mode", + CS35L45_BST_BPE_MISC_CONFIG, + CS35L45_BST_BPE_IL_LIM_MODE_MASK, + CS35L45_BST_BPE_IL_LIM_MODE_SHIFT}, + [BST_BPE_OUT_OPMODE_SEL] = {"bst-bpe-out-opmode-sel", + CS35L45_BST_BPE_MISC_CONFIG, + CS35L45_BST_BPE_OUT_OPMODE_SEL_MASK, + CS35L45_BST_BPE_OUT_OPMODE_SEL_SHIFT}, + [BST_BPE_INST_L3_BYP] = {"bst-bpe-inst-l3-byp", + CS35L45_BST_BPE_MISC_CONFIG, + CS35L45_BST_BPE_INST_L3_BYP_MASK, + CS35L45_BST_BPE_INST_L3_BYP_SHIFT}, + [BST_BPE_INST_L2_BYP] = {"bst-bpe-inst-l2-byp", + CS35L45_BST_BPE_MISC_CONFIG, + CS35L45_BST_BPE_INST_L2_BYP_MASK, + CS35L45_BST_BPE_INST_L2_BYP_SHIFT}, + [BST_BPE_INST_L1_BYP] = {"bst-bpe-inst-l1-byp", + CS35L45_BST_BPE_MISC_CONFIG, + CS35L45_BST_BPE_INST_L1_BYP_MASK, + CS35L45_BST_BPE_INST_L1_BYP_SHIFT}, + [BST_BPE_FILT_SEL] = {"bst-bpe-filt-sel", + CS35L45_BST_BPE_MISC_CONFIG, + CS35L45_BST_BPE_FILT_SEL_MASK, + CS35L45_BST_BPE_FILT_SEL_SHIFT}, +}; + +const struct of_entry bst_bpe_il_lim_map[BST_BPE_IL_LIM_PARAMS] = { + [BST_BPE_IL_LIM_THLD_DEL1] = {"bst-bpe-il-lim-thld-del1", + CS35L45_BST_BPE_IL_LIM_THLD, + CS35L45_BST_BPE_IL_LIM_THLD_DEL1_MASK, + CS35L45_BST_BPE_IL_LIM_THLD_DEL1_SHIFT}, + [BST_BPE_IL_LIM_THLD_DEL2] = {"bst-bpe-il-lim-thld-del2", + CS35L45_BST_BPE_IL_LIM_THLD, + CS35L45_BST_BPE_IL_LIM_THLD_DEL2_MASK, + CS35L45_BST_BPE_IL_LIM_THLD_DEL2_SHIFT}, + [BST_BPE_IL_LIM1_THLD] = {"bst-bpe-il-lim1-thld", + CS35L45_BST_BPE_IL_LIM_THLD, + CS35L45_BST_BPE_IL_LIM1_THLD_MASK, + CS35L45_BST_BPE_IL_LIM1_THLD_SHIFT}, + [BST_BPE_IL_LIM1_DLY] = {"bst-bpe-il-lim1-dly", + CS35L45_BST_BPE_IL_LIM_DLY, + CS35L45_BST_BPE_IL_LIM1_DLY_MASK, + CS35L45_BST_BPE_IL_LIM1_DLY_SHIFT}, + [BST_BPE_IL_LIM2_DLY] = {"bst-bpe-il-lim2-dly", + CS35L45_BST_BPE_IL_LIM_DLY, + CS35L45_BST_BPE_IL_LIM2_DLY_MASK, + CS35L45_BST_BPE_IL_LIM2_DLY_SHIFT}, + [BST_BPE_IL_LIM_DLY_HYST] = {"bst-bpe-il-lim-dly-hyst", + CS35L45_BST_BPE_IL_LIM_DLY, + CS35L45_BST_BPE_IL_LIM_DLY_HYST_MASK, + CS35L45_BST_BPE_IL_LIM_DLY_HYST_SHIFT}, + [BST_BPE_IL_LIM_THLD_HYST] = {"bst-bpe-il-lim-thld-hyst", + CS35L45_BST_BPE_IL_LIM_THLD, + CS35L45_BST_BPE_IL_LIM_THLD_HYST_MASK, + CS35L45_BST_BPE_IL_LIM_THLD_HYST_SHIFT}, + [BST_BPE_IL_LIM1_ATK_RATE] = {"bst-bpe-il-lim1-atk-rate", + CS35L45_BST_BPE_IL_LIM_ATK_RATE, + CS35L45_BST_BPE_IL_LIM1_ATK_RATE_MASK, + CS35L45_BST_BPE_IL_LIM1_ATK_RATE_SHIFT}, + [BST_BPE_IL_LIM2_ATK_RATE] = {"bst-bpe-il-lim2-atk-rate", + CS35L45_BST_BPE_IL_LIM_ATK_RATE, + CS35L45_BST_BPE_IL_LIM2_ATK_RATE_MASK, + CS35L45_BST_BPE_IL_LIM2_ATK_RATE_SHIFT}, + [BST_BPE_IL_LIM1_RLS_RATE] = {"bst-bpe-il-lim1-rls-rate", + CS35L45_BST_BPE_IL_LIM_RLS_RATE, + CS35L45_BST_BPE_IL_LIM1_RLS_RATE_MASK, + CS35L45_BST_BPE_IL_LIM1_RLS_RATE_SHIFT}, + [BST_BPE_IL_LIM2_RLS_RATE] = {"bst-bpe-il-lim2-rls-rate", + CS35L45_BST_BPE_IL_LIM_RLS_RATE, + CS35L45_BST_BPE_IL_LIM2_RLS_RATE_MASK, + CS35L45_BST_BPE_IL_LIM2_RLS_RATE_SHIFT}, +}; + +const struct of_entry ldpm_map[LDPM_PARAMS] = { + [LDPM_GP1_BOOST_SEL] = {"ldpm-gp1-boost-sel", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP1_BOOST_SEL_MASK, + CS35L45_LDPM_GP1_BOOST_SEL_SHIFT}, + [LDPM_GP1_AMP_SEL] = {"ldpm-gp1-amp-sel", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP1_AMP_SEL_MASK, + CS35L45_LDPM_GP1_AMP_SEL_SHIFT}, + [LDPM_GP1_DELAY] = {"ldpm-gp1-delay", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP1_DELAY_MASK, + CS35L45_LDPM_GP1_DELAY_SHIFT}, + [LDPM_GP1_PCM_THLD] = {"ldpm-gp1-pcm-thld", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP1_PCM_THLD_MASK, + CS35L45_LDPM_GP1_PCM_THLD_SHIFT}, + [LDPM_GP2_IMON_SEL] = {"ldpm-gp2-imon-sel", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP2_IMON_SEL_MASK, + CS35L45_LDPM_GP2_IMON_SEL_SHIFT}, + [LDPM_GP2_VMON_SEL] = {"ldpm-gp2-vmon-sel", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP2_VMON_SEL_MASK, + CS35L45_LDPM_GP2_VMON_SEL_SHIFT}, + [LDPM_GP2_DELAY] = {"ldpm-gp2-delay", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP2_DELAY_MASK, + CS35L45_LDPM_GP2_DELAY_SHIFT}, + [LDPM_GP2_PCM_THLD] = {"ldpm-gp2-pcm-thld", CS35L45_LDPM_CONFIG, + CS35L45_LDPM_GP2_PCM_THLD_MASK, + CS35L45_LDPM_GP2_PCM_THLD_SHIFT}, +}; + +const struct of_entry classh_map[CLASSH_PARAMS] = { + [CH_HDRM] = {"ch-hdrm", CS35L45_CLASSH_CONFIG1, + CS35L45_CH_HDRM_MASK, CS35L45_CH_HDRM_SHIFT}, + [CH_RATIO] = {"ch-ratio", CS35L45_CLASSH_CONFIG1, + CS35L45_CH_RATIO_MASK, CS35L45_CH_RATIO_SHIFT}, + [CH_REL_RATE] = {"ch-rel-rate", CS35L45_CLASSH_CONFIG1, + CS35L45_CH_REL_RATE_MASK, CS35L45_CH_REL_RATE_SHIFT}, + [CH_OVB_THLD1] = {"ch-ovb-thld1", CS35L45_CLASSH_CONFIG2, + CS35L45_CH_OVB_THLD1_MASK, CS35L45_CH_OVB_THLD1_SHIFT}, + [CH_OVB_THLDDELTA] = {"ch-ovb-thlddelta", CS35L45_CLASSH_CONFIG2, + CS35L45_CH_OVB_THLDDELTA_MASK, CS35L45_CH_OVB_THLDDELTA_SHIFT}, + [CH_VDD_BST_MAX] = {"ch-vdd-bst-max", CS35L45_CLASSH_CONFIG2, + CS35L45_CH_VDD_BST_MAX_MASK, CS35L45_CH_VDD_BST_MAX_SHIFT}, + [CH_OVB_RATIO] = {"ch-ovb-ratio", CS35L45_CLASSH_CONFIG3, + CS35L45_CH_OVB_RATIO_MASK, CS35L45_CH_OVB_RATIO_SHIFT}, + [CH_THLD1_OFFSET] = {"ch-thld1-offset", CS35L45_CLASSH_CONFIG3, + CS35L45_CH_THLD1_OFFSET_MASK, CS35L45_CH_THLD1_OFFSET_SHIFT}, + [AUD_MEM_DEPTH] = {"aud-mem-depth", CS35L45_AUD_MEM, + CS35L45_AUD_MEM_DEPTH_MASK, CS35L45_AUD_MEM_DEPTH_SHIFT}, +}; diff --git a/techpack/audio/asoc/codecs/cs35l45/cs35l45.c b/techpack/audio/asoc/codecs/cs35l45/cs35l45.c new file mode 100644 index 0000000000000..6f04835b83167 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/cs35l45.c @@ -0,0 +1,3174 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * cs35l45.c - CS35L45 ALSA SoC audio driver + * + * Copyright 2019 Cirrus Logic, Inc. + * + * Author: James Schulman + * + */ +#define DEBUG + +//#define MDSYNC_CS +//#define FAST_SWITCH_DEBUG +#define FAST_SWITCH_WORKAROUND + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l45.h" +#include "cs35l45_user.h" + +static struct wm_adsp_ops cs35l45_halo_ops; +static int (*cs35l45_halo_start_core)(struct wm_adsp *dsp); + +static const char *cs35l45_fast_switch_text[] = { + "fast_switch1.txt", + "fast_switch2.txt", + "fast_switch3.txt", + "fast_switch4.txt", + "fast_switch5.txt", +}; + +static int cs35l45_fast_switch_en_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s: fast_switch_en = %d\n", __func__, cs35l45->fast_switch_en); + ucontrol->value.integer.value[0] = cs35l45->fast_switch_en; + + return 0; +} + +static int cs35l45_do_fast_switch(struct cs35l45_private *cs35l45) +{ + char val_str[CS35L45_BUFSIZE]; + const char *fw_name; + const struct firmware *fw; + int ret; + unsigned int i, j, k; + s32 data_ctl_len, val; + bool fw_running = false; + __be32 *data_ctl_buf, cmd_ctl, st_ctl; + + data_ctl_buf = NULL; + + fw_name = cs35l45->fast_switch_names[cs35l45->fast_switch_file_idx]; + dev_dbg(cs35l45->dev, "fw_name:%s\n", fw_name); + ret = request_firmware(&fw, fw_name, cs35l45->dev); + if (ret < 0) { + dev_err(cs35l45->dev, "Failed to request firmware:%s\n", + fw_name); + return -EIO; + } + + /* Parse number of data in file */ + for (i = 0, j = 0; (char)fw->data[i] != ','; i++) { + if ((char)fw->data[i] == ' ') { + /* Skip white space */ + } else { + /* fw->data[i] must be numerical digit */ + if (j < CS35L45_BUFSIZE - 1) { + val_str[j] = fw->data[i]; + j++; + } else { + dev_err(cs35l45->dev, "Invalid input\n"); + ret = -EINVAL; + goto exit; + } + } + } + i++; /* points to beginning of next number */ + val_str[j] = '\0'; + ret = kstrtos32(val_str, 10, &data_ctl_len); + if (ret < 0) { + dev_err(cs35l45->dev, "kstrtos32 failed (%d) val_str:%s\n", + ret, val_str); + goto exit; + } + + dev_dbg(cs35l45->dev, "data_ctl_len:%u\n", data_ctl_len); + + data_ctl_buf = kcalloc(1, data_ctl_len * sizeof(__be32), GFP_KERNEL); + if (!data_ctl_buf) { + ret = -ENOMEM; + goto exit; + } + + data_ctl_buf[0] = cpu_to_be32(data_ctl_len); + + /* i continues from end of previous loop */ + for (j = 0, k = 1; i <= fw->size; i++) { + if (i == fw->size || (char)fw->data[i] == ',') { + /* + * Reached end of parameter + * delimited either by ',' or end of file + * Parse number and write parameter + */ + val_str[j] = '\0'; + ret = kstrtos32(val_str, 10, &val); + if (ret < 0) { + dev_err(cs35l45->dev, + "kstrtos32 failed (%d) val_str:%s\n", + ret, val_str); + goto exit; + } + data_ctl_buf[k] = cpu_to_be32(val); + j = 0; + k++; + } else if ((char)fw->data[i] == ' ') { + /* Skip white space */ + } else { + /* fw->data[i] must be numerical digit */ + if (j < CS35L45_BUFSIZE - 1) { + val_str[j] = fw->data[i]; + j++; + } else { + dev_err(cs35l45->dev, "Invalid input\n"); + ret = -EINVAL; + goto exit; + } + } + } + + ret = wm_adsp_write_ctl(&cs35l45->dsp, "CSPL_UPDATE_PARAMS_CONFIG", + WMFW_ADSP2_YM, CS35L45_ALGID, data_ctl_buf, + data_ctl_len * sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, + "Failed to write CSPL_UPDATE_PARAMS_CONFIG\n"); + goto exit; + } + dev_dbg(cs35l45->dev, + "Wrote %u reg for CSPL_UPDATE_PARAMS_CONFIG\n", data_ctl_len); + +#ifdef FAST_SWITCH_DEBUG + ret = wm_adsp_read_ctl(&cs35l45->dsp, "CSPL_UPDATE_PARAMS_CONFIG", + WMFW_ADSP2_YM, CS35L45_ALGID, data_ctl_buf, + data_ctl_len * sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, + "Failed to read CSPL_UPDATE_PARAMS_CONFIG\n"); + goto exit; + } + dev_dbg(cs35l45->dev, "read CSPL_UPDATE_PARAMS_CONFIG:\n"); + for (i = 0; i < data_ctl_len; i++) + dev_dbg(cs35l45->dev, "%u\n", be32_to_cpu(data_ctl_buf[i])); +#endif + cmd_ctl = cpu_to_be32(CSPL_CMD_UPDATE_PARAM); + ret = wm_adsp_write_ctl(&cs35l45->dsp, "CSPL_COMMAND", WMFW_ADSP2_XM, + CS35L45_ALGID, &cmd_ctl, sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, "Failed to write CSPL_COMMAND\n"); + goto exit; + } + + /* Verify CSPL COMMAND */ + for (i = 0; i < 5; i++) { + ret = wm_adsp_read_ctl(&cs35l45->dsp, "CSPL_STATE", + WMFW_ADSP2_XM, CS35L45_ALGID, + &st_ctl, sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, "Failed to read CSPL_STATE\n"); + goto exit; + } + if (be32_to_cpu(st_ctl) == CSPL_ST_RUNNING) { + dev_dbg(cs35l45->dev, + "CSPL STATE == RUNNING (%u attempt)\n", i); + fw_running = true; + break; + } + + usleep_range(100, 110); + } + + if (!fw_running) { + dev_err(cs35l45->dev, "CSPL_STATE (%d) is not running\n", + st_ctl); + ret = -1; + goto exit; + } +exit: + kfree(data_ctl_buf); + release_firmware(fw); + return ret; +} + +static int cs35l45_fast_switch_en_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s: fast_switch_en = %ld\n", __func__, ucontrol->value.integer.value[0]); + + #if !defined(FAST_SWITCH_WORKAROUND) + if (!cs35l45->fast_switch_en && ucontrol->value.integer.value[0]) + /* + * Rising on fast switch enable + * Perform fast use case switching + */ + ret = cs35l45_do_fast_switch(cs35l45); + #endif + + cs35l45->fast_switch_en = ucontrol->value.integer.value[0]; + + return ret; +} + +static int cs35l45_fast_switch_file_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + struct soc_enum *soc_enum; + unsigned int i = ucontrol->value.enumerated.item[0]; + + dev_dbg(cs35l45->dev, "%s: fast_switch_file_idx = %u\n", __func__, i); + soc_enum = (struct soc_enum *)kcontrol->private_value; + + if (i >= soc_enum->items) { + dev_err(cs35l45->dev, "Invalid mixer input (%u)\n", i); + return -EINVAL; + } + + #if defined(FAST_SWITCH_WORKAROUND) + if (!cs35l45->dsp.running) { + dev_err(cs35l45->dev, "DSP not running\n"); + return 0; + } + + if ((i != cs35l45->fast_switch_file_idx) && cs35l45->fast_switch_en) { + int ret; + + cs35l45->fast_switch_file_idx = i; + ret = cs35l45_do_fast_switch(cs35l45); + dev_dbg(cs35l45->dev, "%s: fast switch %s\n", __func__, ret ? "fail" : "success"); + } + #endif + + return 0; +} + +static int cs35l45_fast_switch_file_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s: fast_switch_file_idx = %u\n", __func__, cs35l45->fast_switch_file_idx); + ucontrol->value.enumerated.item[0] = cs35l45->fast_switch_file_idx; + + return 0; +} + +struct cs35l45_mixer_cache { + unsigned int reg; + unsigned int mask; + unsigned int val; +}; + +static int __cs35l45_initialize(struct cs35l45_private *cs35l45); +static int cs35l45_hibernate(struct cs35l45_private *cs35l45, bool hiber_en); +static int cs35l45_set_sysclk(struct cs35l45_private *cs35l45, int clk_id, + unsigned int freq); + +static void cs35l45_dsp_pmd_work(struct work_struct *work) +{ + struct cs35l45_private *cs35l45 = container_of(work, + struct cs35l45_private, + dsp_pmd_work); + unsigned int pll_sts, pwr_sts, timeout; + + dev_dbg(cs35l45->dev, "%s: PLL_FORCE_EN to be disabled\n", __func__); + mutex_lock(&cs35l45->dsp_pmd_lock); + + timeout = 50; + do { + regmap_read(cs35l45->regmap, CS35L45_IRQ1_STS_1, &pwr_sts); + regmap_read(cs35l45->regmap, CS35L45_IRQ1_STS_3, &pll_sts); + + pwr_sts &= CS35L45_MSM_GLOBAL_EN_ASSERT_MASK; + pll_sts &= CS35L45_PLL_LOCK_FLAG_MASK; + + usleep_range(1000, 1100); + timeout--; + } while (pwr_sts && pll_sts && timeout); + + if (timeout == 0) + dev_err(cs35l45->dev, "Timeout for PLL disable conditions\n"); + else + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_FORCE_EN_MASK, 0); + + mutex_unlock(&cs35l45->dsp_pmd_lock); + dev_dbg(cs35l45->dev, "%s: PLL_FORCE_EN is disabled\n", __func__); +} + +static bool cs35l45_is_csplmboxsts_correct(enum cspl_mboxcmd cmd, + enum cspl_mboxstate sts) +{ + switch (cmd) { + case CSPL_MBOX_CMD_NONE: + case CSPL_MBOX_CMD_UNKNOWN_CMD: + return true; + case CSPL_MBOX_CMD_PAUSE: + return (sts == CSPL_MBOX_STS_PAUSED); + case CSPL_MBOX_CMD_RESUME: + return (sts == CSPL_MBOX_STS_RUNNING); + case CSPL_MBOX_CMD_REINIT: + return (sts == CSPL_MBOX_STS_RUNNING); + case CSPL_MBOX_CMD_STOP_PRE_REINIT: + return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); + case CSPL_MBOX_CMD_HIBERNATE: + return (sts == CSPL_MBOX_STS_HIBERNATE); + case CSPL_MBOX_CMD_OUT_OF_HIBERNATE: + return (sts == CSPL_MBOX_STS_PAUSED); + case CSPL_MBOX_CMD_PREPARE_RECONFIGURATION: + return (sts == CSPL_MBOX_STS_RECONFIGURING); + case CSPL_MBOX_CMD_APPLY_RECONFIGURATION: + return (sts == CSPL_MBOX_STS_PAUSED); + default: + return false; + } +} + +int cs35l45_set_csplmboxcmd(struct cs35l45_private *cs35l45, + enum cspl_mboxcmd cmd) +{ + unsigned int sts, i; + + /* Reset DSP sticky bit */ + regmap_write(cs35l45->regmap, CS35L45_IRQ2_EINT_2, + CS35L45_DSP_VIRT1_MBOX_MASK); + + /* Reset AP sticky bit */ + regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_2, + CS35L45_DSP_VIRT2_MBOX_MASK); + + /* Unmask DSP INT */ + regmap_update_bits(cs35l45->regmap, CS35L45_IRQ2_MASK_2, + CS35L45_DSP_VIRT1_MBOX_MASK, 0); + + regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, cmd); + + /* Poll for DSP ACK */ + for (i = 0; i < 5; i++) { + usleep_range(1000, 1100); + + regmap_read(cs35l45->regmap, CS35L45_IRQ1_EINT_2, &sts); + if (!(sts & CS35L45_DSP_VIRT2_MBOX_MASK)) + continue; + + regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_2, + CS35L45_DSP_VIRT2_MBOX_MASK); + + break; + } + + /* Mask DSP INT */ + regmap_update_bits(cs35l45->regmap, CS35L45_IRQ2_MASK_2, + CS35L45_DSP_VIRT1_MBOX_MASK, + CS35L45_DSP_VIRT1_MBOX_MASK); + + if (i == 5) { + dev_err(cs35l45->dev, "Timeout waiting for MBOX ACK\n"); + return -ETIMEDOUT; + } + + regmap_read(cs35l45->regmap, CS35L45_DSP_MBOX_2, &sts); + if (!cs35l45_is_csplmboxsts_correct(cmd, (enum cspl_mboxstate)sts)) { + dev_err(cs35l45->dev, "Failed to set MBOX (cmd: %u, sts: %u)\n", + cmd, sts); + return -ENOMSG; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cs35l45_set_csplmboxcmd); + +static int cs35l45_dsp_loader_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s: event = 0x%x\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (cs35l45->dsp.booted) { + dev_err(cs35l45->dev, "DSP already booted\n"); + return -EPERM; + } + + wm_adsp_early_event(w, kcontrol, event); + break; + case SND_SOC_DAPM_POST_PMU: + wm_adsp_event(w, kcontrol, event); + break; + default: + dev_err(cs35l45->dev, "Invalid event = 0x%x\n", event); + return -EINVAL; + } + + return 0; +} + +static int cs35l45_dsp_boot_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + enum cspl_mboxcmd mboxcmd = CSPL_MBOX_CMD_NONE; + unsigned int sts, i; + int ret; + + dev_dbg(cs35l45->dev, "%s: event = 0x%x\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (!cs35l45->dsp.booted) { + dev_err(cs35l45->dev, "Preload DSP before boot\n"); + return -EPERM; + } + + regmap_update_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL, + CS35L45_MEM_RDY_MASK, + CS35L45_MEM_RDY_MASK); + + regmap_write(cs35l45->regmap, CS35L45_DSP1_CCM_CORE_CONTROL, + CS35L45_CCM_PM_REMAP_MASK | + CS35L45_CCM_CORE_RESET_MASK); + + (*cs35l45_halo_start_core)(&cs35l45->dsp); + + /* Poll for DSP ACK */ + for (i = 0; i < 10; i++) { + usleep_range(1000, 1100); + + regmap_read(cs35l45->regmap, CS35L45_IRQ1_EINT_2, &sts); + if (!(sts & CS35L45_DSP_VIRT2_MBOX_MASK)) + continue; + + regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_2, + CS35L45_DSP_VIRT2_MBOX_MASK); + + break; + } + + if (i == 10) + dev_err(cs35l45->dev, "Timeout waiting for MBOX ACK\n"); + + mboxcmd = CSPL_MBOX_CMD_PAUSE; + ret = cs35l45_set_csplmboxcmd(cs35l45, mboxcmd); + if (ret < 0) + dev_err(cs35l45->dev, "MBOX failure (%d)\n", ret); + break; + case SND_SOC_DAPM_PRE_PMD: + regmap_update_bits(cs35l45->regmap, + CS35L45_DSP1_STREAM_ARB_TX1_CONFIG_0, + CS35L45_DSP1_STREAM_ARB_TX1_EN_MASK, 0); + + regmap_update_bits(cs35l45->regmap, + CS35L45_DSP1_STREAM_ARB_MSTR1_CONFIG_0, + CS35L45_DSP1_STREAM_ARB_MSTR0_EN_MASK, 0); + + wm_adsp_early_event(w, kcontrol, event); + wm_adsp_event(w, kcontrol, event); + + regmap_update_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL, + CS35L45_MEM_RDY_MASK, 0); + break; + default: + dev_err(cs35l45->dev, "Invalid event = 0x%x\n", event); + return -EINVAL; + } + + return 0; +} + +static int cs35l45_dsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + enum cspl_mboxcmd mboxcmd = CSPL_MBOX_CMD_NONE; + int ret = 0; + + dev_dbg(cs35l45->dev, "%s: event = 0x%x\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (!cs35l45->dsp.running) { + dev_err(cs35l45->dev, "DSP not running\n"); + return -EPERM; + } + + { + unsigned int val; + regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &val); + dev_dbg(cs35l45->dev, "%s: CS35L45_REFCLK_INPUT = 0x%x\n", __func__, val); + } + + flush_work(&cs35l45->dsp_pmd_work); + + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_FORCE_EN_MASK, + CS35L45_PLL_FORCE_EN_MASK); + + usleep_range(5000, 5100); + + mboxcmd = CSPL_MBOX_CMD_RESUME; + ret = cs35l45_set_csplmboxcmd(cs35l45, mboxcmd); + if (ret < 0) + dev_err(cs35l45->dev, "MBOX failure (%d)\n", ret); + break; + case SND_SOC_DAPM_PRE_PMD: + if (!cs35l45->dsp.running) { + dev_err(cs35l45->dev, "DSP not running\n"); + return -EPERM; + } + + mboxcmd = CSPL_MBOX_CMD_PAUSE; + ret = cs35l45_set_csplmboxcmd(cs35l45, mboxcmd); + if (ret < 0) + dev_err(cs35l45->dev, "MBOX failure (%d)\n", ret); + + queue_work(system_unbound_wq, &cs35l45->dsp_pmd_work); + + break; + default: + dev_err(cs35l45->dev, "Invalid event = 0x%x\n", event); + ret = -EINVAL; + } + + return ret; +} + +static int cs35l45_global_en_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + unsigned int val; + int ret = 0; + + dev_dbg(cs35l45->dev, "%s: event = 0x%x\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, + CS35L45_GLOBAL_EN_MASK); + break; + case SND_SOC_DAPM_PRE_PMD: + regmap_read(cs35l45->regmap, CS35L45_BLOCK_ENABLES, &val); + + val = (val & CS35L45_BST_EN_MASK) >> CS35L45_BST_EN_SHIFT; + if (val == CS35L45_BST_DISABLE_FET_ON) + regmap_update_bits(cs35l45->regmap, + CS35L45_BLOCK_ENABLES, + CS35L45_BST_EN_MASK, + CS35L45_BST_DISABLE_FET_OFF << + CS35L45_BST_EN_SHIFT); + + usleep_range(3000, 3100); + + regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 0); + break; + default: + dev_err(cs35l45->dev, "Invalid event = 0x%x\n", event); + ret = -EINVAL; + } + + return ret; +} + +static const char * const digital_pcm_volume_soft_ramp_text[] = { + "Off", "0.5ms", "1ms", "2ms", "4ms", "8ms", "16ms", "32ms"}; + +static SOC_ENUM_SINGLE_DECL(digital_pcm_volume_soft_ramp, + CS35L45_AMP_PCM_CONTROL, 12, + digital_pcm_volume_soft_ramp_text); + +static const char * const pcm_tx_txt[] = {"Zero", "ASP_RX1", "ASP_RX2", "VMON", + "IMON", "ERR_VOL", "VDD_BATTMON", "VDD_BSTMON", + "DSP_TX1", "DSP_TX2"}; + +static const unsigned int pcm_tx_val[] = {CS35L45_PCM_SRC_ZERO, + CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2, + CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, + CS35L45_PCM_SRC_ERR_VOL, CS35L45_PCM_SRC_VDD_BATTMON, + CS35L45_PCM_SRC_VDD_BSTMON, CS35L45_PCM_SRC_DSP_TX1, + CS35L45_PCM_SRC_DSP_TX2}; + +static const char * const pcm_rx_txt[] = {"Zero", "ASP_RX1", "ASP_RX2", "VMON", + "IMON", "ERR_VOL", "CLASSH_TGT", "VDD_BATTMON", + "VDD_BSTMON", "TEMPMON"}; + +static const unsigned int pcm_rx_val[] = {CS35L45_PCM_SRC_ZERO, + CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2, + CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, + CS35L45_PCM_SRC_ERR_VOL, CS35L45_PCM_SRC_CLASSH_TGT, + CS35L45_PCM_SRC_VDD_BATTMON, CS35L45_PCM_SRC_VDD_BSTMON, + CS35L45_PCM_SRC_TEMPMON}; + +static const char * const pcm_dac_txt[] = {"Zero", "ASP_RX1", "ASP_RX2", + "DSP_TX1", "DSP_TX2"}; + +static const unsigned int pcm_dac_val[] = {CS35L45_PCM_SRC_ZERO, + CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2, + CS35L45_PCM_SRC_DSP_TX1, CS35L45_PCM_SRC_DSP_TX2}; + +static const char * const pcm_ng_txt[] = {"Zero", "ASP_RX1", "ASP_RX2"}; + +static const unsigned int pcm_ng_val[] = {CS35L45_PCM_SRC_ZERO, + CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2}; + +static const struct soc_enum mux_enums[] = { + SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX1_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_tx_txt), pcm_tx_txt, pcm_tx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX2_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_tx_txt), pcm_tx_txt, pcm_tx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX3_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_tx_txt), pcm_tx_txt, pcm_tx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX4_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_tx_txt), pcm_tx_txt, pcm_tx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX1_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX2_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX3_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX4_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX5_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX6_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX7_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX8_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_rx_txt), pcm_rx_txt, pcm_rx_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_DACPCM1_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_dac_txt), pcm_dac_txt, pcm_dac_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_NGATE1_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_ng_txt), pcm_ng_txt, pcm_ng_val), + SOC_VALUE_ENUM_SINGLE(CS35L45_NGATE2_INPUT, 0, CS35L45_PCM_SRC_MASK, + ARRAY_SIZE(pcm_ng_txt), pcm_ng_txt, pcm_ng_val), +}; + +static const struct snd_kcontrol_new muxes[] = { + SOC_DAPM_ENUM("ASP_TX1 Source", mux_enums[ASP_TX1]), + SOC_DAPM_ENUM("ASP_TX2 Source", mux_enums[ASP_TX2]), + SOC_DAPM_ENUM("ASP_TX3 Source", mux_enums[ASP_TX3]), + SOC_DAPM_ENUM("ASP_TX4 Source", mux_enums[ASP_TX4]), +}; + +static const char *virt_text[] = { "None", "Ref"}; +static SOC_ENUM_SINGLE_DECL(virt_enum, SND_SOC_NOPM, 2, virt_text); + +static const struct snd_kcontrol_new virt_mux = + SOC_DAPM_ENUM("Virt Connect", virt_enum); + +static const struct snd_kcontrol_new amp_en_ctl = + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); + +static const struct snd_kcontrol_new amp_pwr_en_ctl = + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); + +static const struct snd_kcontrol_new bbpe_en_ctl = + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); + +static const struct snd_kcontrol_new ngate_en_ctl = + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); + +static const struct snd_kcontrol_new nfr_en_ctl = + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); + +static const struct snd_soc_dapm_widget cs35l45_dapm_widgets[] = { + SND_SOC_DAPM_SPK("DSP1 Preload", NULL), + SND_SOC_DAPM_SPK("DSP1 Enable", NULL), + + SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, + cs35l45_dsp_loader_ev, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_SUPPLY_S("DSP1 Boot", 200, SND_SOC_NOPM, 0, 0, + cs35l45_dsp_boot_ev, SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_PGA_S("DSP1 Slave", 100, SND_SOC_NOPM, 0, 0, + cs35l45_dsp_power_ev, SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_PGA_S("DSP1 Master", 200, SND_SOC_NOPM, 0, 0, + cs35l45_dsp_power_ev, SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_PGA_E("GLOBAL_EN", SND_SOC_NOPM, 0, 0, NULL, 0, + cs35l45_global_en_ev, SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_MUX("ASPTX Ref", SND_SOC_NOPM, 0, 0, &virt_mux), + + SND_SOC_DAPM_SUPPLY("VMON", CS35L45_BLOCK_ENABLES, 12, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("IMON", CS35L45_BLOCK_ENABLES, 13, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BATTMON", CS35L45_BLOCK_ENABLES, 8, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BSTMON", CS35L45_BLOCK_ENABLES, 9, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RCV_EN", CS35L45_BLOCK_ENABLES, 2, 0, NULL, 0), + + SND_SOC_DAPM_AIF_IN("ASP", NULL, 0, CS35L45_BLOCK_ENABLES2, 27, 0), + SND_SOC_DAPM_AIF_IN("ASP_RX1", NULL, 0, CS35L45_ASP_ENABLES1, 16, 0), + SND_SOC_DAPM_AIF_IN("ASP_RX2", NULL, 0, CS35L45_ASP_ENABLES1, 17, 0), + SND_SOC_DAPM_AIF_IN("NGATE_CH1", NULL, 0, CS35L45_MIXER_NGATE_CH1_CFG, + 16, 0), + SND_SOC_DAPM_AIF_IN("NGATE_CH2", NULL, 0, CS35L45_MIXER_NGATE_CH2_CFG, + 16, 0), +#if 1 // To support that J18 uses same RX/TX TDM format without independent capture dai link + SND_SOC_DAPM_AIF_OUT("ASP_TX1", NULL, 0, CS35L45_ASP_ENABLES1, 0, 0), + SND_SOC_DAPM_AIF_OUT("ASP_TX2", NULL, 0, CS35L45_ASP_ENABLES1, 1, 0), + SND_SOC_DAPM_AIF_OUT("ASP_TX3", NULL, 0, CS35L45_ASP_ENABLES1, 2, 0), + SND_SOC_DAPM_AIF_OUT("ASP_TX4", NULL, 0, CS35L45_ASP_ENABLES1, 3, 0), +#else + SND_SOC_DAPM_AIF_OUT("ASP_TX1", NULL, 0, CS35L45_ASP_ENABLES1, 0, 1), + SND_SOC_DAPM_AIF_OUT("ASP_TX2", NULL, 0, CS35L45_ASP_ENABLES1, 1, 1), + SND_SOC_DAPM_AIF_OUT("ASP_TX3", NULL, 0, CS35L45_ASP_ENABLES1, 2, 1), + SND_SOC_DAPM_AIF_OUT("ASP_TX4", NULL, 0, CS35L45_ASP_ENABLES1, 3, 1), +#endif + + SND_SOC_DAPM_MUX("ASP_TX1 Source", SND_SOC_NOPM, 0, 0, &muxes[ASP_TX1]), + SND_SOC_DAPM_MUX("ASP_TX2 Source", SND_SOC_NOPM, 0, 0, &muxes[ASP_TX2]), + SND_SOC_DAPM_MUX("ASP_TX3 Source", SND_SOC_NOPM, 0, 0, &muxes[ASP_TX3]), + SND_SOC_DAPM_MUX("ASP_TX4 Source", SND_SOC_NOPM, 0, 0, &muxes[ASP_TX4]), + + SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 0, &_en_ctl), + SND_SOC_DAPM_SWITCH("AMP PWR Enable", SND_SOC_NOPM, 0, 0, &_pwr_en_ctl), + SND_SOC_DAPM_SWITCH("BBPE Enable", CS35L45_BLOCK_ENABLES2, 13, 0, + &bbpe_en_ctl), + SND_SOC_DAPM_SWITCH("NFR Enable", CS35L45_BLOCK_ENABLES, 1, 0, + &nfr_en_ctl), + SND_SOC_DAPM_SWITCH("NGATE Enable", SND_SOC_NOPM, 0, 0, &ngate_en_ctl), + + SND_SOC_DAPM_MIXER("Exit", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_OUTPUT("SPK"), + SND_SOC_DAPM_OUTPUT("RCV"), + SND_SOC_DAPM_INPUT("AP"), +}; + +static const struct snd_soc_dapm_route cs35l45_dapm_routes[] = { + /* DSP */ + {"DSP1 Preload", NULL, "DSP1 Preloader"}, + {"DSP1 Enable", NULL, "DSP1 Boot"}, + + {"DSP1 Slave", NULL, "DSP1 Preloader"}, + {"DSP1 Slave", NULL, "DSP1 Boot"}, + {"DSP1 Slave", NULL, "VMON"}, + {"DSP1 Slave", NULL, "IMON"}, + {"DSP1 Slave", NULL, "BATTMON"}, + {"DSP1 Slave", NULL, "BSTMON"}, + + {"DSP1 Master", NULL, "DSP1 Preloader"}, + {"DSP1 Master", NULL, "DSP1 Boot"}, + {"DSP1 Master", NULL, "VMON"}, + {"DSP1 Master", NULL, "IMON"}, + {"DSP1 Master", NULL, "BATTMON"}, + {"DSP1 Master", NULL, "BSTMON"}, + + /* Feedback */ + {"ASP_TX1", NULL, "AP"}, + {"ASP_TX2", NULL, "AP"}, + {"ASP_TX3", NULL, "AP"}, + {"ASP_TX4", NULL, "AP"}, + + {"ASP_TX1 Source", "Zero", "ASP_TX1"}, + {"ASP_TX2 Source", "Zero", "ASP_TX2"}, + {"ASP_TX3 Source", "Zero", "ASP_TX3"}, + {"ASP_TX4 Source", "Zero", "ASP_TX4"}, + + {"Capture", NULL, "ASP_TX1 Source"}, + {"Capture", NULL, "ASP_TX2 Source"}, + {"Capture", NULL, "ASP_TX3 Source"}, + {"Capture", NULL, "ASP_TX4 Source"}, + + {"Capture", NULL, "VMON"}, + {"Capture", NULL, "IMON"}, + {"Capture", NULL, "BATTMON"}, + {"Capture", NULL, "BSTMON"}, + + {"ASP_TX1", NULL, "Playback"}, + {"ASP_TX2", NULL, "Playback"}, + {"ASPTX Ref", "Ref", "ASP_TX1"}, + {"ASPTX Ref", "Ref", "ASP_TX2"}, + {"Exit", NULL, "ASPTX Ref"}, + + /* Playback */ + {"Entry", NULL, "Playback"}, + + {"AMP Enable", "Switch", "Entry"}, + + {"ASP_RX1", NULL, "AMP Enable"}, + {"ASP_RX2", NULL, "AMP Enable"}, + + {"ASP", NULL, "ASP_RX1"}, + {"ASP", NULL, "ASP_RX2"}, + + {"BBPE Enable", "Switch", "AMP Enable"}, + {"NFR Enable", "Switch", "AMP Enable"}, + + {"NGATE_CH1", NULL, "AMP Enable"}, + {"NGATE_CH2", NULL, "AMP Enable"}, + + {"NGATE Enable", "Switch", "NGATE_CH1"}, + {"NGATE Enable", "Switch", "NGATE_CH2"}, + + {"Exit", NULL, "ASP"}, + {"Exit", NULL, "BBPE Enable"}, + {"Exit", NULL, "NFR Enable"}, + {"Exit", NULL, "NGATE Enable"}, + + {"RCV", NULL, "RCV_EN"}, + {"RCV", NULL, "Exit"}, + + {"AMP PWR Enable", "Switch", "Exit"}, + {"SPK", NULL, "AMP PWR Enable"}, +}; + +static const struct snd_soc_dapm_route cs35l45_asp_routes[] = { + {"GLOBAL_EN", NULL, "Entry"}, + {"Exit", NULL, "GLOBAL_EN"}, +}; + +static const struct snd_soc_dapm_route cs35l45_dsp_slave_routes[] = { + {"DSP1 Slave", NULL, "Entry"}, + {"Exit", NULL, "DSP1 Slave"}, +}; + +static const struct snd_soc_dapm_route cs35l45_dsp_master_routes[] = { + {"DSP1 Master", NULL, "Entry"}, + {"Exit", NULL, "DSP1 Master"}, +}; + +static int cs35l45_set_dapm_route_mode(struct cs35l45_private *cs35l45, + enum dapm_route_mode dapm_mode) +{ + struct snd_soc_component *component = + snd_soc_lookup_component(cs35l45->dev, NULL); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + + if (cs35l45->dapm_mode == dapm_mode) + return 0; + + switch (cs35l45->dapm_mode) { + case DAPM_MODE_ASP: + snd_soc_dapm_del_routes(dapm, cs35l45_asp_routes, + ARRAY_SIZE(cs35l45_asp_routes)); + break; + case DAPM_MODE_DSP_SLAVE: + snd_soc_dapm_del_routes(dapm, cs35l45_dsp_slave_routes, + ARRAY_SIZE(cs35l45_dsp_slave_routes)); + break; + case DAPM_MODE_DSP_MASTER: + snd_soc_dapm_del_routes(dapm, cs35l45_dsp_master_routes, + ARRAY_SIZE(cs35l45_dsp_master_routes)); + break; + } + + switch (dapm_mode) { + case DAPM_MODE_ASP: + snd_soc_dapm_add_routes(dapm, cs35l45_asp_routes, + ARRAY_SIZE(cs35l45_asp_routes)); + break; + case DAPM_MODE_DSP_SLAVE: + snd_soc_dapm_add_routes(dapm, cs35l45_dsp_slave_routes, + ARRAY_SIZE(cs35l45_dsp_slave_routes)); + break; + case DAPM_MODE_DSP_MASTER: + snd_soc_dapm_add_routes(dapm, cs35l45_dsp_master_routes, + ARRAY_SIZE(cs35l45_dsp_master_routes)); + break; + default: + dev_err(cs35l45->dev, "Invalid DAPM route mode (%d)\n", + dapm_mode); + return -EINVAL; + } + + cs35l45->dapm_mode = dapm_mode; + + return 0; +} + +static const char * const gain_texts[] = {"10dB", "13dB", "16dB", "19dB"}; +static const unsigned int gain_values[] = {0x00, 0x01, 0x02, 0x03}; +static SOC_VALUE_ENUM_SINGLE_DECL(gain_enum, CS35L45_AMP_GAIN, + CS35L45_AMP_GAIN_PCM_SHIFT, + CS35L45_AMP_GAIN_PCM_MASK >> CS35L45_AMP_GAIN_PCM_SHIFT, + gain_texts, gain_values); + +static const char * const amplifier_mode_texts[] = {"SPK", "RCV"}; +static SOC_ENUM_SINGLE_DECL(amplifier_mode_enum, SND_SOC_NOPM, 0, + amplifier_mode_texts); + +static const char * const hibernate_mode_texts[] = {"Off", "On"}; +static SOC_ENUM_SINGLE_DECL(hibernate_mode_enum, SND_SOC_NOPM, 0, + hibernate_mode_texts); + +static const char * const channel_swap_texts[] = {"Off", "On"}; +static SOC_ENUM_SINGLE_DECL(channel_swap_enum, SND_SOC_NOPM, 0, + channel_swap_texts); + +static const DECLARE_TLV_DB_RANGE(dig_pcm_vol_tlv, 0, 0, + TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), + 1, 913, TLV_DB_SCALE_ITEM(-10200, 25, 0)); + +static int cs35l45_activate_ctl(struct cs35l45_private *cs35l45, + const char *ctl_name, bool active) +{ + struct snd_soc_component *component = + snd_soc_lookup_component(cs35l45->dev, NULL); + struct snd_card *card = component->card->snd_card; + struct snd_kcontrol *kcontrol; + struct snd_kcontrol_volatile *vd; + unsigned int index_offset; + char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; + + if (component->name_prefix) + snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s", + component->name_prefix, ctl_name); + else + snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s", ctl_name); + + kcontrol = snd_soc_card_get_kcontrol(component->card, name); + if (!kcontrol) { + dev_err(cs35l45->dev, "Can't find kcontrol %s\n", name); + return -EINVAL; + } + + index_offset = snd_ctl_get_ioff(kcontrol, &kcontrol->id); + vd = &kcontrol->vd[index_offset]; + if (active) + vd->access |= SNDRV_CTL_ELEM_ACCESS_WRITE; + else + vd->access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; + + snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_INFO, &kcontrol->id); + + return 0; +} + +static int cs35l45_amplifier_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = cs35l45->amplifier_mode; + + return 0; +} + +static int cs35l45_amplifier_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + unsigned int val; + + if (ucontrol->value.integer.value[0] == cs35l45->amplifier_mode) + return 0; + + regmap_read(cs35l45->regmap, CS35L45_IRQ1_STS_1, &val); + if (val & CS35L45_MSM_GLOBAL_EN_ASSERT_MASK) { + dev_err(cs35l45->dev, "Only switch mode while powered down\n"); + return -EINVAL; + } + + cs35l45->amplifier_mode = ucontrol->value.integer.value[0]; + + if (cs35l45->amplifier_mode == AMP_MODE_SPK) { + snd_soc_component_force_enable_pin(component, "SPK"); + snd_soc_component_disable_pin(component, "RCV"); + + regmap_update_bits(cs35l45->regmap, CS35L45_BLOCK_ENABLES, + CS35L45_BST_EN_MASK, + CS35L45_BST_ENABLE << CS35L45_BST_EN_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_HVLV_CONFIG, + CS35L45_HVLV_MODE_MASK, + CS35L45_HVLV_OPERATION << + CS35L45_HVLV_MODE_SHIFT); + } else /* AMP_MODE_RCV */ { + snd_soc_component_force_enable_pin(component, "RCV"); + snd_soc_component_disable_pin(component, "SPK"); + + regmap_update_bits(cs35l45->regmap, CS35L45_BLOCK_ENABLES, + CS35L45_BST_EN_MASK, + CS35L45_BST_DISABLE_FET_OFF << + CS35L45_BST_EN_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_HVLV_CONFIG, + CS35L45_HVLV_MODE_MASK, + CS35L45_FORCE_LV_OPERATION << + CS35L45_HVLV_MODE_SHIFT); + + regmap_update_bits(cs35l45->regmap, + CS35L45_BLOCK_ENABLES2, + CS35L45_AMP_DRE_EN_MASK, 0); + + regmap_update_bits(cs35l45->regmap, CS35L45_AMP_GAIN, + CS35L45_AMP_GAIN_PCM_MASK, + CS35L45_AMP_GAIN_PCM_13DBV << + CS35L45_AMP_GAIN_PCM_SHIFT); + } + + snd_soc_dapm_sync(dapm); + + return 0; +} + +static int cs35l45_hibernate_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = cs35l45->hibernate_mode; + + return 0; +} + +static int cs35l45_hibernate_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + int ret; + + ret = cs35l45_hibernate(cs35l45, ucontrol->value.integer.value[0]); + if (ret < 0) + dev_err(cs35l45->dev, "Set hibernate mode failed (%d)\n", ret); + + return 0; +} + +static int cs35l45_dsp_boot_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s\n", __func__); + + ucontrol->value.integer.value[0] = (cs35l45->dsp1_enable_pin > 0) ? 1 : 0; + + return 0; +} + +static int cs35l45_dsp_boot_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + + dev_dbg(cs35l45->dev, "%s\n", __func__); + if (!cs35l45->dsp.booted) { + dev_err(cs35l45->dev, "Preload DSP before boot\n"); + return -EPERM; + } + + if (ucontrol->value.integer.value[0]) { + snd_soc_component_force_enable_pin(component, "DSP1 Enable"); + cs35l45->dsp1_enable_pin = 1; + cs35l45_set_dapm_route_mode(cs35l45, DAPM_MODE_DSP_MASTER); + + snd_soc_dapm_sync(dapm); + + #if defined(MDSYNC_CS) + regmap_update_bits(cs35l45->regmap, CS35L45_BLOCK_ENABLES2, + CS35L45_SYNC_EN_MASK, CS35L45_SYNC_EN_MASK); + + regmap_update_bits(cs35l45->regmap, CS35L45_SYNC_TX_RX_ENABLES, + CS35L45_SYNC_SW_EN_MASK, + CS35L45_SYNC_SW_EN_MASK); + #endif + } else { + snd_soc_component_disable_pin(component, "DSP1 Enable"); + cs35l45->dsp1_enable_pin = 0; + cs35l45_set_dapm_route_mode(cs35l45, DAPM_MODE_ASP); + + snd_soc_dapm_sync(dapm); + + regmap_update_bits(cs35l45->regmap, CS35L45_BLOCK_ENABLES2, + CS35L45_SYNC_EN_MASK, 0); + + regmap_update_bits(cs35l45->regmap, CS35L45_SYNC_TX_RX_ENABLES, + CS35L45_SYNC_SW_EN_MASK, 0); + } + + return 0; +} + +static int cs35l45_amp_active_status_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + unsigned int global_en, force_pll_en; + + regmap_read(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, &global_en); + regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &force_pll_en); + global_en &= CS35L45_GLOBAL_EN_MASK; + force_pll_en = (force_pll_en & CS35L45_PLL_FORCE_EN_MASK) ? 1 : 0; + + dev_dbg(cs35l45->dev, "%s: global_en=%u, force_pll_en=%u\n", __func__, global_en, force_pll_en); + + ucontrol->value.integer.value[0] = (global_en | force_pll_en); + + return 0; +} + +static int cs35l45_amp_active_status_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +static int cs35l45_ldpm_config_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + unsigned int ldpm_config; + + regmap_read(cs35l45->regmap, CS35L45_LDPM_CONFIG, &ldpm_config); + dev_dbg(cs35l45->dev, "%s: LDPM_CONFIG = 0x%x\n", __func__, ldpm_config); + ucontrol->value.integer.value[0] = ldpm_config; + + return 0; +} + +static int cs35l45_ldpm_config_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + unsigned int ldpm_config; + + ldpm_config = ucontrol->value.integer.value[0]; + dev_dbg(cs35l45->dev, "%s: LDPM_CONFIG = 0x%x\n", __func__, ldpm_config); + regmap_write(cs35l45->regmap, CS35L45_LDPM_CONFIG, ldpm_config); + + return 0; +} + +static int cs35l45_global_err_rls_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s\n", __func__); + + ucontrol->value.integer.value[0] = cs35l45->global_err_rls; + + return 0; +} + +static int cs35l45_global_err_rls_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +static int cs35l45_sync_num_devices_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s: sync_num_devices = %u\n", __func__, cs35l45->sync_num_devices); + + ucontrol->value.integer.value[0] = cs35l45->sync_num_devices; + + return 0; +} + +static int cs35l45_sync_num_devices_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + __be32 buf; + int ret; + + dev_dbg(cs35l45->dev, "%s: sync_num_devices = %lu\n", __func__, ucontrol->value.integer.value[0]); + + if (!cs35l45->dsp.running) { + dev_err(cs35l45->dev, "DSP not running\n"); + return -EPERM; + } + + cs35l45->sync_num_devices = ucontrol->value.integer.value[0]; + + buf = cpu_to_be32(cs35l45->sync_num_devices); + ret = wm_adsp_write_ctl(&cs35l45->dsp, "NEW_NUM_DEVICES", WMFW_ADSP2_XM, + CS35L45_ALGID_MDSYNC, &buf, sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, "Control write error (%d)\n", ret); + return ret; + } + + return 0; +} + +static int cs35l45_sync_id_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s: sync_id = %u\n", __func__, cs35l45->sync_id); + + ucontrol->value.integer.value[0] = cs35l45->sync_id; + + return 0; +} + +static int cs35l45_sync_id_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + __be32 buf; + int ret; + + dev_dbg(cs35l45->dev, "%s: sync_id = %lu\n", __func__, ucontrol->value.integer.value[0]); + + if (!cs35l45->dsp.running) { + dev_err(cs35l45->dev, "DSP not running\n"); + return -EPERM; + } + + cs35l45->sync_id = ucontrol->value.integer.value[0]; + + buf = cpu_to_be32(cs35l45->sync_id); + ret = wm_adsp_write_ctl(&cs35l45->dsp, "NEW_ID", WMFW_ADSP2_XM, + CS35L45_ALGID_MDSYNC, &buf, sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, "Control write error (%d)\n", ret); + return ret; + } + + return 0; +} + +static int cs35l45_dsp_prepare_reconfig_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = 0; + + return 0; +} + +static int cs35l45_dsp_prepare_reconfig_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l45->dev, "%s: value = %lu\n", __func__, ucontrol->value.integer.value[0]); + if (!cs35l45->dsp.running) { + dev_err(cs35l45->dev, "DSP not running\n"); + return -EPERM; + } + + if (!ucontrol->value.integer.value[0]) + return 0; + + { + unsigned int val; + regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &val); + dev_dbg(cs35l45->dev, "%s: CS35L45_REFCLK_INPUT = 0x%x\n", __func__, val); + } + + regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, + CSPL_MBOX_CMD_PREPARE_RECONFIGURATION); + + usleep_range(5000, 5100); + + return 0; +} + +static int cs35l45_dsp_apply_reconfig_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = 0; + + return 0; +} + +static int cs35l45_dsp_apply_reconfig_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + static const struct reg_sequence cs35l45_sync_pwr_en_patch[] = { + {0x00000040, 0x00000055}, + {0x00000040, 0x000000AA}, + {0x00000044, 0x00000055}, + {0x00000044, 0x000000AA}, + {0x00002114, 0x00040000}, + {0x0000225C, 0x0002000A}, + {0x00000040, 0x00000000}, + {0x00000044, 0x00000000}, + }; + static const struct reg_sequence cs35l45_sync_pwr_dis_patch[] = { + {0x00000040, 0x00000055}, + {0x00000040, 0x000000AA}, + {0x00000044, 0x00000055}, + {0x00000044, 0x000000AA}, + {0x00002114, 0x00000000}, + {0x0000225C, 0x00000000}, + {0x00000040, 0x00000000}, + {0x00000044, 0x00000000}, + }; + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + unsigned int is_master, num_devices, mask; + __be32 buf; + int ret = 0; + + dev_dbg(cs35l45->dev, "%s: value = %lu\n", __func__, ucontrol->value.integer.value[0]); + if (!cs35l45->dsp.running) { + dev_err(cs35l45->dev, "DSP not running\n"); + return -EPERM; + } + + if (!ucontrol->value.integer.value[0]) + return 0; + + ret = wm_adsp_read_ctl(&cs35l45->dsp, "MASTER", WMFW_ADSP2_XM, + CS35L45_ALGID_MDSYNC, &buf, sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, "Control read error (%d)\n", ret); + return ret; + } + + is_master = be32_to_cpu(buf); + + ret = wm_adsp_read_ctl(&cs35l45->dsp, "NUM_DEVICES", WMFW_ADSP2_XM, + CS35L45_ALGID_MDSYNC, &buf, sizeof(__be32)); + if (ret < 0) { + dev_err(cs35l45->dev, "Control read error (%d)\n", ret); + return ret; + } + + num_devices = be32_to_cpu(buf); + + if (is_master && (num_devices > 1)) + mask = CS35L45_SYNC_PWR_TX_EN_MASK | + CS35L45_SYNC_PWR_RX_EN_MASK; + else if ((num_devices > 1)) + mask = CS35L45_SYNC_PWR_RX_EN_MASK; + else + mask = 0; + + regmap_update_bits(cs35l45->regmap, CS35L45_SYNC_TX_RX_ENABLES, + CS35L45_SYNC_PWR_TX_EN_MASK | + CS35L45_SYNC_PWR_RX_EN_MASK, mask); + + if (mask) + regmap_register_patch(cs35l45->regmap, + cs35l45_sync_pwr_en_patch, + ARRAY_SIZE(cs35l45_sync_pwr_en_patch)); + else + regmap_register_patch(cs35l45->regmap, + cs35l45_sync_pwr_dis_patch, + ARRAY_SIZE(cs35l45_sync_pwr_dis_patch)); + + if (is_master) + cs35l45_set_dapm_route_mode(cs35l45, DAPM_MODE_DSP_MASTER); + else + cs35l45_set_dapm_route_mode(cs35l45, DAPM_MODE_DSP_SLAVE); + + regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, + CSPL_MBOX_CMD_APPLY_RECONFIGURATION); + + usleep_range(5000, 5100); + + return 0; +} + +static int cs35l45_channel_swap_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + int swapped = 0; + int val; + + if (cs35l45->dsp.booted) { + wm_adsp_read_ctl(&cs35l45->dsp, "CH_BAL", WMFW_ADSP2_XM, CS35L45_ALGID, (void *)&val, sizeof(__be32)); + + dev_dbg(cs35l45->dev, "%s: CH_BAL = 0x%08x\n", __func__, be32_to_cpu(val)); + swapped = (0x400000==be32_to_cpu(val)) ? 1 : 0; + } + + ucontrol->value.integer.value[0] = swapped; + + return 0; +} + +static int cs35l45_channel_swap_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + int val; + + if (cs35l45->dsp.booted) { + if (ucontrol->value.integer.value[0]) + val = 0x400000; + else + val = 0; + + val = cpu_to_be32(val); + wm_adsp_write_ctl(&cs35l45->dsp, "CH_BAL", WMFW_ADSP2_XM, CS35L45_ALGID, (void *)&val, sizeof(__be32)); + } + + return 0; +} + +static const struct snd_kcontrol_new cs35l45_aud_controls[] = { + WM_ADSP_FW_CONTROL("DSP1", 0), + WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), + + SOC_ENUM("Digital PCM Volume Soft Ramp", digital_pcm_volume_soft_ramp), + + SOC_SINGLE("AMP Mute", CS35L45_AMP_OUTPUT_MUTE, 0, 1, 0), + #if defined(MDSYNC_CS) + SOC_SINGLE("SYNC Enable Switch", CS35L45_BLOCK_ENABLES2, 8, 1, 0), + #endif + SOC_SINGLE_EXT("DSP1 Boot Switch", SND_SOC_NOPM, 1, 1, 0, + cs35l45_dsp_boot_get, cs35l45_dsp_boot_put), + SOC_SINGLE_EXT("AMP Active Status", SND_SOC_NOPM, 0, 1, 0, + cs35l45_amp_active_status_get, cs35l45_amp_active_status_put), + SOC_SINGLE_EXT("LDPM Config", SND_SOC_NOPM, 0, 0x1ffff, 0, + cs35l45_ldpm_config_get, cs35l45_ldpm_config_put), + SOC_SINGLE_EXT("AMP Global Error Release", SND_SOC_NOPM, 0, 0x7fffffff, 0, + cs35l45_global_err_rls_get, cs35l45_global_err_rls_put), + SOC_SINGLE_EXT("DSP1 SYNC NUM DEVICES", SND_SOC_NOPM, 1, 8, 0, + cs35l45_sync_num_devices_get, + cs35l45_sync_num_devices_put), + SOC_SINGLE_EXT("DSP1 SYNC ID", SND_SOC_NOPM, 1, 7, 0, + cs35l45_sync_id_get, cs35l45_sync_id_put), + SOC_SINGLE_EXT("DSP1 Prepare Reconfiguration", SND_SOC_NOPM, 1, 1, 0, + cs35l45_dsp_prepare_reconfig_get, + cs35l45_dsp_prepare_reconfig_put), + SOC_SINGLE_EXT("DSP1 Apply Reconfiguration", SND_SOC_NOPM, 1, 1, 0, + cs35l45_dsp_apply_reconfig_get, + cs35l45_dsp_apply_reconfig_put), + SOC_SINGLE_EXT("Fast Use Case Switch Enable", SND_SOC_NOPM, 0, 1, 0, + cs35l45_fast_switch_en_get, cs35l45_fast_switch_en_put), + SOC_ENUM_EXT("Channel Swap", channel_swap_enum, + cs35l45_channel_swap_get, cs35l45_channel_swap_put), + SOC_SINGLE_RANGE("ASPTX1 Slot Position", CS35L45_ASP_FRAME_CONTROL1, 0, + 0, 63, 0), + SOC_SINGLE_RANGE("ASPTX2 Slot Position", CS35L45_ASP_FRAME_CONTROL1, 8, + 0, 63, 0), + SOC_SINGLE_RANGE("ASPTX3 Slot Position", CS35L45_ASP_FRAME_CONTROL1, 16, + 0, 63, 0), + SOC_SINGLE_RANGE("ASPTX4 Slot Position", CS35L45_ASP_FRAME_CONTROL1, 24, + 0, 63, 0), + SOC_SINGLE_RANGE("ASPRX1 Slot Position", CS35L45_ASP_FRAME_CONTROL5, 0, + 0, 63, 0), + SOC_SINGLE_RANGE("ASPRX2 Slot Position", CS35L45_ASP_FRAME_CONTROL5, 8, + 0, 63, 0), + + SOC_ENUM("DSP_RX1 Source", mux_enums[DSP_RX1]), + SOC_ENUM("DSP_RX2 Source", mux_enums[DSP_RX2]), + SOC_ENUM("DSP_RX3 Source", mux_enums[DSP_RX3]), + SOC_ENUM("DSP_RX4 Source", mux_enums[DSP_RX4]), + SOC_ENUM("DSP_RX5 Source", mux_enums[DSP_RX5]), + SOC_ENUM("DSP_RX6 Source", mux_enums[DSP_RX6]), + SOC_ENUM("DSP_RX7 Source", mux_enums[DSP_RX7]), + SOC_ENUM("DSP_RX8 Source", mux_enums[DSP_RX8]), + SOC_ENUM("DACPCM Source", mux_enums[DACPCM]), + SOC_ENUM("NGATE1 Source", mux_enums[NGATE1]), + SOC_ENUM("NGATE2 Source", mux_enums[NGATE2]), + SOC_ENUM("AMP PCM Gain", gain_enum), + + SOC_ENUM_EXT("Amplifier Mode", amplifier_mode_enum, + cs35l45_amplifier_mode_get, cs35l45_amplifier_mode_put), + SOC_ENUM_EXT("Hibernate Mode", hibernate_mode_enum, + cs35l45_hibernate_mode_get, cs35l45_hibernate_mode_put), + + { + .name = "Digital PCM Volume", + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | + SNDRV_CTL_ELEM_ACCESS_READWRITE, + .tlv.p = dig_pcm_vol_tlv, + .info = snd_soc_info_volsw_sx, + .get = snd_soc_get_volsw_sx, + .put = snd_soc_put_volsw_sx, + .private_value = (unsigned long)&(struct soc_mixer_control) + { + .reg = CS35L45_AMP_PCM_CONTROL, + .rreg = CS35L45_AMP_PCM_CONTROL, + .shift = 0, .rshift = 0, + .max = 0x391, .min = CS35L45_AMP_VOL_PCM_MUTE + } + }, +}; + +static int cs35l45_component_set_sysclk(struct snd_soc_component *component, int clk_id, int source, unsigned int freq, int dir); + +static int cs35l45_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(codec_dai->component); + unsigned int asp_fmt, fsync_inv, bclk_inv, master_mode; + + dev_dbg(cs35l45->dev, "%s\n", __func__); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + master_mode = 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + master_mode = 0; + break; + default: + dev_warn(cs35l45->dev, "Mixed master mode unsupported (%d)\n", + fmt & SND_SOC_DAIFMT_MASTER_MASK); + return -EINVAL; + } + + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, + CS35L45_ASP_BCLK_MSTR_MASK, + master_mode << CS35L45_ASP_BCLK_MSTR_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, + CS35L45_ASP_FSYNC_MSTR_MASK, + master_mode << CS35L45_ASP_FSYNC_MSTR_SHIFT); + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + asp_fmt = 0; + break; + case SND_SOC_DAIFMT_I2S: + asp_fmt = 2; + break; + default: + dev_warn(cs35l45->dev, "Unsupported DAI format (%d)\n", + fmt & SND_SOC_DAIFMT_FORMAT_MASK); + return -EINVAL; + } + + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, + CS35L45_ASP_FMT_MASK, + asp_fmt << CS35L45_ASP_FMT_SHIFT); + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_IF: + fsync_inv = 1; + bclk_inv = 0; + break; + case SND_SOC_DAIFMT_IB_NF: + fsync_inv = 0; + bclk_inv = 1; + break; + case SND_SOC_DAIFMT_IB_IF: + fsync_inv = 1; + bclk_inv = 1; + break; + case SND_SOC_DAIFMT_NB_NF: + fsync_inv = 0; + bclk_inv = 0; + break; + default: + dev_warn(cs35l45->dev, "Invalid clock polarity (%d)\n", + fmt & SND_SOC_DAIFMT_INV_MASK); + return -EINVAL; + } + + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, + CS35L45_ASP_FSYNC_INV_MASK, + fsync_inv << CS35L45_ASP_FSYNC_INV_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, + CS35L45_ASP_BCLK_INV_MASK, + bclk_inv << CS35L45_ASP_BCLK_INV_SHIFT); + + return 0; +} + +static int cs35l45_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(dai->component); + unsigned int asp_width, asp_wl, global_fs; + unsigned int hpf_override = CS35l45_HPF_DEFAULT; + static const struct reg_sequence cs35l45_unlock[] = { + {0x00000040, 0x00000055}, + {0x00000040, 0x000000AA}, + {0x00000044, 0x00000055}, + {0x00000044, 0x000000AA}, + }; + static const struct reg_sequence cs35l45_lock[] = { + {0x00000040, 0x00000000}, + {0x00000044, 0x00000000}, + }; + + switch (params_rate(params)) { + case 8000: + global_fs = CS35L45_8_KHZ; + break; + case 16000: + global_fs = CS35L45_16_KHZ; + break; + case 44100: + hpf_override = CS35L45_HPF_44P1; + global_fs = CS35L45_44P100_KHZ; + break; + case 48000: + global_fs = CS35L45_48P0_KHZ; + break; + case 88200: + hpf_override = CS35L45_HPF_88P2; + global_fs = CS35L45_88P200_KHZ; + break; + case 96000: + global_fs = CS35L45_96P0_KHZ; + break; + default: + dev_warn(cs35l45->dev, "Unsupported params rate (%d)\n", + params_rate(params)); + return -EINVAL; + } + + regmap_update_bits(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE, + CS35L45_GLOBAL_FS_MASK, + global_fs << CS35L45_GLOBAL_FS_SHIFT); + + regmap_register_patch(cs35l45->regmap, cs35l45_unlock, + ARRAY_SIZE(cs35l45_unlock)); + + regmap_write(cs35l45->regmap, CS35L45_AMP_PCM_HPF_TST, hpf_override); + + regmap_register_patch(cs35l45->regmap, cs35l45_lock, + ARRAY_SIZE(cs35l45_lock)); + + asp_wl = params_width(params); + if (asp_wl > CS35L45_ASP_WL_MAX) + asp_wl = CS35L45_ASP_WL_MAX; + else if (asp_wl < CS35L45_ASP_WL_MIN) + asp_wl = CS35L45_ASP_WL_MIN; + + asp_width = cs35l45->pdata.use_tdm_slots ? + cs35l45->slot_width : params_physical_width(params); + + dev_dbg(cs35l45->dev, "%s: fs=%d, asp_wl=%d, asp_width=%d\n", __func__, params_rate(params), asp_wl, asp_width); + + // TDM + cs35l45_component_set_sysclk(dai->component, 0, 0, 8 * params_rate(params) * asp_width, 0); + // I2S + //cs35l45_component_set_sysclk(dai->component, 0, 0, 2 * params_rate(params) * asp_width, 0); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, + CS35L45_ASP_WIDTH_RX_MASK, + asp_width << CS35L45_ASP_WIDTH_RX_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL5, + CS35L45_ASP_WL_MASK, + asp_wl << CS35L45_ASP_WL_SHIFT); + /* To support that J18 uses same RX/TX TDM format without independent capture dai link */ + //} else { + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2, + CS35L45_ASP_WIDTH_TX_MASK, + asp_width << CS35L45_ASP_WIDTH_TX_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL1, + CS35L45_ASP_WL_MASK, + asp_wl << CS35L45_ASP_WL_SHIFT); + } + + return 0; +} + +static int cs35l45_dai_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, + int slots, int slot_width) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(dai->component); + + dev_dbg(cs35l45->dev, "%s\n", __func__); + + cs35l45->slot_width = slot_width; + + return 0; +} + +static int cs35l45_dai_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(dai->component); + + dev_dbg(cs35l45->dev, "%s\n", __func__); + + return cs35l45_set_sysclk(cs35l45, clk_id, freq); +} + +static int cs35l45_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(dai->component); + + dev_dbg(cs35l45->dev, "%s\n", __func__); + + // TDM + cs35l45_dai_set_fmt(dai, SND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_DSP_A); + // I2S + //cs35l45_dai_set_fmt(dai, SND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_I2S); + + + if (cs35l45->hibernate_mode == HIBER_MODE_EN) { + dev_err(cs35l45->dev, + "Amp is hibernating; please wake up first\n"); + return -EPERM; + } + + return 0; +} + +static int cs35l45_dai_digital_mute(struct snd_soc_dai *dai, int mute) +{ + struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component); + unsigned int dv; + + regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_CONTROL, &dv); + dv &= GENMASK(14, 12); + dv >>= 12; + dev_dbg(cs35l45->dev, "%s: mute = %d, ramp=%u, previous dig_vol=0x%x\n", __func__, mute, dv, cs35l45->dig_vol); + + if (dv) { + if (mute) { + regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_CONTROL, &cs35l45->dig_vol); + cs35l45->dig_vol &= GENMASK(10, 0); + regmap_update_bits(cs35l45->regmap, CS35L45_AMP_PCM_CONTROL, + GENMASK(10, 0), + CS35L45_AMP_VOL_PCM_MUTE-1); + //msleep(34); + msleep(51); + } else { + regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_CONTROL, &dv); + dv &= GENMASK(10, 0); + if (CS35L45_AMP_VOL_PCM_MUTE-1!=dv) + cs35l45->dig_vol = dv; + regmap_update_bits(cs35l45->regmap, CS35L45_AMP_PCM_CONTROL, + GENMASK(10, 0), + cs35l45->dig_vol); + } + } else { + regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_CONTROL, &dv); + dv &= GENMASK(10, 0); + dev_dbg(cs35l45->dev, "%s: dv = 0x%x\n", __func__, dv); + if (CS35L45_AMP_VOL_PCM_MUTE-1==dv) + regmap_update_bits(cs35l45->regmap, CS35L45_AMP_PCM_CONTROL, + GENMASK(10, 0), + cs35l45->dig_vol); + } + + dev_dbg(cs35l45->dev, "%s: mute = %d done\n", __func__, mute); + + return 0; +} + +static const struct snd_soc_dai_ops cs35l45_dai_ops = { + .startup = cs35l45_dai_startup, + .set_fmt = cs35l45_dai_set_fmt, + .hw_params = cs35l45_dai_hw_params, + .set_tdm_slot = cs35l45_dai_set_tdm_slot, + .set_sysclk = cs35l45_dai_set_sysclk, + .digital_mute = cs35l45_dai_digital_mute, +}; + +#define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_3LE| \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +#define CS35L45_RATES (SNDRV_PCM_RATE_8000 | \ + SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_88200 | \ + SNDRV_PCM_RATE_96000) + +static struct snd_soc_dai_driver cs35l45_dai = { + .name = "cs35l45", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 8, + .rates = CS35L45_RATES, + .formats = CS35L45_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 8, + .rates = CS35L45_RATES, + .formats = CS35L45_FORMATS, + }, + .ops = &cs35l45_dai_ops, +}; + +static int cs35l45_component_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, + unsigned int freq, int dir) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + return cs35l45_set_sysclk(cs35l45, clk_id, freq); +} + +static char fast_ctl[] = "Fast Use Case Delta File"; + +static int cs35l45_component_probe(struct snd_soc_component *component) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + int ret; + char widget[32]; + + dev_dbg(cs35l45->dev, "%s: name_prefix=%s\n", __func__, component->name_prefix); + cs35l45->dapm_mode = DAPM_MODE_ASP; + + snd_soc_dapm_add_routes(dapm, cs35l45_asp_routes, + ARRAY_SIZE(cs35l45_asp_routes)); + + snd_soc_component_disable_pin(component, "RCV"); + snd_soc_component_disable_pin(component, "DSP1 Enable"); + cs35l45->dsp1_enable_pin = 0; + if (component->name_prefix) { + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "Capture"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "Playback"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "DSP1 Slave"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "DSP1 Master"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "GLOBAL_EN"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASPTX Ref"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "VMON"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "IMON"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "BATTMON"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "BSTMON"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "RCV_EN"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_RX1"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_RX2"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX1"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX2"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX3"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX4"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX1 Source"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX2 Source"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX3 Source"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "ASP_TX4 Source"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "AMP Enable"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "AMP PWR Enable"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "NGATE_CH1"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "NGATE_CH2"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "BBPE Enable"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "NFR Enable"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "NGATE Enable"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "Exit"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "Entry"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "SPK"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "RCV"); + snd_soc_dapm_ignore_suspend(dapm, widget); + snprintf(widget, sizeof(widget), "%s %s", component->name_prefix, "AP"); + snd_soc_dapm_ignore_suspend(dapm, widget); + } else { + snd_soc_dapm_ignore_suspend(dapm, "Capture"); + snd_soc_dapm_ignore_suspend(dapm, "Playback"); + snd_soc_dapm_ignore_suspend(dapm, "DSP1 Slave"); + snd_soc_dapm_ignore_suspend(dapm, "DSP1 Master"); + snd_soc_dapm_ignore_suspend(dapm, "GLOBAL_EN"); + snd_soc_dapm_ignore_suspend(dapm, "ASPTX Ref"); + snd_soc_dapm_ignore_suspend(dapm, "VMON"); + snd_soc_dapm_ignore_suspend(dapm, "IMON"); + snd_soc_dapm_ignore_suspend(dapm, "BATTMON"); + snd_soc_dapm_ignore_suspend(dapm, "BSTMON"); + snd_soc_dapm_ignore_suspend(dapm, "RCV_EN"); + snd_soc_dapm_ignore_suspend(dapm, "ASP"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_RX1"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_RX2"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX1"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX2"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX3"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX4"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX1 Source"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX2 Source"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX3 Source"); + snd_soc_dapm_ignore_suspend(dapm, "ASP_TX4 Source"); + snd_soc_dapm_ignore_suspend(dapm, "AMP Enable"); + snd_soc_dapm_ignore_suspend(dapm, "AMP PWR Enable"); + snd_soc_dapm_ignore_suspend(dapm, "NGATE_CH1"); + snd_soc_dapm_ignore_suspend(dapm, "NGATE_CH2"); + snd_soc_dapm_ignore_suspend(dapm, "BBPE Enable"); + snd_soc_dapm_ignore_suspend(dapm, "NFR Enable"); + snd_soc_dapm_ignore_suspend(dapm, "NGATE Enable"); + snd_soc_dapm_ignore_suspend(dapm, "Exit"); + snd_soc_dapm_ignore_suspend(dapm, "Entry"); + snd_soc_dapm_ignore_suspend(dapm, "SPK"); + snd_soc_dapm_ignore_suspend(dapm, "RCV"); + snd_soc_dapm_ignore_suspend(dapm, "AP"); + } + + snd_soc_dapm_sync(dapm); + + component->regmap = cs35l45->regmap; + + wm_adsp2_component_probe(&cs35l45->dsp, component); + + /* Add run-time mixer control for fast use case switch */ + cs35l45->fast_ctl.name = fast_ctl; + cs35l45->fast_ctl.iface = SNDRV_CTL_ELEM_IFACE_MIXER; + cs35l45->fast_ctl.info = snd_soc_info_enum_double; + cs35l45->fast_ctl.get = cs35l45_fast_switch_file_get; + cs35l45->fast_ctl.put = cs35l45_fast_switch_file_put; + cs35l45->fast_ctl.private_value = + (unsigned long)&cs35l45->fast_switch_enum; + ret = snd_soc_add_component_controls(component, &cs35l45->fast_ctl, 1); + if (ret < 0) + dev_err(cs35l45->dev, + "snd_soc_add_component_controls failed (%d)\n", ret); + return ret; +} + +static void cs35l45_component_remove(struct snd_soc_component *component) +{ + struct cs35l45_private *cs35l45 = + snd_soc_component_get_drvdata(component); + + wm_adsp2_component_remove(&cs35l45->dsp, component); +} + +static const struct snd_soc_component_driver cs35l45_component = { + .probe = cs35l45_component_probe, + .remove = cs35l45_component_remove, + .set_sysclk = cs35l45_component_set_sysclk, + + .dapm_widgets = cs35l45_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs35l45_dapm_widgets), + + .dapm_routes = cs35l45_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(cs35l45_dapm_routes), + + .controls = cs35l45_aud_controls, + .num_controls = ARRAY_SIZE(cs35l45_aud_controls), +}; + +static int cs35l45_get_clk_config(int freq) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs35l45_pll_sysclk); i++) { + if (cs35l45_pll_sysclk[i].freq == freq) + return cs35l45_pll_sysclk[i].clk_cfg; + } + + return -EINVAL; +} + +static int cs35l45_set_sysclk(struct cs35l45_private *cs35l45, int clk_id, + unsigned int freq) +{ + unsigned int val; + int extclk_cfg, clksrc; + + dev_dbg(cs35l45->dev, "%s: clk_id = %d, freq = %u\n", __func__, clk_id, freq); + + switch (clk_id) { + case 0: + clksrc = CS35L45_PLL_REFCLK_SEL_BCLK; + break; + default: + dev_err(cs35l45->dev, "Invalid CLK Config\n"); + return -EINVAL; + } + + extclk_cfg = cs35l45_get_clk_config(freq); + if (extclk_cfg < 0) { + dev_err(cs35l45->dev, "Invalid CLK Config: %d, freq: %u\n", + extclk_cfg, freq); + return -EINVAL; + } + + regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &val); + val = (val & CS35L45_PLL_REFCLK_FREQ_MASK) >> + CS35L45_PLL_REFCLK_FREQ_SHIFT; + + if (val == extclk_cfg) { + dev_dbg(cs35l45->dev, "%s: clk_id = %d, freq = %u, ignore duplicate PLL setting.\n", __func__, clk_id, freq); + return 0; + } + + dev_dbg(cs35l45->dev, "%s: clk_id = %d, freq = %u, update PLL setting!!!\n", __func__, clk_id, freq); + + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_OPEN_LOOP_MASK, + CS35L45_PLL_OPEN_LOOP_MASK); + + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_REFCLK_FREQ_MASK, + extclk_cfg << CS35L45_PLL_REFCLK_FREQ_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_REFCLK_EN_MASK, 0); + + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_REFCLK_SEL_MASK, + clksrc << CS35L45_PLL_REFCLK_SEL_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_OPEN_LOOP_MASK, 0); + + regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, + CS35L45_PLL_REFCLK_EN_MASK, + CS35L45_PLL_REFCLK_EN_MASK); + + return 0; +} + +static int cs35l45_msm_global_en_assert(struct cs35l45_private *cs35l45) +{ + if (cs35l45->amplifier_mode == AMP_MODE_RCV) + regmap_update_bits(cs35l45->regmap, CS35L45_BLOCK_ENABLES, + CS35L45_BST_EN_MASK, + CS35L45_BST_DISABLE_FET_ON << + CS35L45_BST_EN_SHIFT); + + return 0; +} + +static int cs35l45_amp_short_assert(struct cs35l45_private *cs35l45) +{ + if (cs35l45->global_err_rls < 0x7fffffff) + cs35l45->global_err_rls++; + + regmap_update_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, BIT(11), 0); + regmap_update_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, BIT(11), BIT(11)); + regmap_update_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, BIT(11), 0); + + return 0; +} + +static const struct cs35l45_irq_monitor cs35l45_irq_mons[] = { + { + .reg = CS35L45_IRQ1_EINT_1, + .mask = CS35L45_IRQ1_MASK_1, + .bitmask = CS35L45_MSM_GLOBAL_EN_ASSERT_MASK, + .description = "Global enable assertion", + .err_msg = "Global enable assert detected!", + .callback = cs35l45_msm_global_en_assert, + }, + { + .reg = CS35L45_IRQ1_EINT_1, + .mask = CS35L45_IRQ1_MASK_1, + .bitmask = CS35L45_AMP_SHORT_ERR_MASK, + .description = "Amplifier short error", + .err_msg = "AMP short error detected!\n", + .callback = cs35l45_amp_short_assert, + }, + { + .reg = CS35L45_IRQ1_EINT_1, + .mask = CS35L45_IRQ1_MASK_1, + .bitmask = CS35L45_BST_SHORT_ERR_MASK, + .description = "Boost inductor short error", + .err_msg = "BST short error detected!\n", + .callback = NULL, + }, +#if 0 // For debug purpose + { + .reg = CS35L45_IRQ1_EINT_3, + .mask = CS35L45_IRQ1_MASK_3, + .bitmask = CS35L45_PLL_LOCK_FLAG_MASK, + .description = "PLL lock flag", + .err_msg = "PLL lock flag detected!\n", + .callback = NULL, + //.callback = cs35l45_pll_lock_event, + }, + { + .reg = CS35L45_IRQ1_EINT_3, + .mask = CS35L45_IRQ1_MASK_3, + .bitmask = CS35L45_PLL_UNLOCK_FLAG_RISE_MASK, + .description = "PLL unlock flag rise", + .err_msg = "PLL unlock flag detected!\n", + .callback = NULL, + //.callback = cs35l45_pll_unlock_event, + }, +#endif + { + .reg = CS35L45_IRQ1_EINT_18, + .mask = CS35L45_IRQ1_MASK_18, + .bitmask = CS35L45_GLOBAL_ERROR_MASK, + .description = "Global error", + .err_msg = "Global error detected!\n", + .callback = NULL, + }, +}; + +static irqreturn_t cs35l45_irq(int irq, void *data) +{ + struct cs35l45_private *cs35l45 = data; + unsigned int irq_regs[] = {CS35L45_IRQ1_EINT_1, CS35L45_IRQ1_EINT_2, + CS35L45_IRQ1_EINT_3, CS35L45_IRQ1_EINT_4, + CS35L45_IRQ1_EINT_5, CS35L45_IRQ1_EINT_7, + CS35L45_IRQ1_EINT_8, CS35L45_IRQ1_EINT_18}; + unsigned int irq_masks[] = {CS35L45_IRQ1_MASK_1, CS35L45_IRQ1_MASK_2, + CS35L45_IRQ1_MASK_3, CS35L45_IRQ1_MASK_4, + CS35L45_IRQ1_MASK_5, CS35L45_IRQ1_MASK_7, + CS35L45_IRQ1_MASK_8, CS35L45_IRQ1_MASK_18}; + unsigned int status[ARRAY_SIZE(irq_regs)]; + unsigned int masks[ARRAY_SIZE(irq_masks)]; + unsigned int val; + unsigned int i; + int ret; + bool irq_detect = false; + + if (!cs35l45->initialized) + return IRQ_NONE; + + for (i = 0; i < ARRAY_SIZE(irq_regs); i++) { + regmap_read(cs35l45->regmap, irq_regs[i], &status[i]); + regmap_read(cs35l45->regmap, irq_masks[i], &masks[i]); + irq_detect |= (status[i] & (~masks[i])); + } + + if (!irq_detect) + return IRQ_NONE; + + for (i = 0; i < ARRAY_SIZE(cs35l45_irq_mons); i++) { + regmap_read(cs35l45->regmap, cs35l45_irq_mons[i].reg, &val); + if (!(val & cs35l45_irq_mons[i].bitmask)) + continue; + + regmap_write(cs35l45->regmap, cs35l45_irq_mons[i].reg, + cs35l45_irq_mons[i].bitmask); + + if (cs35l45_irq_mons[i].err_msg) + dev_err(cs35l45->dev, "%s\n", + cs35l45_irq_mons[i].err_msg); + + if (cs35l45_irq_mons[i].callback) { + ret = cs35l45_irq_mons[i].callback(cs35l45); + if (ret < 0) + dev_err(cs35l45->dev, + "IRQ (%s) callback failure (%d)\n", + cs35l45_irq_mons[i].description, ret); + } + } + + return IRQ_HANDLED; +} + +static int cs35l45_register_irq_monitors(struct cs35l45_private *cs35l45) +{ + unsigned int val; + int i; + + if (!cs35l45->irq) + return 0; + + for (i = 0; i < ARRAY_SIZE(cs35l45_irq_mons); i++) { + regmap_read(cs35l45->regmap, cs35l45_irq_mons[i].mask, &val); + if (!(val & cs35l45_irq_mons[i].bitmask)) { + dev_err(cs35l45->dev, "IRQ (%s) is already unmasked\n", + cs35l45_irq_mons[i].description); + continue; + } + + regmap_write(cs35l45->regmap, cs35l45_irq_mons[i].reg, + cs35l45_irq_mons[i].bitmask); + + regmap_update_bits(cs35l45->regmap, cs35l45_irq_mons[i].mask, + cs35l45_irq_mons[i].bitmask, 0); + } + + return 0; +} + +static int cs35l45_apply_of_data(struct cs35l45_private *cs35l45) +{ + struct cs35l45_platform_data *pdata = &cs35l45->pdata; + struct gpio_ctrl *gpios[] = {&pdata->gpio_ctrl1, &pdata->gpio_ctrl2, + &pdata->gpio_ctrl3}; + const struct of_entry *entry; + unsigned int gpio_regs[] = {CS35L45_GPIO1_CTRL1, CS35L45_GPIO2_CTRL1, + CS35L45_GPIO3_CTRL1}; + unsigned int pad_regs[] = {CS35L45_SYNC_GPIO1, + CS35L45_INTB_GPIO2_MCLK_REF, CS35L45_GPIO3}; + unsigned int val; + u32 *ptr; + int i, j; + + if (!pdata) + return 0; + + if (pdata->asp_sdout_hiz_ctrl & CS35L45_VALID_PDATA) { + val = pdata->asp_sdout_hiz_ctrl & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL3, + CS35L45_ASP_DOUT_HIZ_CTRL_MASK, + val << CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT); + } + + if (pdata->ngate_ch1_hold & CS35L45_VALID_PDATA) { + val = pdata->ngate_ch1_hold & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_MIXER_NGATE_CH1_CFG, + CS35L45_AUX_NGATE_CH_HOLD_MASK, + val << CS35L45_AUX_NGATE_CH_HOLD_SHIFT); + } + + if (pdata->ngate_ch1_thr & CS35L45_VALID_PDATA) { + val = pdata->ngate_ch1_thr & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_MIXER_NGATE_CH1_CFG, + CS35L45_AUX_NGATE_CH_THR_MASK, + val << CS35L45_AUX_NGATE_CH_THR_SHIFT); + } + + if (pdata->ngate_ch2_hold & CS35L45_VALID_PDATA) { + val = pdata->ngate_ch2_hold & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_MIXER_NGATE_CH2_CFG, + CS35L45_AUX_NGATE_CH_HOLD_MASK, + val << CS35L45_AUX_NGATE_CH_HOLD_SHIFT); + } + + if (pdata->ngate_ch2_thr & CS35L45_VALID_PDATA) { + val = pdata->ngate_ch2_thr & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_MIXER_NGATE_CH2_CFG, + CS35L45_AUX_NGATE_CH_THR_MASK, + val << CS35L45_AUX_NGATE_CH_THR_SHIFT); + } + + if (!pdata->bst_bpe_inst_cfg.is_present) + goto bst_bpe_misc_cfg; + + for (i = BST_BPE_INST_THLD; i < BST_BPE_INST_PARAMS; i++) { + for (j = L0; j < BST_BPE_INST_LEVELS; j++) { + entry = cs35l45_get_bst_bpe_inst_entry(j, i); + ptr = cs35l45_get_bst_bpe_inst_param(cs35l45, j, i); + val = ((*ptr) & (~CS35L45_VALID_PDATA)) << entry->shift; + if ((entry->reg) && ((*ptr) & CS35L45_VALID_PDATA)) + regmap_update_bits(cs35l45->regmap, entry->reg, + entry->mask, val); + } + } + +bst_bpe_misc_cfg: + if (!pdata->bst_bpe_misc_cfg.is_present) + goto bst_bpe_il_lim_cfg; + + for (i = BST_BPE_INST_INF_HOLD_RLS; i < BST_BPE_MISC_PARAMS; i++) { + ptr = cs35l45_get_bst_bpe_misc_param(cs35l45, i); + val = ((*ptr) & (~CS35L45_VALID_PDATA)) + << bst_bpe_misc_map[i].shift; + if ((*ptr) & CS35L45_VALID_PDATA) + regmap_update_bits(cs35l45->regmap, + bst_bpe_misc_map[i].reg, + bst_bpe_misc_map[i].mask, val); + } + +bst_bpe_il_lim_cfg: + if (!pdata->bst_bpe_il_lim_cfg.is_present) + goto hvlv_cfg; + + for (i = BST_BPE_IL_LIM_THLD_DEL1; i < BST_BPE_IL_LIM_PARAMS; i++) { + ptr = cs35l45_get_bst_bpe_il_lim_param(cs35l45, i); + val = ((*ptr) & (~CS35L45_VALID_PDATA)) + << bst_bpe_il_lim_map[i].shift; + if ((*ptr) & CS35L45_VALID_PDATA) + regmap_update_bits(cs35l45->regmap, + bst_bpe_il_lim_map[i].reg, + bst_bpe_il_lim_map[i].mask, val); + } + +hvlv_cfg: + if (!pdata->hvlv_cfg.is_present) + goto ldpm_cfg; + + if (pdata->hvlv_cfg.hvlv_thld_hys & CS35L45_VALID_PDATA) { + val = pdata->hvlv_cfg.hvlv_thld_hys & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_HVLV_CONFIG, + CS35L45_HVLV_THLD_HYS_MASK, + val << CS35L45_HVLV_THLD_HYS_SHIFT); + } + + if (pdata->hvlv_cfg.hvlv_thld & CS35L45_VALID_PDATA) { + val = pdata->hvlv_cfg.hvlv_thld & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_HVLV_CONFIG, + CS35L45_HVLV_THLD_MASK, + val << CS35L45_HVLV_THLD_SHIFT); + } + + if (pdata->hvlv_cfg.hvlv_dly & CS35L45_VALID_PDATA) { + val = pdata->hvlv_cfg.hvlv_dly & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, CS35L45_HVLV_CONFIG, + CS35L45_HVLV_DLY_MASK, + val << CS35L45_HVLV_DLY_SHIFT); + } + +ldpm_cfg: + if (!pdata->ldpm_cfg.is_present) + goto classh_cfg; + + for (i = LDPM_GP1_BOOST_SEL; i < LDPM_PARAMS; i++) { + ptr = cs35l45_get_ldpm_param(cs35l45, i); + val = ((*ptr) & (~CS35L45_VALID_PDATA)) << ldpm_map[i].shift; + if ((*ptr) & CS35L45_VALID_PDATA) + regmap_update_bits(cs35l45->regmap, ldpm_map[i].reg, + ldpm_map[i].mask, val); + } + +classh_cfg: + if (!pdata->classh_cfg.is_present) + goto gpio_cfg; + + for (i = CH_HDRM; i < CLASSH_PARAMS; i++) { + ptr = cs35l45_get_classh_param(cs35l45, i); + val = ((*ptr) & (~CS35L45_VALID_PDATA)) << classh_map[i].shift; + if ((*ptr) & CS35L45_VALID_PDATA) + regmap_update_bits(cs35l45->regmap, classh_map[i].reg, + classh_map[i].mask, val); + } + + regmap_update_bits(cs35l45->regmap, CS35L45_CLASSH_CONFIG3, + CS35L45_CH_OVB_LATCH_MASK, + CS35L45_CH_OVB_LATCH_MASK); + + regmap_update_bits(cs35l45->regmap, CS35L45_CLASSH_CONFIG3, + CS35L45_CH_OVB_LATCH_MASK, 0); + +gpio_cfg: + for (i = 0; i < ARRAY_SIZE(gpios); i++) { + if (!gpios[i]->is_present) + continue; + + if (gpios[i]->dir & CS35L45_VALID_PDATA) { + val = gpios[i]->dir & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, gpio_regs[i], + CS35L45_GPIO_DIR_MASK, + val << CS35L45_GPIO_DIR_SHIFT); + } + + if (gpios[i]->lvl & CS35L45_VALID_PDATA) { + val = gpios[i]->lvl & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, gpio_regs[i], + CS35L45_GPIO_LVL_MASK, + val << CS35L45_GPIO_LVL_SHIFT); + } + + if (gpios[i]->op_cfg & CS35L45_VALID_PDATA) { + val = gpios[i]->op_cfg & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, gpio_regs[i], + CS35L45_GPIO_OP_CFG_MASK, + val << CS35L45_GPIO_OP_CFG_SHIFT); + } + + if (gpios[i]->pol & CS35L45_VALID_PDATA) { + val = gpios[i]->pol & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, gpio_regs[i], + CS35L45_GPIO_POL_MASK, + val << CS35L45_GPIO_POL_SHIFT); + } + + if (gpios[i]->ctrl & CS35L45_VALID_PDATA) { + val = gpios[i]->ctrl & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, pad_regs[i], + CS35L45_GPIO_CTRL_MASK, + val << CS35L45_GPIO_CTRL_SHIFT); + } + + if (gpios[i]->invert & CS35L45_VALID_PDATA) { + val = gpios[i]->invert & (~CS35L45_VALID_PDATA); + regmap_update_bits(cs35l45->regmap, pad_regs[i], + CS35L45_GPIO_INVERT_MASK, + val << CS35L45_GPIO_INVERT_SHIFT); + } + } + + return 0; +} + +static int cs35l45_parse_of_data(struct cs35l45_private *cs35l45) +{ + struct cs35l45_platform_data *pdata = &cs35l45->pdata; + struct device_node *node = cs35l45->dev->of_node; + struct device_node *child; + const struct of_entry *entry; + struct gpio_ctrl *gpios[] = {&pdata->gpio_ctrl1, &pdata->gpio_ctrl2, + &pdata->gpio_ctrl3}; + unsigned int val, num_fast_switch, params[BST_BPE_INST_LEVELS]; + char of_name[32]; + u32 *ptr; + int ret, i, j; + + if ((!node) || (!pdata)) + return 0; + + ret = of_property_count_strings(node, "cirrus,fast-switch"); + if (ret < 0) { + /* + * device tree do not provide file name. + * Use default value + */ + num_fast_switch = ARRAY_SIZE(cs35l45_fast_switch_text); + cs35l45->fast_switch_enum.items = + ARRAY_SIZE(cs35l45_fast_switch_text); + cs35l45->fast_switch_enum.texts = cs35l45_fast_switch_text; + cs35l45->fast_switch_names = cs35l45_fast_switch_text; + } else { + /* Device tree provides file name */ + num_fast_switch = (size_t)ret; + dev_info(cs35l45->dev, "num_fast_switch:%u\n", num_fast_switch); + cs35l45->fast_switch_names = + devm_kmalloc(cs35l45->dev, + num_fast_switch * sizeof(char *), + GFP_KERNEL); + if (!cs35l45->fast_switch_names) + return -ENOMEM; + of_property_read_string_array(node, "cirrus,fast-switch", + cs35l45->fast_switch_names, + num_fast_switch); + for (i = 0; i < num_fast_switch; i++) { + dev_info(cs35l45->dev, "%d:%s\n", i, + cs35l45->fast_switch_names[i]); + } + cs35l45->fast_switch_enum.items = num_fast_switch; + cs35l45->fast_switch_enum.texts = cs35l45->fast_switch_names; + } + + cs35l45->fast_switch_enum.reg = SND_SOC_NOPM; + cs35l45->fast_switch_enum.shift_l = 0; + cs35l45->fast_switch_enum.shift_r = 0; + cs35l45->fast_switch_enum.mask = + roundup_pow_of_two(num_fast_switch) - 1; + + ret = of_property_read_u32(node, "cirrus,asp-sdout-hiz-ctrl", &val); + if (!ret) + pdata->asp_sdout_hiz_ctrl = val | CS35L45_VALID_PDATA; + + pdata->use_tdm_slots = of_property_read_bool(node, + "cirrus,use-tdm-slots"); + + ret = of_property_read_string(node, "cirrus,dsp-part-name", + &pdata->dsp_part_name); + if (ret < 0) + pdata->dsp_part_name = "cs35l45"; + + ret = of_property_read_u32(node, "cirrus,ngate-ch1-hold", &val); + if (!ret) + pdata->ngate_ch1_hold = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(node, "cirrus,ngate-ch1-thr", &val); + if (!ret) + pdata->ngate_ch1_thr = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(node, "cirrus,ngate-ch2-hold", &val); + if (!ret) + pdata->ngate_ch2_hold = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(node, "cirrus,ngate-ch2-thr", &val); + if (!ret) + pdata->ngate_ch2_thr = val | CS35L45_VALID_PDATA; + + child = of_get_child_by_name(node, "cirrus,bst-bpe-inst-config"); + pdata->bst_bpe_inst_cfg.is_present = child ? true : false; + if (!pdata->bst_bpe_inst_cfg.is_present) + goto bst_bpe_misc_cfg; + + for (i = BST_BPE_INST_THLD; i < BST_BPE_INST_PARAMS; i++) { + entry = cs35l45_get_bst_bpe_inst_entry(L0, i); + ret = of_property_read_u32_array(child, entry->name, params, + BST_BPE_INST_LEVELS); + if (ret) + continue; + + for (j = L0; j < BST_BPE_INST_LEVELS; j++) { + ptr = cs35l45_get_bst_bpe_inst_param(cs35l45, j, i); + (*ptr) = params[j] | CS35L45_VALID_PDATA; + } + } + + of_node_put(child); + +bst_bpe_misc_cfg: + child = of_get_child_by_name(node, "cirrus,bst-bpe-misc-config"); + pdata->bst_bpe_misc_cfg.is_present = child ? true : false; + if (!pdata->bst_bpe_misc_cfg.is_present) + goto bst_bpe_il_lim_cfg; + + for (i = BST_BPE_INST_INF_HOLD_RLS; i < BST_BPE_MISC_PARAMS; i++) { + ptr = cs35l45_get_bst_bpe_misc_param(cs35l45, i); + ret = of_property_read_u32(child, bst_bpe_misc_map[i].name, + &val); + if (!ret) + (*ptr) = val | CS35L45_VALID_PDATA; + } + + of_node_put(child); + +bst_bpe_il_lim_cfg: + child = of_get_child_by_name(node, "cirrus,bst-bpe-il-lim-config"); + pdata->bst_bpe_il_lim_cfg.is_present = child ? true : false; + if (!pdata->bst_bpe_il_lim_cfg.is_present) + goto hvlv_cfg; + + for (i = BST_BPE_IL_LIM_THLD_DEL1; i < BST_BPE_IL_LIM_PARAMS; i++) { + ptr = cs35l45_get_bst_bpe_il_lim_param(cs35l45, i); + ret = of_property_read_u32(child, bst_bpe_il_lim_map[i].name, + &val); + if (!ret) + (*ptr) = val | CS35L45_VALID_PDATA; + } + + of_node_put(child); + +hvlv_cfg: + child = of_get_child_by_name(node, "cirrus,hvlv-config"); + pdata->hvlv_cfg.is_present = child ? true : false; + if (!pdata->hvlv_cfg.is_present) + goto ldpm_cfg; + + ret = of_property_read_u32(child, "hvlv-thld-hys", &val); + if (!ret) + pdata->hvlv_cfg.hvlv_thld_hys = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(child, "hvlv-thld", &val); + if (!ret) + pdata->hvlv_cfg.hvlv_thld = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(child, "hvlv-dly", &val); + if (!ret) + pdata->hvlv_cfg.hvlv_dly = val | CS35L45_VALID_PDATA; + + of_node_put(child); + +ldpm_cfg: + child = of_get_child_by_name(node, "cirrus,ldpm-config"); + pdata->ldpm_cfg.is_present = child ? true : false; + if (!pdata->ldpm_cfg.is_present) + goto classh_cfg; + + for (i = LDPM_GP1_BOOST_SEL; i < LDPM_PARAMS; i++) { + ptr = cs35l45_get_ldpm_param(cs35l45, i); + ret = of_property_read_u32(child, ldpm_map[i].name, &val); + if (!ret) + (*ptr) = val | CS35L45_VALID_PDATA; + } + + of_node_put(child); + +classh_cfg: + child = of_get_child_by_name(node, "cirrus,classh-config"); + pdata->classh_cfg.is_present = child ? true : false; + if (!pdata->classh_cfg.is_present) + goto gpio_cfg; + + for (i = CH_HDRM; i < CLASSH_PARAMS; i++) { + ptr = cs35l45_get_classh_param(cs35l45, i); + ret = of_property_read_u32(child, classh_map[i].name, &val); + if (!ret) + (*ptr) = val | CS35L45_VALID_PDATA; + } + + of_node_put(child); + +gpio_cfg: + for (i = 0; i < ARRAY_SIZE(gpios); i++) { + sprintf(of_name, "cirrus,gpio-ctrl%d", i + 1); + child = of_get_child_by_name(node, of_name); + gpios[i]->is_present = child ? true : false; + if (!gpios[i]->is_present) + continue; + + ret = of_property_read_u32(child, "gpio-dir", &val); + if (!ret) + gpios[i]->dir = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(child, "gpio-lvl", &val); + if (!ret) + gpios[i]->lvl = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(child, "gpio-op-cfg", &val); + if (!ret) + gpios[i]->op_cfg = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(child, "gpio-pol", &val); + if (!ret) + gpios[i]->pol = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(child, "gpio-ctrl", &val); + if (!ret) + gpios[i]->ctrl = val | CS35L45_VALID_PDATA; + + ret = of_property_read_u32(child, "gpio-invert", &val); + if (!ret) + gpios[i]->invert = val | CS35L45_VALID_PDATA; + + of_node_put(child); + } + + return 0; +} + +static int cs35l45_hibernate(struct cs35l45_private *cs35l45, bool hiber_en) +{ + unsigned int sts, cmd, val; + int ret, i; + struct cs35l45_mixer_cache mixer_cache[] = { + {CS35L45_ASPTX1_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_ASPTX2_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_ASPTX3_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_ASPTX4_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX1_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX2_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX3_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX4_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX5_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX6_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX7_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DSP1RX8_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_DACPCM1_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_NGATE1_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_NGATE2_INPUT, CS35L45_PCM_SRC_MASK, 0}, + {CS35L45_AMP_GAIN, CS35L45_AMP_GAIN_PCM_MASK, 0}, + {CS35L45_AMP_OUTPUT_MUTE, CS35L45_AMP_MUTE_MASK, 0}, + {CS35L45_AMP_PCM_CONTROL, CS35L45_AMP_VOL_PCM_MASK, 0}, + {CS35L45_ASP_FRAME_CONTROL1, CS35L45_ASP_TX_ALL_SLOTS, 0}, + {CS35L45_ASP_FRAME_CONTROL5, CS35L45_ASP_RX_ALL_SLOTS, 0}, + }; + + if (hiber_en == cs35l45->hibernate_mode) + return 0; + + if (!cs35l45->dsp.booted) { + dev_err(cs35l45->dev, "Firmware not loaded\n"); + return -EPERM; + } + + if (hiber_en == HIBER_MODE_EN) { + regmap_read(cs35l45->regmap, CS35L45_DSP_MBOX_2, &sts); + if (((enum cspl_mboxstate)sts) != CSPL_MBOX_STS_PAUSED) { + dev_err(cs35l45->dev, "FW not paused (%d)\n", sts); + return -EINVAL; + } + + flush_work(&cs35l45->dsp_pmd_work); + + cmd = CSPL_MBOX_CMD_HIBERNATE; + regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, cmd); + + ret = cs35l45_activate_ctl(cs35l45, "DSP1 Preload Switch", + false); + if (ret < 0) + dev_err(cs35l45->dev, "Unable to deactivate ctl (%d)\n", + ret); + + cs35l45->initialized = false; + + regcache_cache_only(cs35l45->regmap, true); + } else /* HIBER_MODE_DIS */ { + for (i = 0; i < ARRAY_SIZE(mixer_cache); i++) + regmap_read(cs35l45->regmap, mixer_cache[i].reg, + &mixer_cache[i].val); + + regcache_cache_only(cs35l45->regmap, false); + + regcache_drop_region(cs35l45->regmap, CS35L45_DEVID, + CS35L45_MIXER_NGATE_CH2_CFG); + + for (i = 0; i < 5; i++) { + usleep_range(200, 300); + + ret = regmap_read(cs35l45->regmap, CS35L45_DEVID, &val); + if (!ret) + break; + } + + if (i == 5) { + dev_info(cs35l45->dev, "Timeout trying to wake amp"); + return -ETIMEDOUT; + } + + ret = __cs35l45_initialize(cs35l45); + if (ret < 0) { + dev_err(cs35l45->dev, "Failed to reinitialize (%d)\n", + ret); + return ret; + } + + regmap_update_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL, + CS35L45_MEM_RDY_MASK, CS35L45_MEM_RDY_MASK); + + usleep_range(100, 200); + + cmd = CSPL_MBOX_CMD_OUT_OF_HIBERNATE; + ret = cs35l45_set_csplmboxcmd(cs35l45, cmd); + if (ret < 0) + dev_err(cs35l45->dev, "MBOX failure (%d)\n", ret); + + for (i = 0; i < ARRAY_SIZE(mixer_cache); i++) + regmap_update_bits(cs35l45->regmap, mixer_cache[i].reg, + mixer_cache[i].mask, + mixer_cache[i].val); + + ret = cs35l45_activate_ctl(cs35l45, "DSP1 Preload Switch", + true); + if (ret < 0) + dev_err(cs35l45->dev, "Unable to activate ctl (%d)\n", + ret); + } + + cs35l45->hibernate_mode = hiber_en; + + return 0; +} + +static const struct reg_sequence cs35l45_sync_patch[] = { + {0x00000040, 0x00000055}, + {0x00000040, 0x000000AA}, + {0x00000044, 0x00000055}, + {0x00000044, 0x000000AA}, + {CS35L45_GLOBAL_OVERRIDES, 0x0000000A}, + {0x0000350C, 0x7FF0007C}, + {0x00003510, 0x00007FF0}, + {0x00000040, 0x00000000}, + {0x00000044, 0x00000000}, +}; + +static const struct reg_sequence cs35l45_init_patch[] = { + {0x00000040, 0x00000055}, + {0x00000040, 0x000000AA}, + {0x00000044, 0x00000055}, + {0x00000044, 0x000000AA}, + {0x00006480, 0x0830500A}, + {0x00007C60, 0x1000850B}, + {CS35L45_BOOST_OV_CFG, 0x007000D0}, + {CS35L45_LDPM_CONFIG, 0x0001B636}, + {0x00002C08, 0x00000009}, + {0x00006850, 0x0A30FFC4}, + {0x00003820, 0x00040100}, + {0x00003824, 0x00000000}, + {0x00007CFC, 0x62870004}, + {0x00000040, 0x00000000}, + {0x00000044, 0x00000000}, + {CS35L45_BOOST_CCM_CFG, 0xF0000003}, + {CS35L45_BOOST_DCM_CFG, 0x08710220}, + {CS35L45_ERROR_RELEASE, 0x00200000}, +}; + +static int __cs35l45_initialize(struct cs35l45_private *cs35l45) +{ + struct device *dev = cs35l45->dev; + unsigned int sts; + int ret, i; + + if (cs35l45->initialized) + return -EPERM; + + for (i = 0; i < 5; i++) { + usleep_range(1000, 1100); + + regmap_read(cs35l45->regmap, CS35L45_IRQ1_EINT_4, &sts); + if (!(sts & CS35L45_OTP_BOOT_DONE_STS_MASK)) + continue; + + regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_4, + CS35L45_OTP_BOOT_DONE_STS_MASK | + CS35L45_OTP_BUSY_MASK); + + break; + } + + if (i == 5) { + dev_err(cs35l45->dev, "Timeout waiting for OTP boot\n"); + return -ETIMEDOUT; + } + + ret = regmap_register_patch(cs35l45->regmap, cs35l45_init_patch, + ARRAY_SIZE(cs35l45_init_patch)); + if (ret < 0) { + dev_err(dev, "Failed to apply init patch %d\n", ret); + return ret; + } + + regmap_write(cs35l45->regmap, CS35L45_MIXER_PILOT0_INPUT, + CS35L45_PCM_SRC_DSP_TX2); + + ret = cs35l45_apply_of_data(cs35l45); + if (ret < 0) { + dev_err(dev, "applying OF data failed (%d)\n", ret); + return ret; + } + + if (cs35l45->irq) { + ret = cs35l45_register_irq_monitors(cs35l45); + if (ret < 0) { + dev_err(dev, "Failed to register IRQ monitors: %d\n", + ret); + return ret; + } + } + + regmap_update_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL, + CS35L45_WKSRC_EN_MASK, + cs35l45->wksrc << CS35L45_WKSRC_EN_SHIFT); + + regmap_update_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL, + CS35L45_UPDT_WKCTL_MASK, CS35L45_UPDT_WKCTL_MASK); + + regmap_update_bits(cs35l45->regmap, CS35L45_WKI2C_CTL, + CS35L45_WKI2C_ADDR_MASK, cs35l45->i2c_addr); + + regmap_update_bits(cs35l45->regmap, CS35L45_WKI2C_CTL, + CS35L45_UPDT_WKI2C_MASK, CS35L45_UPDT_WKI2C_MASK); + + ret = regmap_register_patch(cs35l45->regmap, cs35l45_sync_patch, + ARRAY_SIZE(cs35l45_sync_patch)); + if (ret < 0) { + dev_err(dev, "Failed to apply sync patch %d\n", ret); + return ret; + } + + /* + * Workarounds: + * To be modified accordingly to match firmware version + */ + + // Workaround: Change DSP_RXn defaults to match firmware 6.28 and above with PICL. + #if 1 + regmap_update_bits(cs35l45->regmap, CS35L45_DSP1RX5_INPUT, GENMASK(6, 0), CS35L45_PCM_SRC_VDD_BATTMON); + regmap_update_bits(cs35l45->regmap, CS35L45_DSP1RX6_INPUT, GENMASK(6, 0), CS35L45_PCM_SRC_VDD_BSTMON); + regmap_update_bits(cs35l45->regmap, CS35L45_DSP1RX7_INPUT, GENMASK(6, 0), CS35L45_PCM_SRC_CLASSH_TGT); + #endif + + // Workaround: Preset PLL clock once in early stage without AP clock + + cs35l45_set_sysclk(cs35l45, 0, 12288000); + + /* + * Workarounds end. + */ + + cs35l45->initialized = true; + + return 0; +} + +int cs35l45_initialize(struct cs35l45_private *cs35l45) +{ + struct device *dev = cs35l45->dev; + unsigned int dev_id, rev_id; + int ret; + + ret = regmap_read(cs35l45->regmap, CS35L45_DEVID, &dev_id); + if (ret < 0) { + dev_err(dev, "Get Device ID failed\n"); + return ret; + } + + ret = regmap_read(cs35l45->regmap, CS35L45_REVID, &rev_id); + if (ret < 0) { + dev_err(dev, "Get Revision ID failed\n"); + return ret; + } + + ret = __cs35l45_initialize(cs35l45); + if (ret < 0) { + dev_err(dev, "CS35L45 failed to initialize (%d)\n", ret); + return ret; + } + + regmap_update_bits(cs35l45->regmap, + CS35L45_DSP1_STREAM_ARB_TX1_CONFIG_0, + CS35L45_DSP1_STREAM_ARB_TX1_EN_MASK, 0); + + regmap_update_bits(cs35l45->regmap, + CS35L45_DSP1_STREAM_ARB_MSTR1_CONFIG_0, + CS35L45_DSP1_STREAM_ARB_MSTR0_EN_MASK, 0); + + regmap_update_bits(cs35l45->regmap, CS35L45_DSP1_CCM_CORE_CONTROL, + CS35L45_CCM_CORE_EN_MASK, 0); + + dev_info(dev, "Cirrus Logic CS35L45 (%x), Revision: %02X\n", dev_id, + rev_id); + + return 0; +} +EXPORT_SYMBOL_GPL(cs35l45_initialize); + +static const struct wm_adsp_region cs35l45_dsp1_regions[] = { + { .type = WMFW_HALO_PM_PACKED, .base = CS35L45_DSP1_PMEM_0 }, + { .type = WMFW_HALO_XM_PACKED, .base = CS35L45_DSP1_XMEM_PACK_0 }, + { .type = WMFW_HALO_YM_PACKED, .base = CS35L45_DSP1_YMEM_PACK_0 }, + {. type = WMFW_ADSP2_XM, .base = CS35L45_DSP1_XMEM_UNPACK24_0}, + {. type = WMFW_ADSP2_YM, .base = CS35L45_DSP1_YMEM_UNPACK24_0}, +}; + +static int cs35l45_dsp_init(struct cs35l45_private *cs35l45) +{ + struct wm_adsp *dsp = &cs35l45->dsp; + int ret, i; + + dsp->part = cs35l45->pdata.dsp_part_name; + dsp->num = 1; + dsp->type = WMFW_HALO; + dsp->rev = 0; + dsp->dev = cs35l45->dev; + dsp->regmap = cs35l45->regmap; + dsp->base = CS35L45_DSP1_CLOCK_FREQ; + dsp->base_sysinfo = CS35L45_DSP1_SYS_ID; + dsp->mem = cs35l45_dsp1_regions; + dsp->num_mems = ARRAY_SIZE(cs35l45_dsp1_regions); + dsp->lock_regions = 0xFFFFFFFF; + dsp->n_rx_channels = CS35L45_DSP_N_RX_RATES; + dsp->n_tx_channels = CS35L45_DSP_N_TX_RATES; + + mutex_init(&cs35l45->rate_lock); + ret = wm_halo_init(dsp, &cs35l45->rate_lock); + + for (i = 0; i < CS35L45_DSP_N_RX_RATES; i++) + dsp->rx_rate_cache[i] = 0x1; + + for (i = 0; i < CS35L45_DSP_N_TX_RATES; i++) + dsp->tx_rate_cache[i] = 0x1; + + if (!cs35l45_halo_start_core) { + cs35l45_halo_start_core = dsp->ops->start_core; + cs35l45_halo_ops = (*dsp->ops); + cs35l45_halo_ops.start_core = NULL; + } + + dsp->ops = &cs35l45_halo_ops; + + return ret; +} + +static const char * const cs35l45_supplies[] = {"VA", "VP"}; + +int cs35l45_probe(struct cs35l45_private *cs35l45) +{ + struct device *dev = cs35l45->dev; + unsigned long irq_pol = IRQF_ONESHOT | IRQF_SHARED; + int ret; + u32 i; + + cs35l45->fast_switch_en = false; + cs35l45->fast_switch_file_idx = 0; + + INIT_WORK(&cs35l45->dsp_pmd_work, cs35l45_dsp_pmd_work); + + mutex_init(&cs35l45->dsp_pmd_lock); + + for (i = 0; i < ARRAY_SIZE(cs35l45_supplies); i++) + cs35l45->supplies[i].supply = cs35l45_supplies[i]; + + ret = devm_regulator_bulk_get(dev, CS35L45_NUM_SUPPLIES, + cs35l45->supplies); + if (ret < 0) { + dev_err(dev, "Failed to request core supplies: %d\n", ret); + return ret; + } + + ret = regulator_bulk_enable(CS35L45_NUM_SUPPLIES, cs35l45->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable core supplies: %d\n", ret); + return ret; + } + + /* returning NULL can be an option if in stereo mode */ + cs35l45->reset_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(cs35l45->reset_gpio)) { + ret = PTR_ERR(cs35l45->reset_gpio); + cs35l45->reset_gpio = NULL; + if (ret == -EBUSY) { + dev_info(dev, + "Reset line busy, assuming shared reset\n"); + } else { + dev_err(dev, "Failed to get reset GPIO: %d\n", ret); + goto err; + } + } + + if (cs35l45->reset_gpio) { + gpiod_set_value_cansleep(cs35l45->reset_gpio, 0); + usleep_range(2000, 2100); + gpiod_set_value_cansleep(cs35l45->reset_gpio, 1); + } + + cs35l45->slot_width = CS35L45_DEFAULT_SLOT_WIDTH; + + ret = cs35l45_parse_of_data(cs35l45); + if (ret < 0) { + dev_err(dev, "parsing OF data failed: %d\n", ret); + goto err; + } + + ret = cs35l45_dsp_init(cs35l45); + if (ret < 0) { + dev_err(dev, "dsp_init failed: %d\n", ret); + goto err; + } + + if (cs35l45->irq) { + if (cs35l45->pdata.gpio_ctrl2.invert & (~CS35L45_VALID_PDATA)) + irq_pol |= IRQF_TRIGGER_HIGH; + else + irq_pol |= IRQF_TRIGGER_LOW; + + ret = devm_request_threaded_irq(dev, cs35l45->irq, NULL, + cs35l45_irq, irq_pol, + "cs35l45", cs35l45); + if (ret < 0) + dev_warn(cs35l45->dev, "Failed to request IRQ: %d\n", + ret); + } + + return devm_snd_soc_register_component(dev, &cs35l45_component, + &cs35l45_dai, 1); + +err: + regulator_bulk_disable(CS35L45_NUM_SUPPLIES, cs35l45->supplies); + return ret; +} +EXPORT_SYMBOL_GPL(cs35l45_probe); + +int cs35l45_remove(struct cs35l45_private *cs35l45) +{ + if (cs35l45->reset_gpio) + gpiod_set_value_cansleep(cs35l45->reset_gpio, 0); + + wm_adsp2_remove(&cs35l45->dsp); + regulator_bulk_disable(CS35L45_NUM_SUPPLIES, cs35l45->supplies); + + return 0; +} +EXPORT_SYMBOL_GPL(cs35l45_remove); + +MODULE_DESCRIPTION("ASoC CS35L45 driver"); +MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l45/cs35l45.h b/techpack/audio/asoc/codecs/cs35l45/cs35l45.h new file mode 100644 index 0000000000000..295c47cb71ade --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/cs35l45.h @@ -0,0 +1,741 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * cs35l45.h - CS35L45 ALSA SoC audio driver + * + * Copyright 2019 Cirrus Logic, Inc. + * + * Author: James Schulman + * + */ + +#ifndef __CS35L45_H__ +#define __CS35L45_H__ + +#include + +#define CS35L45_DEVID 0x00000000 +#define CS35L45_REVID 0x00000004 +#define CS35L45_RELID 0x0000000C +#define CS35L45_OTPID 0x00000010 +#define CS35L45_SFT_RESET 0x00000020 +#define CS35L45_GLOBAL_ENABLES 0x00002014 +#define CS35L45_BLOCK_ENABLES 0x00002018 +#define CS35L45_BLOCK_ENABLES2 0x0000201C +#define CS35L45_GLOBAL_OVERRIDES 0x00002020 +#define CS35L45_GLOBAL_SYNC 0x00002024 +#define CS35L45_ERROR_RELEASE 0x00002034 +#define CS35L45_CHIP_STATUS 0x00002040 +#define CS35L45_REG_2114 0x00002114 +#define CS35L45_REG_225C 0x0000225C +#define CS35L45_SYNC_GPIO1 0x00002430 +#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434 +#define CS35L45_GPIO3 0x00002438 +#define CS35L45_GPIO_GLOBAL_ENABLE_CONTROL 0x00002440 +#define CS35L45_PWRMGT_CTL 0x00002900 +#define CS35L45_WAKESRC_CTL 0x00002904 +#define CS35L45_WKI2C_CTL 0x00002908 +#define CS35L45_PWRMGT_STS 0x0000290C +#define CS35L45_REFCLK_INPUT 0x00002C04 +#define CS35L45_REG_2C08 0x00002C08 +#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C +#define CS35L45_SWIRE_CLK_CTRL 0x00002C14 +#define CS35L45_SYNC_TX_RX_ENABLES 0x00003400 +#define CS35L45_SYNC_SW_TX_ID 0x00003408 +#define CS35L45_BOOST_VOLTAGE_CFG 0x00003800 +#define CS35L45_BOOST_CCM_CFG 0x00003808 +#define CS35L45_BOOST_DCM_CFG 0x0000380C +#define CS35L45_BOOST_LPMODE_CFG 0x00003810 +#define CS35L45_BOOST_RAMP_CFG 0x00003814 +#define CS35L45_BOOST_STARTUP_CFG 0x00003818 +#define CS35L45_BOOST_OV_CFG 0x0000382C +#define CS35L45_BOOST_UV_CFG 0x00003830 +#define CS35L45_BOOST_STATUS 0x00003834 +#define CS35L45_BST_BPE_INST_THLD 0x00003C00 +#define CS35L45_BST_BPE_INST_ILIM 0x00003C04 +#define CS35L45_BST_BPE_INST_SS_ILIM 0x00003C08 +#define CS35L45_BST_BPE_INST_ATK_RATE 0x00003C0C +#define CS35L45_BST_BPE_INST_HOLD_TIME 0x00003C10 +#define CS35L45_BST_BPE_INST_RLS_RATE 0x00003C14 +#define CS35L45_BST_BPE_MISC_CONFIG 0x00003C20 +#define CS35L45_BST_BPE_IL_LIM_THLD 0x00003C24 +#define CS35L45_BST_BPE_IL_LIM_DLY 0x00003C28 +#define CS35L45_BST_BPE_IL_LIM_ATK_RATE 0x00003C2C +#define CS35L45_BST_BPE_IL_LIM_RLS_RATE 0x00003C30 +#define CS35L45_BST_BPE_INST_STATUS 0x00003C3C +#define CS35L45_MONITOR_FILT 0x00004008 +#define CS35L45_IMON_COMP 0x00004010 +#define CS35L45_STATUS 0x00004200 +#define CS35L45_MON_VALUE 0x00004404 +#define CS35L45_ASP_ENABLES1 0x00004800 +#define CS35L45_ASP_CONTROL1 0x00004804 +#define CS35L45_ASP_CONTROL2 0x00004808 +#define CS35L45_ASP_CONTROL3 0x0000480C +#define CS35L45_ASP_FRAME_CONTROL1 0x00004810 +#define CS35L45_ASP_FRAME_CONTROL2 0x00004814 +#define CS35L45_ASP_FRAME_CONTROL5 0x00004820 +#define CS35L45_ASP_DATA_CONTROL1 0x00004830 +#define CS35L45_ASP_DATA_CONTROL5 0x00004840 +#define CS35L45_DACPCM1_INPUT 0x00004C00 +#define CS35L45_MIXER_PILOT0_INPUT 0x00004C04 +#define CS35L45_ASPTX1_INPUT 0x00004C20 +#define CS35L45_ASPTX2_INPUT 0x00004C24 +#define CS35L45_ASPTX3_INPUT 0x00004C28 +#define CS35L45_ASPTX4_INPUT 0x00004C2C +#define CS35L45_ASPTX5_INPUT 0x00004C30 +#define CS35L45_DSP1RX1_INPUT 0x00004C40 +#define CS35L45_DSP1RX2_INPUT 0x00004C44 +#define CS35L45_DSP1RX3_INPUT 0x00004C48 +#define CS35L45_DSP1RX4_INPUT 0x00004C4C +#define CS35L45_DSP1RX5_INPUT 0x00004C50 +#define CS35L45_DSP1RX6_INPUT 0x00004C54 +#define CS35L45_DSP1RX7_INPUT 0x00004C58 +#define CS35L45_DSP1RX8_INPUT 0x00004C5C +#define CS35L45_NGATE1_INPUT 0x00004C60 +#define CS35L45_NGATE2_INPUT 0x00004C64 +#define CS35L45_SWIRE_PORT1_CH1_INPUT 0x00004C70 +#define CS35L45_SWIRE_PORT1_CH2_INPUT 0x00004C74 +#define CS35L45_SWIRE_PORT1_CH3_INPUT 0x00004C78 +#define CS35L45_SWIRE_PORT1_CH4_INPUT 0x00004C7C +#define CS35L45_SWIRE_PORT1_CH5_INPUT 0x00004C80 +#define CS35L45_AMP_ERR_VOL_SEL 0x00006000 +#define CS35L45_TEMP_WARN_THRESHOLD 0x00006020 +#define CS35L45_TEMP_WARN_CONFIG 0x00006024 +#define CS35L45_TEMP_WARN_TRIG_AUTO 0x00006028 +#define CS35L45_TEMP_WARN_STATUS 0x0000602C +#define CS35L45_BPE_INST_THLD 0x00006064 +#define CS35L45_BPE_INST_ATTN 0x00006068 +#define CS35L45_BPE_INST_ATK_RATE 0x00006074 +#define CS35L45_BPE_INST_HOLD_TIME 0x00006080 +#define CS35L45_BPE_INST_RLS_RATE 0x00006084 +#define CS35L45_BPE_MISC_CONFIG 0x00006090 +#define CS35L45_BPE_INST_STATUS 0x00006094 +#define CS35L45_HVLV_CONFIG 0x00006400 +#define CS35L45_LDPM_CONFIG 0x00006404 +#define CS35L45_CLASSH_CONFIG1 0x00006408 +#define CS35L45_CLASSH_CONFIG2 0x0000640C +#define CS35L45_CLASSH_CONFIG3 0x00006410 +#define CS35L45_AUD_MEM 0x00006418 +#define CS35L45_AMP_PCM_CONTROL 0x00007000 +#define CS35L45_AMP_PCM_HPF_TST 0x00007004 +#define CS35L45_AMP_GAIN 0x00007800 +#define CS35L45_DAC_MSM_CONFIG 0x00007C00 +#define CS35L45_AMP_OUTPUT_MUTE 0x00007C04 +#define CS35L45_AMP_OUTPUT_DRV 0x00007C08 +#define CS35L45_ALIVE_DCIN_WD 0x00007C20 +#define CS35L45_IRQ1_CFG 0x0000E000 +#define CS35L45_IRQ1_STATUS 0x0000E004 +#define CS35L45_IRQ1_EINT_1 0x0000E010 +#define CS35L45_IRQ1_EINT_2 0x0000E014 +#define CS35L45_IRQ1_EINT_3 0x0000E018 +#define CS35L45_IRQ1_EINT_4 0x0000E01C +#define CS35L45_IRQ1_EINT_5 0x0000E020 +#define CS35L45_IRQ1_EINT_7 0x0000E028 +#define CS35L45_IRQ1_EINT_8 0x0000E02C +#define CS35L45_IRQ1_EINT_18 0x0000E054 +#define CS35L45_IRQ1_STS_1 0x0000E090 +#define CS35L45_IRQ1_STS_2 0x0000E094 +#define CS35L45_IRQ1_STS_3 0x0000E098 +#define CS35L45_IRQ1_STS_4 0x0000E09C +#define CS35L45_IRQ1_STS_5 0x0000E0A0 +#define CS35L45_IRQ1_STS_7 0x0000E0A8 +#define CS35L45_IRQ1_STS_8 0x0000E0AC +#define CS35L45_IRQ1_STS_18 0x0000E0D4 +#define CS35L45_IRQ1_MASK_1 0x0000E110 +#define CS35L45_IRQ1_MASK_2 0x0000E114 +#define CS35L45_IRQ1_MASK_3 0x0000E118 +#define CS35L45_IRQ1_MASK_4 0x0000E11C +#define CS35L45_IRQ1_MASK_5 0x0000E120 +#define CS35L45_IRQ1_MASK_7 0x0000E128 +#define CS35L45_IRQ1_MASK_8 0x0000E12C +#define CS35L45_IRQ1_MASK_18 0x0000E154 +#define CS35L45_IRQ1_EDGE_1 0x0000E210 +#define CS35L45_IRQ1_EDGE_4 0x0000E21C +#define CS35L45_IRQ1_POL_1 0x0000E290 +#define CS35L45_IRQ1_POL_2 0x0000E294 +#define CS35L45_IRQ1_POL_4 0x0000E29C +#define CS35L45_IRQ1_DB_3 0x0000E318 +#define CS35L45_IRQ2_CFG 0x0000E800 +#define CS35L45_IRQ2_STATUS 0x0000E804 +#define CS35L45_IRQ2_EINT_1 0x0000E810 +#define CS35L45_IRQ2_EINT_2 0x0000E814 +#define CS35L45_IRQ2_EINT_3 0x0000E818 +#define CS35L45_IRQ2_EINT_4 0x0000E81C +#define CS35L45_IRQ2_EINT_5 0x0000E820 +#define CS35L45_IRQ2_EINT_7 0x0000E828 +#define CS35L45_IRQ2_EINT_8 0x0000E82C +#define CS35L45_IRQ2_EINT_18 0x0000E854 +#define CS35L45_IRQ2_STS_1 0x0000E890 +#define CS35L45_IRQ2_STS_2 0x0000E894 +#define CS35L45_IRQ2_STS_3 0x0000E898 +#define CS35L45_IRQ2_STS_4 0x0000E89C +#define CS35L45_IRQ2_STS_5 0x0000E8A0 +#define CS35L45_IRQ2_STS_7 0x0000E8A8 +#define CS35L45_IRQ2_STS_8 0x0000E8AC +#define CS35L45_IRQ2_STS_18 0x0000E8D4 +#define CS35L45_IRQ2_MASK_1 0x0000E910 +#define CS35L45_IRQ2_MASK_2 0x0000E914 +#define CS35L45_IRQ2_MASK_3 0x0000E918 +#define CS35L45_IRQ2_MASK_4 0x0000E91C +#define CS35L45_IRQ2_MASK_5 0x0000E920 +#define CS35L45_IRQ2_MASK_7 0x0000E928 +#define CS35L45_IRQ2_MASK_8 0x0000E92C +#define CS35L45_IRQ2_MASK_18 0x0000E954 +#define CS35L45_IRQ2_EDGE_1 0x0000EA10 +#define CS35L45_IRQ2_EDGE_4 0x0000EA1C +#define CS35L45_IRQ2_POL_1 0x0000EA90 +#define CS35L45_IRQ2_POL_2 0x0000EA94 +#define CS35L45_IRQ2_POL_4 0x0000EA9C +#define CS35L45_IRQ2_DB_3 0x0000EB18 +#define CS35L45_GPIO_STATUS1 0x0000F000 +#define CS35L45_GPIO1_CTRL1 0x0000F008 +#define CS35L45_GPIO2_CTRL1 0x0000F00C +#define CS35L45_GPIO3_CTRL1 0x0000F010 +#define CS35L45_MIXER_NGATE_CH1_CFG 0x00010004 +#define CS35L45_MIXER_NGATE_CH2_CFG 0x00010008 +#define CS35L45_DSP_MBOX_1 0x00011000 +#define CS35L45_DSP_MBOX_2 0x00011004 +#define CS35L45_DSP_MBOX_3 0x00011008 +#define CS35L45_DSP_MBOX_4 0x0001100C +#define CS35L45_DSP_MBOX_5 0x00011010 +#define CS35L45_DSP_MBOX_6 0x00011014 +#define CS35L45_DSP_MBOX_7 0x00011018 +#define CS35L45_DSP_MBOX_8 0x0001101C +#define CS35L45_DSP_VIRT1_MBOX_1 0x00011020 +#define CS35L45_DSP_VIRT1_MBOX_2 0x00011024 +#define CS35L45_DSP_VIRT1_MBOX_3 0x00011028 +#define CS35L45_DSP_VIRT1_MBOX_4 0x0001102C +#define CS35L45_DSP_VIRT1_MBOX_5 0x00011030 +#define CS35L45_DSP_VIRT1_MBOX_6 0x00011034 +#define CS35L45_DSP_VIRT1_MBOX_7 0x00011038 +#define CS35L45_DSP_VIRT1_MBOX_8 0x0001103C +#define CS35L45_DSP_VIRT2_MBOX_1 0x00011040 +#define CS35L45_DSP_VIRT2_MBOX_2 0x00011044 +#define CS35L45_DSP_VIRT2_MBOX_3 0x00011048 +#define CS35L45_DSP_VIRT2_MBOX_4 0x0001104C +#define CS35L45_DSP_VIRT2_MBOX_5 0x00011050 +#define CS35L45_DSP_VIRT2_MBOX_6 0x00011054 +#define CS35L45_DSP_VIRT2_MBOX_7 0x00011058 +#define CS35L45_DSP_VIRT2_MBOX_8 0x0001105C +#define CS35L45_CLOCK_DETECT_1 0x00012000 +#define CS35L45_DSP1_XMEM_PACK_0 0x02000000 +#define CS35L45_DSP1_XMEM_PACK_4607 0x020047FC +#define CS35L45_DSP1_XMEM_UNPACK32_0 0x02400000 +#define CS35L45_DSP1_XMEM_UNPACK32_3071 0x02402FFC +#define CS35L45_DSP1_SYS_ID 0x025E0000 +#define CS35L45_DSP1_XMEM_UNPACK24_0 0x02800000 +#define CS35L45_DSP1_XMEM_UNPACK24_6143 0x02805FFC +#define CS35L45_DSP1_CLOCK_FREQ 0x02B80000 +#define CS35L45_DSP1_RX1_RATE 0x02B80080 +#define CS35L45_DSP1_RX2_RATE 0x02B80088 +#define CS35L45_DSP1_RX3_RATE 0x02B80090 +#define CS35L45_DSP1_RX4_RATE 0x02B80098 +#define CS35L45_DSP1_RX5_RATE 0x02B800A0 +#define CS35L45_DSP1_RX6_RATE 0x02B800A8 +#define CS35L45_DSP1_RX7_RATE 0x02B800B0 +#define CS35L45_DSP1_RX8_RATE 0x02B800B8 +#define CS35L45_DSP1_TX1_RATE 0x02B80280 +#define CS35L45_DSP1_TX2_RATE 0x02B80288 +#define CS35L45_DSP1_TX3_RATE 0x02B80290 +#define CS35L45_DSP1_TX4_RATE 0x02B80298 +#define CS35L45_DSP1_TX5_RATE 0x02B802A0 +#define CS35L45_DSP1_TX6_RATE 0x02B802A8 +#define CS35L45_DSP1_TX7_RATE 0x02B802B0 +#define CS35L45_DSP1_TX8_RATE 0x02B802B8 +#define CS35L45_DSP1_SCRATCH1 0x02B805C0 +#define CS35L45_DSP1_SCRATCH2 0x02B805C8 +#define CS35L45_DSP1_SCRATCH3 0x02B805D0 +#define CS35L45_DSP1_SCRATCH4 0x02B805D8 +#define CS35L45_DSP1_CCM_CORE_CONTROL 0x02BC1000 +#define CS35L45_DSP1_STREAM_ARB_MSTR1_CONFIG_0 0x02BC5000 +#define CS35L45_DSP1_STREAM_ARB_TX1_CONFIG_0 0x02BC5200 +#define CS35L45_DSP1_YMEM_PACK_0 0x02C00000 +#define CS35L45_DSP1_YMEM_PACK_1532 0x02C017F0 +#define CS35L45_DSP1_YMEM_UNPACK32_0 0x03000000 +#define CS35L45_DSP1_YMEM_UNPACK32_1022 0x03000FF8 +#define CS35L45_DSP1_YMEM_UNPACK24_0 0x03400000 +#define CS35L45_DSP1_YMEM_UNPACK24_2043 0x03401FEC +#define CS35L45_DSP1_PMEM_0 0x03800000 +#define CS35L45_DSP1_PMEM_3834 0x03803BE8 +#define CS35L45_LASTREG 0x03C6EFE8 + +#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000 + +#define CS35L45_GLOBAL_EN_SHIFT 0 +#define CS35L45_GLOBAL_EN_MASK BIT(0) + +#define CS35L45_TEMPMON_GLOBAL_OVR_SHIFT 3 +#define CS35L45_TEMPMON_GLOBAL_OVR_MASK BIT(3) + +#define CS35L45_BST_DISABLE_FET_OFF 0x00 +#define CS35L45_BST_DISABLE_FET_ON 0x01 +#define CS35L45_BST_ENABLE 0x02 + +#define CS35L45_BST_EN_SHIFT 4 +#define CS35L45_BST_EN_MASK GENMASK(5, 4) + +#define CS35L45_AMP_DRE_EN_SHIFT 20 +#define CS35L45_AMP_DRE_EN_MASK BIT(20) +#define CS35L45_SYNC_EN_SHIFT 8 +#define CS35L45_SYNC_EN_MASK BIT(8) + +#define CS35L45_MEM_RDY_SHIFT 1 +#define CS35L45_MEM_RDY_MASK BIT(1) + +#define CS35L45_WKSRC_SYNC_GPIO1 BIT(0) +#define CS35L45_WKSRC_INT_GPIO2 BIT(1) +#define CS35L45_WKSRC_GPIO3 BIT(2) +#define CS35L45_WKSRC_SPI BIT(3) +#define CS35L45_WKSRC_I2C BIT(4) + +#define CS35L45_UPDT_WKCTL_SHIFT 15 +#define CS35L45_UPDT_WKCTL_MASK BIT(15) +#define CS35L45_WKSRC_EN_SHIFT 8 +#define CS35L45_WKSRC_EN_MASK GENMASK(12, 8) +#define CS35L45_WKSRC_POL_SHIFT 0 +#define CS35L45_WKSRC_POL_MASK GENMASK(3, 0) + +#define CS35L45_UPDT_WKI2C_SHIFT 15 +#define CS35L45_UPDT_WKI2C_MASK BIT(15) +#define CS35L45_WKI2C_ADDR_SHIFT 0 +#define CS35L45_WKI2C_ADDR_MASK GENMASK(6, 0) + +#define CS35L45_CCM_CORE_RESET_SHIFT 9 +#define CS35L45_CCM_CORE_RESET_MASK BIT(9) +#define CS35L45_CCM_PM_REMAP_SHIFT 7 +#define CS35L45_CCM_PM_REMAP_MASK BIT(7) +#define CS35L45_CCM_CORE_EN_SHIFT 0 +#define CS35L45_CCM_CORE_EN_MASK BIT(0) + +#define CS35L45_DSP1_STREAM_ARB_MSTR0_EN_SHIFT 0 +#define CS35L45_DSP1_STREAM_ARB_MSTR0_EN_MASK BIT(0) + +#define CS35L45_DSP1_STREAM_ARB_TX1_EN_SHIFT 0 +#define CS35L45_DSP1_STREAM_ARB_TX1_EN_MASK BIT(0) + +#define CS35L45_DSP_N_RX_RATES 8 +#define CS35L45_DSP_N_TX_RATES 8 +#define CS35L45_DSP_RATE_SHIFT 0 +#define CS35L45_DSP_RATE_MASK 0x1f +#define CS35L45_DSP_SAMPLE_RATE_RX1 0x00080 +#define CS35L45_DSP_SAMPLE_RATE_TX1 0x00280 + +#define CS35L45_48P0_KHZ 0x03 +#define CS35L45_96P0_KHZ 0x04 +#define CS35L45_44P100_KHZ 0x0B +#define CS35L45_88P200_KHZ 0x0C +#define CS35L45_8_KHZ 0x11 +#define CS35L45_16_KHZ 0x12 + +#define CS35L45_GLOBAL_FS_SHIFT 0 +#define CS35L45_GLOBAL_FS_MASK GENMASK(4, 0) + +#define CS35L45_SYNC_LSW_RX_EN_SHIFT 19 +#define CS35L45_SYNC_LSW_RX_EN_MASK BIT(19) +#define CS35L45_SYNC_LSW_TX_EN_SHIFT 18 +#define CS35L45_SYNC_LSW_TX_EN_MASK BIT(18) +#define CS35L45_SYNC_SW_RX_EN_SHIFT 17 +#define CS35L45_SYNC_SW_RX_EN_MASK BIT(17) +#define CS35L45_SYNC_SW_TX_EN_SHIFT 16 +#define CS35L45_SYNC_SW_TX_EN_MASK BIT(16) +#define CS35L45_SYNC_PWR_RX_EN_SHIFT 5 +#define CS35L45_SYNC_PWR_RX_EN_MASK BIT(5) +#define CS35L45_SYNC_PWR_TX_EN_SHIFT 4 +#define CS35L45_SYNC_PWR_TX_EN_MASK BIT(4) + +#define CS35L45_SYNC_SW_EN_MASK (CS35L45_SYNC_LSW_RX_EN_MASK | \ + CS35L45_SYNC_LSW_TX_EN_MASK | \ + CS35L45_SYNC_SW_RX_EN_MASK | \ + CS35L45_SYNC_SW_TX_EN_MASK) + +#define CS35L45_SYNC_LSW_TXID_SHIFT 8 +#define CS35L45_SYNC_LSW_TXID_MASK GENMASK(10, 8) +#define CS35L45_SYNC_SW_TXID_SHIFT 0 +#define CS35L45_SYNC_SW_TXID_MASK GENMASK(2, 0) + +#define CS35L45_PLL_REFCLK_SEL_BCLK 0x0 +#define CS35L45_PLL_REFCLK_SEL_SWIRE_CLK 0x7 + +#define CS35L45_PLL_FORCE_EN_SHIFT 16 +#define CS35L45_PLL_FORCE_EN_MASK BIT(16) +#define CS35L45_PLL_OPEN_LOOP_SHIFT 11 +#define CS35L45_PLL_OPEN_LOOP_MASK BIT(11) +#define CS35L45_PLL_REFCLK_FREQ_SHIFT 5 +#define CS35L45_PLL_REFCLK_FREQ_MASK GENMASK(10, 5) +#define CS35L45_PLL_REFCLK_EN_SHIFT 4 +#define CS35L45_PLL_REFCLK_EN_MASK BIT(4) +#define CS35L45_PLL_REFCLK_SEL_SHIFT 0 +#define CS35L45_PLL_REFCLK_SEL_MASK GENMASK(2, 0) + +#define CS35L45_BST_BPE_INST_L3_THLD_SHIFT 24 +#define CS35L45_BST_BPE_INST_L3_THLD_MASK GENMASK(31, 24) +#define CS35L45_BST_BPE_INST_L2_THLD_SHIFT 16 +#define CS35L45_BST_BPE_INST_L2_THLD_MASK GENMASK(23, 16) +#define CS35L45_BST_BPE_INST_L1_THLD_SHIFT 8 +#define CS35L45_BST_BPE_INST_L1_THLD_MASK GENMASK(15, 8) +#define CS35L45_BST_BPE_INST_L0_THLD_SHIFT 0 +#define CS35L45_BST_BPE_INST_L0_THLD_MASK GENMASK(7, 0) + +#define CS35L45_BST_BPE_INST_L4_ILIM_SHIFT 24 +#define CS35L45_BST_BPE_INST_L4_ILIM_MASK GENMASK(30, 24) +#define CS35L45_BST_BPE_INST_L3_ILIM_SHIFT 16 +#define CS35L45_BST_BPE_INST_L3_ILIM_MASK GENMASK(22, 16) +#define CS35L45_BST_BPE_INST_L2_ILIM_SHIFT 8 +#define CS35L45_BST_BPE_INST_L2_ILIM_MASK GENMASK(14, 8) +#define CS35L45_BST_BPE_INST_L1_ILIM_SHIFT 0 +#define CS35L45_BST_BPE_INST_L1_ILIM_MASK GENMASK(6, 0) + +#define CS35L45_BST_BPE_INST_L4_SS_ILIM_SHIFT 24 +#define CS35L45_BST_BPE_INST_L4_SS_ILIM_MASK GENMASK(30, 24) +#define CS35L45_BST_BPE_INST_L3_SS_ILIM_SHIFT 16 +#define CS35L45_BST_BPE_INST_L3_SS_ILIM_MASK GENMASK(22, 16) +#define CS35L45_BST_BPE_INST_L2_SS_ILIM_SHIFT 8 +#define CS35L45_BST_BPE_INST_L2_SS_ILIM_MASK GENMASK(14, 8) +#define CS35L45_BST_BPE_INST_L1_SS_ILIM_SHIFT 0 +#define CS35L45_BST_BPE_INST_L1_SS_ILIM_MASK GENMASK(6, 0) + +#define CS35L45_BST_BPE_INST_L3_ATK_RATE_SHIFT 24 +#define CS35L45_BST_BPE_INST_L3_ATK_RATE_MASK GENMASK(26, 24) +#define CS35L45_BST_BPE_INST_L2_ATK_RATE_SHIFT 16 +#define CS35L45_BST_BPE_INST_L2_ATK_RATE_MASK GENMASK(18, 16) +#define CS35L45_BST_BPE_INST_L1_ATK_RATE_SHIFT 8 +#define CS35L45_BST_BPE_INST_L1_ATK_RATE_MASK GENMASK(10, 8) + +#define CS35L45_BST_BPE_INST_L3_HOLD_TIME_SHIFT 24 +#define CS35L45_BST_BPE_INST_L3_HOLD_TIME_MASK GENMASK(27, 24) +#define CS35L45_BST_BPE_INST_L2_HOLD_TIME_SHIFT 16 +#define CS35L45_BST_BPE_INST_L2_HOLD_TIME_MASK GENMASK(19, 16) +#define CS35L45_BST_BPE_INST_L1_HOLD_TIME_SHIFT 8 +#define CS35L45_BST_BPE_INST_L1_HOLD_TIME_MASK GENMASK(11, 8) +#define CS35L45_BST_BPE_INST_L0_HOLD_TIME_SHIFT 0 +#define CS35L45_BST_BPE_INST_L0_HOLD_TIME_MASK GENMASK(3, 0) + +#define CS35L45_BST_BPE_INST_L3_RLS_RATE_SHIFT 24 +#define CS35L45_BST_BPE_INST_L3_RLS_RATE_MASK GENMASK(28, 24) +#define CS35L45_BST_BPE_INST_L2_RLS_RATE_SHIFT 16 +#define CS35L45_BST_BPE_INST_L2_RLS_RATE_MASK GENMASK(20, 16) +#define CS35L45_BST_BPE_INST_L1_RLS_RATE_SHIFT 8 +#define CS35L45_BST_BPE_INST_L1_RLS_RATE_MASK GENMASK(12, 8) +#define CS35L45_BST_BPE_INST_L0_RLS_RATE_SHIFT 0 +#define CS35L45_BST_BPE_INST_L0_RLS_RATE_MASK GENMASK(4, 0) + +#define CS35L45_BST_BPE_INST_INF_HOLD_RLS_SHIFT 16 +#define CS35L45_BST_BPE_INST_INF_HOLD_RLS_MASK BIT(16) +#define CS35L45_BST_BPE_IL_LIM_MODE_SHIFT 15 +#define CS35L45_BST_BPE_IL_LIM_MODE_MASK BIT(15) +#define CS35L45_BST_BPE_OUT_OPMODE_SEL_SHIFT 12 +#define CS35L45_BST_BPE_OUT_OPMODE_SEL_MASK GENMASK(13, 12) +#define CS35L45_BST_BPE_INST_L3_BYP_SHIFT 10 +#define CS35L45_BST_BPE_INST_L3_BYP_MASK BIT(10) +#define CS35L45_BST_BPE_INST_L2_BYP_SHIFT 9 +#define CS35L45_BST_BPE_INST_L2_BYP_MASK BIT(9) +#define CS35L45_BST_BPE_INST_L1_BYP_SHIFT 8 +#define CS35L45_BST_BPE_INST_L1_BYP_MASK BIT(8) +#define CS35L45_BST_BPE_FILT_SEL_SHIFT 0 +#define CS35L45_BST_BPE_FILT_SEL_MASK GENMASK(1, 0) + +#define CS35L45_BST_BPE_IL_LIM_THLD_HYST_SHIFT 24 +#define CS35L45_BST_BPE_IL_LIM_THLD_HYST_MASK GENMASK(28, 24) +#define CS35L45_BST_BPE_IL_LIM_THLD_DEL2_SHIFT 16 +#define CS35L45_BST_BPE_IL_LIM_THLD_DEL2_MASK GENMASK(23, 16) +#define CS35L45_BST_BPE_IL_LIM_THLD_DEL1_SHIFT 8 +#define CS35L45_BST_BPE_IL_LIM_THLD_DEL1_MASK GENMASK(15, 8) +#define CS35L45_BST_BPE_IL_LIM1_THLD_SHIFT 0 +#define CS35L45_BST_BPE_IL_LIM1_THLD_MASK GENMASK(7, 0) + +#define CS35L45_BST_BPE_IL_LIM_DLY_HYST_SHIFT 16 +#define CS35L45_BST_BPE_IL_LIM_DLY_HYST_MASK GENMASK(22, 16) +#define CS35L45_BST_BPE_IL_LIM2_DLY_SHIFT 8 +#define CS35L45_BST_BPE_IL_LIM2_DLY_MASK GENMASK(15, 8) +#define CS35L45_BST_BPE_IL_LIM1_DLY_SHIFT 0 +#define CS35L45_BST_BPE_IL_LIM1_DLY_MASK GENMASK(7, 0) + +#define CS35L45_BST_BPE_IL_LIM2_ATK_RATE_SHIFT 8 +#define CS35L45_BST_BPE_IL_LIM2_ATK_RATE_MASK GENMASK(10, 8) +#define CS35L45_BST_BPE_IL_LIM1_ATK_RATE_SHIFT 0 +#define CS35L45_BST_BPE_IL_LIM1_ATK_RATE_MASK GENMASK(2, 0) + +#define CS35L45_BST_BPE_IL_LIM2_RLS_RATE_SHIFT 8 +#define CS35L45_BST_BPE_IL_LIM2_RLS_RATE_MASK GENMASK(12, 8) +#define CS35L45_BST_BPE_IL_LIM1_RLS_RATE_SHIFT 0 +#define CS35L45_BST_BPE_IL_LIM1_RLS_RATE_MASK GENMASK(4, 0) + +#define CS35L45_ASP_WIDTH_16 0x10 +#define CS35L45_ASP_WIDTH_24 0x18 +#define CS35L45_ASP_WIDTH_32 0x20 + +#define CS35L45_ASP_WIDTH_RX_SHIFT 24 +#define CS35L45_ASP_WIDTH_RX_MASK GENMASK(31, 24) +#define CS35L45_ASP_WIDTH_TX_SHIFT 16 +#define CS35L45_ASP_WIDTH_TX_MASK GENMASK(23, 16) +#define CS35L45_ASP_FMT_SHIFT 8 +#define CS35L45_ASP_FMT_MASK GENMASK(10, 8) +#define CS35L45_ASP_BCLK_INV_SHIFT 6 +#define CS35L45_ASP_BCLK_INV_MASK BIT(6) +#define CS35L45_ASP_BCLK_MSTR_SHIFT 4 +#define CS35L45_ASP_BCLK_MSTR_MASK BIT(4) +#define CS35L45_ASP_FSYNC_INV_SHIFT 2 +#define CS35L45_ASP_FSYNC_INV_MASK BIT(2) +#define CS35L45_ASP_FSYNC_MSTR_SHIFT 0 +#define CS35L45_ASP_FSYNC_MSTR_MASK BIT(0) + +#define CS35L45_ASP_WL_MAX 24 +#define CS35L45_ASP_WL_MIN 12 + +#define CS35L45_ASP_WL_SHIFT 0 +#define CS35L45_ASP_WL_MASK GENMASK(5, 0) + +#define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT 0 +#define CS35L45_ASP_DOUT_HIZ_CTRL_MASK GENMASK(1, 0) + +#define CS35L45_ASP_TX4_SLOT_SHIFT 24 +#define CS35L45_ASP_TX4_SLOT_MASK GENMASK(29, 24) +#define CS35L45_ASP_TX3_SLOT_SHIFT 16 +#define CS35L45_ASP_TX3_SLOT_MASK GENMASK(21, 16) +#define CS35L45_ASP_TX2_SLOT_SHIFT 8 +#define CS35L45_ASP_TX2_SLOT_MASK GENMASK(13, 8) +#define CS35L45_ASP_TX1_SLOT_SHIFT 0 +#define CS35L45_ASP_TX1_SLOT_MASK GENMASK(5, 0) + +#define CS35L45_ASP_TX_ALL_SLOTS (CS35L45_ASP_TX4_SLOT_MASK | \ + CS35L45_ASP_TX3_SLOT_MASK | \ + CS35L45_ASP_TX2_SLOT_MASK | \ + CS35L45_ASP_TX1_SLOT_MASK) + +#define CS35L45_ASP_RX2_SLOT_SHIFT 8 +#define CS35L45_ASP_RX2_SLOT_MASK GENMASK(13, 8) +#define CS35L45_ASP_RX1_SLOT_SHIFT 0 +#define CS35L45_ASP_RX1_SLOT_MASK GENMASK(5, 0) + +#define CS35L45_ASP_RX_ALL_SLOTS (CS35L45_ASP_RX2_SLOT_MASK | \ + CS35L45_ASP_RX1_SLOT_MASK) + +#define CS35L45_PCM_SRC_MASK 0x7F +#define CS35L45_PCM_SRC_ZERO 0x00 +#define CS35L45_PCM_SRC_ASP_RX1 0x08 +#define CS35L45_PCM_SRC_ASP_RX2 0x09 +#define CS35L45_PCM_SRC_VMON 0x18 +#define CS35L45_PCM_SRC_IMON 0x19 +#define CS35L45_PCM_SRC_ERR_VOL 0x20 +#define CS35L45_PCM_SRC_CLASSH_TGT 0x21 +#define CS35L45_PCM_SRC_VDD_BATTMON 0x28 +#define CS35L45_PCM_SRC_VDD_BSTMON 0x29 +#define CS35L45_PCM_SRC_DSP_TX1 0x32 +#define CS35L45_PCM_SRC_DSP_TX2 0x33 +#define CS35L45_PCM_SRC_TEMPMON 0x3A +#define CS35L45_PCM_SRC_SWIRE_RX1 0x44 +#define CS35L45_PCM_SRC_SWIRE_RX2 0x45 + +#define CS35L45_FORCE_LV_OPERATION 0x01 +#define CS35L45_FORCE_HV_OPERATION 0x02 +#define CS35L45_HVLV_OPERATION 0x03 + +#define CS35L45_HVLV_THLD_HYS_SHIFT 22 +#define CS35L45_HVLV_THLD_HYS_MASK GENMASK(23, 22) +#define CS35L45_HVLV_THLD_SHIFT 16 +#define CS35L45_HVLV_THLD_MASK GENMASK(20, 16) +#define CS35L45_HVLV_DLY_SHIFT 2 +#define CS35L45_HVLV_DLY_MASK GENMASK(4, 2) +#define CS35L45_HVLV_MODE_SHIFT 0 +#define CS35L45_HVLV_MODE_MASK GENMASK(1, 0) + +#define CS35L45_LDPM_GP1_BOOST_SEL_SHIFT 15 +#define CS35L45_LDPM_GP1_BOOST_SEL_MASK BIT(15) +#define CS35L45_LDPM_GP1_AMP_SEL_SHIFT 14 +#define CS35L45_LDPM_GP1_AMP_SEL_MASK BIT(14) +#define CS35L45_LDPM_GP1_DELAY_SHIFT 11 +#define CS35L45_LDPM_GP1_DELAY_MASK GENMASK(13, 11) +#define CS35L45_LDPM_GP1_PCM_THLD_SHIFT 8 +#define CS35L45_LDPM_GP1_PCM_THLD_MASK GENMASK(10, 8) +#define CS35L45_LDPM_GP2_IMON_SEL_SHIFT 7 +#define CS35L45_LDPM_GP2_IMON_SEL_MASK BIT(7) +#define CS35L45_LDPM_GP2_VMON_SEL_SHIFT 6 +#define CS35L45_LDPM_GP2_VMON_SEL_MASK BIT(6) +#define CS35L45_LDPM_GP2_DELAY_SHIFT 3 +#define CS35L45_LDPM_GP2_DELAY_MASK GENMASK(5, 3) +#define CS35L45_LDPM_GP2_PCM_THLD_SHIFT 0 +#define CS35L45_LDPM_GP2_PCM_THLD_MASK GENMASK(2, 0) + +#define CS35L45_CH_HDRM_SHIFT 24 +#define CS35L45_CH_HDRM_MASK GENMASK(30, 24) +#define CS35L45_CH_RATIO_SHIFT 8 +#define CS35L45_CH_RATIO_MASK GENMASK(12, 8) +#define CS35L45_CH_REL_RATE_SHIFT 0 +#define CS35L45_CH_REL_RATE_MASK GENMASK(7, 0) + +#define CS35L45_CH_OVB_THLD1_SHIFT 16 +#define CS35L45_CH_OVB_THLD1_MASK GENMASK(23, 16) +#define CS35L45_CH_OVB_THLDDELTA_SHIFT 8 +#define CS35L45_CH_OVB_THLDDELTA_MASK GENMASK(15, 8) +#define CS35L45_CH_VDD_BST_MAX_SHIFT 0 +#define CS35L45_CH_VDD_BST_MAX_MASK GENMASK(7, 0) + +#define CS35L45_CH_OVB_LATCH_SHIFT 31 +#define CS35L45_CH_OVB_LATCH_MASK BIT(31) +#define CS35L45_CH_OVB_RATIO_SHIFT 16 +#define CS35L45_CH_OVB_RATIO_MASK GENMASK(20, 16) +#define CS35L45_CH_THLD1_OFFSET_SHIFT 0 +#define CS35L45_CH_THLD1_OFFSET_MASK GENMASK(11, 0) + +#define CS35L45_AUD_MEM_DEPTH_SHIFT 0 +#define CS35L45_AUD_MEM_DEPTH_MASK GENMASK(2, 0) + +#define CS35l45_HPF_DEFAULT 0x00000000 +#define CS35L45_HPF_44P1 0x000108BD +#define CS35L45_HPF_88P2 0x0001045F + +#define CS35L45_AMP_VOL_PCM_MUTE 0x04CF + +#define CS35L45_AMP_VOL_PCM_SHIFT 0 +#define CS35L45_AMP_VOL_PCM_MASK GENMASK(10, 0) + +#define CS35L45_AMP_GAIN_PCM_10DBV 0x00 +#define CS35L45_AMP_GAIN_PCM_13DBV 0x01 +#define CS35L45_AMP_GAIN_PCM_16DBV 0x02 +#define CS35L45_AMP_GAIN_PCM_19DBV 0x03 + +#define CS35L45_AMP_GAIN_PCM_SHIFT 8 +#define CS35L45_AMP_GAIN_PCM_MASK GENMASK(9, 8) + +#define CS35L45_AMP_MUTE_SHIFT 0 +#define CS35L45_AMP_MUTE_MASK BIT(0) + +#define CS35L45_AMP_SHORT_ERR_MASK BIT(31) +#define CS35L45_BST_SHORT_ERR_MASK BIT(8) + +#define CS35L45_MSM_PUP_DONE_MASK BIT(24) +#define CS35L45_MSM_PDN_DONE_MASK BIT(23) +#define CS35L45_MSM_GLOBAL_EN_ASSERT_MASK BIT(22) + +#define CS35L45_DSP_VIRT1_MBOX_MASK BIT(20) +#define CS35L45_DSP_VIRT2_MBOX_MASK BIT(21) + +#define CS35L45_PLL_UNLOCK_FLAG_RISE_MASK BIT(4) +#define CS35L45_PLL_LOCK_FLAG_MASK BIT(1) + +#define CS35L45_OTP_BOOT_DONE_STS_MASK BIT(1) +#define CS35L45_OTP_BUSY_MASK BIT(0) + +#define CS35L45_GLOBAL_ERROR_MASK BIT(15) + +#define CS35L45_GPIO_DIR_SHIFT 31 +#define CS35L45_GPIO_DIR_MASK BIT(31) +#define CS35L45_GPIO_LVL_SHIFT 15 +#define CS35L45_GPIO_LVL_MASK BIT(15) +#define CS35L45_GPIO_OP_CFG_SHIFT 14 +#define CS35L45_GPIO_OP_CFG_MASK BIT(14) +#define CS35L45_GPIO_POL_SHIFT 12 +#define CS35L45_GPIO_POL_MASK BIT(12) + +#define CS35L45_GPIO_CTRL_SHIFT 20 +#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20) +#define CS35L45_GPIO_INVERT_SHIFT 19 +#define CS35L45_GPIO_INVERT_MASK BIT(19) + +#define CS35L45_AUX_NGATE_CH_EN_SHIFT 16 +#define CS35L45_AUX_NGATE_CH_EN_MASK BIT(16) +#define CS35L45_AUX_NGATE_CH_HOLD_SHIFT 8 +#define CS35L45_AUX_NGATE_CH_HOLD_MASK GENMASK(11, 8) +#define CS35L45_AUX_NGATE_CH_THR_SHIFT 0 +#define CS35L45_AUX_NGATE_CH_THR_MASK GENMASK(2, 0) + +#define CS35L45_AUX_NGATE_CH_HOLD_DEFAULT 0x03 +#define CS35L45_AUX_NGATE_CH_THR_DEFAULT 0x03 + +#define CS35L45_MAX_CACHE_REG 0x0000006B +#define CS35L45_MAX_PLL_CONFIGS 64 +#define CS35L45_REGSTRIDE 4 +#define CS35L45_VALID_PDATA 0x80000000 +#define CS35L45_DEFAULT_SLOT_WIDTH 32 +#define CS35L45_BUFSIZE 64 +#define CS35L45_ALGID 0xCD +#define CS35L45_ALGID_MDSYNC 0xF20A + +struct cs35l45_private; + +struct cs35l45_pll_sysclk_config { + int freq; + int clk_cfg; +}; + +enum cspl_mboxstate { + CSPL_MBOX_STS_RUNNING = 0, + CSPL_MBOX_STS_PAUSED = 1, + CSPL_MBOX_STS_RDY_FOR_REINIT = 2, + CSPL_MBOX_STS_HIBERNATE = 3, + CSPL_MBOX_STS_RECONFIGURING = 4, +}; + +enum cspl_mboxcmd { + CSPL_MBOX_CMD_NONE = 0, + CSPL_MBOX_CMD_PAUSE = 1, + CSPL_MBOX_CMD_RESUME = 2, + CSPL_MBOX_CMD_REINIT = 3, + CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, + CSPL_MBOX_CMD_HIBERNATE = 5, + CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, + CSPL_MBOX_CMD_PREPARE_RECONFIGURATION = 7, + CSPL_MBOX_CMD_APPLY_RECONFIGURATION = 8, + CSPL_MBOX_CMD_UNKNOWN_CMD = -1, + CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, +}; + +enum cspl_cmd { + CSPL_CMD_NONE = 0, + CSPL_CMD_MUTE = 1, + CSPL_CMD_UNMUTE = 2, + CSPL_CMD_UPDATE_PARAM = 8, +}; + +enum cspl_st { + CSPL_ST_RUNNING = 0, + CSPL_ST_ERROR = 1, + CSPL_ST_MUTED = 2, + CSPL_ST_REINITING = 3, + CSPL_ST_DIAGNOSING = 6, +}; + +enum pcm_mixers { + ASP_TX1 = 0, + ASP_TX2, + ASP_TX3, + ASP_TX4, + DSP_RX1, + DSP_RX2, + DSP_RX3, + DSP_RX4, + DSP_RX5, + DSP_RX6, + DSP_RX7, + DSP_RX8, + DACPCM, + NGATE1, + NGATE2, +}; + +enum amp_mode { + AMP_MODE_SPK = 0, + AMP_MODE_RCV = 1, +}; + +enum hiber_mode { + HIBER_MODE_DIS = 0, + HIBER_MODE_EN = 1, +}; + +enum dapm_route_mode { + DAPM_MODE_ASP = 0, + DAPM_MODE_DSP_SLAVE = 1, + DAPM_MODE_DSP_MASTER = 2, +}; + +bool cs35l45_readable_reg(struct device *dev, unsigned int reg); +bool cs35l45_volatile_reg(struct device *dev, unsigned int reg); +bool cs35l45_precious_reg(struct device *dev, unsigned int reg); +int cs35l45_set_csplmboxcmd(struct cs35l45_private *cs35l45, + enum cspl_mboxcmd cmd); + +extern const struct reg_default cs35l45_reg[CS35L45_MAX_CACHE_REG]; +extern const struct cs35l45_pll_sysclk_config + cs35l45_pll_sysclk[CS35L45_MAX_PLL_CONFIGS]; + +#endif /*__CS35L45_H__*/ diff --git a/techpack/audio/asoc/codecs/cs35l45/cs35l45_user.h b/techpack/audio/asoc/codecs/cs35l45/cs35l45_user.h new file mode 100644 index 0000000000000..74807b9a40215 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/cs35l45_user.h @@ -0,0 +1,439 @@ +/* + * linux/sound/cs35l45.h -- Platform data for CS35L45 + * + * Copyright 2019 Cirrus Logic, Inc. + * + * Author: James Schulman + * + */ + +#ifndef __CS35L45_USER_H +#define __CS35L45_USER_H + +#define CS35L45_NUM_SUPPLIES 2 + +struct bst_bpe_inst_lvl_config { + unsigned int thld; + unsigned int ilim; + unsigned int ss_ilim; + unsigned int atk_rate; + unsigned int hold_time; + unsigned int rls_rate; +}; + +struct bst_bpe_inst_config { + bool is_present; + struct bst_bpe_inst_lvl_config l0; + struct bst_bpe_inst_lvl_config l1; + struct bst_bpe_inst_lvl_config l2; + struct bst_bpe_inst_lvl_config l3; + struct bst_bpe_inst_lvl_config l4; +}; + +struct bst_bpe_misc_config { + bool is_present; + unsigned int bst_bpe_inst_inf_hold_rls; + unsigned int bst_bpe_il_lim_mode; + unsigned int bst_bpe_out_opmode_sel; + unsigned int bst_bpe_inst_l3_byp; + unsigned int bst_bpe_inst_l2_byp; + unsigned int bst_bpe_inst_l1_byp; + unsigned int bst_bpe_filt_sel; +}; + +struct bst_bpe_il_lim_config { + bool is_present; + unsigned int bst_bpe_il_lim_thld_del1; + unsigned int bst_bpe_il_lim_thld_del2; + unsigned int bst_bpe_il_lim1_thld; + unsigned int bst_bpe_il_lim1_dly; + unsigned int bst_bpe_il_lim2_dly; + unsigned int bst_bpe_il_lim_dly_hyst; + unsigned int bst_bpe_il_lim_thld_hyst; + unsigned int bst_bpe_il_lim1_atk_rate; + unsigned int bst_bpe_il_lim2_atk_rate; + unsigned int bst_bpe_il_lim1_rls_rate; + unsigned int bst_bpe_il_lim2_rls_rate; +}; + +struct hvlv_config { + bool is_present; + unsigned int hvlv_thld_hys; + unsigned int hvlv_thld; + unsigned int hvlv_dly; +}; + +struct ldpm_config { + bool is_present; + unsigned int ldpm_gp1_boost_sel; + unsigned int ldpm_gp1_amp_sel; + unsigned int ldpm_gp1_delay; + unsigned int ldpm_gp1_pcm_thld; + unsigned int ldpm_gp2_imon_sel; + unsigned int ldpm_gp2_vmon_sel; + unsigned int ldpm_gp2_delay; + unsigned int ldpm_gp2_pcm_thld; +}; + +struct classh_config { + bool is_present; + unsigned int ch_hdrm; + unsigned int ch_ratio; + unsigned int ch_rel_rate; + unsigned int ch_ovb_thld1; + unsigned int ch_ovb_thlddelta; + unsigned int ch_vdd_bst_max; + unsigned int ch_ovb_ratio; + unsigned int ch_thld1_offset; + unsigned int aud_mem_depth; +}; + +struct gpio_ctrl { + bool is_present; + unsigned int dir; + unsigned int lvl; + unsigned int op_cfg; + unsigned int pol; + unsigned int ctrl; + unsigned int invert; +}; + +struct cs35l45_irq_monitor { + unsigned int reg; + unsigned int mask; + unsigned int bitmask; + const char *description; + const char *err_msg; + int (*callback)(struct cs35l45_private *cs35l45); +}; + +struct cs35l45_platform_data { + struct bst_bpe_inst_config bst_bpe_inst_cfg; + struct bst_bpe_misc_config bst_bpe_misc_cfg; + struct bst_bpe_il_lim_config bst_bpe_il_lim_cfg; + struct hvlv_config hvlv_cfg; + struct ldpm_config ldpm_cfg; + struct classh_config classh_cfg; + struct gpio_ctrl gpio_ctrl1; + struct gpio_ctrl gpio_ctrl2; + struct gpio_ctrl gpio_ctrl3; + const char *dsp_part_name; + unsigned int asp_sdout_hiz_ctrl; + unsigned int ngate_ch1_hold; + unsigned int ngate_ch1_thr; + unsigned int ngate_ch2_hold; + unsigned int ngate_ch2_thr; + bool use_tdm_slots; +}; + +struct cs35l45_private { + struct wm_adsp dsp; /* needs to be first member */ + struct device *dev; + struct regmap *regmap; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[CS35L45_NUM_SUPPLIES]; + struct cs35l45_platform_data pdata; + struct work_struct dsp_pmd_work; + struct mutex rate_lock; + struct mutex dsp_pmd_lock; + enum dapm_route_mode dapm_mode; + bool initialized; + bool fast_switch_en; + unsigned int wksrc; + unsigned int i2c_addr; + unsigned int sync_num_devices; + unsigned int sync_id; + int irq; + int slot_width; + int amplifier_mode; + int hibernate_mode; + /* Run-time mixer */ + struct snd_kcontrol_new fast_ctl; + unsigned int fast_switch_file_idx; + struct soc_enum fast_switch_enum; + const char **fast_switch_names; + /* Downstream specific */ + unsigned int dig_vol; + int dsp1_enable_pin; + unsigned int global_err_rls; +}; + +int cs35l45_initialize(struct cs35l45_private *cs35l45); +int cs35l45_probe(struct cs35l45_private *cs35l45); +int cs35l45_remove(struct cs35l45_private *cs35l45); + +struct of_entry { + const char *name; + unsigned int reg; + unsigned int mask; + unsigned int shift; +}; + +enum bst_bpe_inst_level { + L0 = 0, + L1, + L2, + L3, + L4, + BST_BPE_INST_LEVELS +}; + +enum bst_bpe_inst_of_param { + BST_BPE_INST_THLD = 0, + BST_BPE_INST_ILIM, + BST_BPE_INST_SS_ILIM, + BST_BPE_INST_ATK_RATE, + BST_BPE_INST_HOLD_TIME, + BST_BPE_INST_RLS_RATE, + BST_BPE_INST_PARAMS +}; + +enum bst_bpe_misc_of_param { + BST_BPE_INST_INF_HOLD_RLS = 0, + BST_BPE_IL_LIM_MODE, + BST_BPE_OUT_OPMODE_SEL, + BST_BPE_INST_L3_BYP, + BST_BPE_INST_L2_BYP, + BST_BPE_INST_L1_BYP, + BST_BPE_FILT_SEL, + BST_BPE_MISC_PARAMS +}; + +enum bst_bpe_il_lim_of_param { + BST_BPE_IL_LIM_THLD_DEL1 = 0, + BST_BPE_IL_LIM_THLD_DEL2, + BST_BPE_IL_LIM1_THLD, + BST_BPE_IL_LIM1_DLY, + BST_BPE_IL_LIM2_DLY, + BST_BPE_IL_LIM_DLY_HYST, + BST_BPE_IL_LIM_THLD_HYST, + BST_BPE_IL_LIM1_ATK_RATE, + BST_BPE_IL_LIM2_ATK_RATE, + BST_BPE_IL_LIM1_RLS_RATE, + BST_BPE_IL_LIM2_RLS_RATE, + BST_BPE_IL_LIM_PARAMS +}; + +enum ldpm_of_param { + LDPM_GP1_BOOST_SEL = 0, + LDPM_GP1_AMP_SEL, + LDPM_GP1_DELAY, + LDPM_GP1_PCM_THLD, + LDPM_GP2_IMON_SEL, + LDPM_GP2_VMON_SEL, + LDPM_GP2_DELAY, + LDPM_GP2_PCM_THLD, + LDPM_PARAMS +}; + +enum classh_of_param { + CH_HDRM = 0, + CH_RATIO, + CH_REL_RATE, + CH_OVB_THLD1, + CH_OVB_THLDDELTA, + CH_VDD_BST_MAX, + CH_OVB_RATIO, + CH_THLD1_OFFSET, + AUD_MEM_DEPTH, + CLASSH_PARAMS +}; + +extern const struct of_entry bst_bpe_inst_thld_map[BST_BPE_INST_LEVELS]; +extern const struct of_entry bst_bpe_inst_ilim_map[BST_BPE_INST_LEVELS]; +extern const struct of_entry bst_bpe_inst_ss_ilim_map[BST_BPE_INST_LEVELS]; +extern const struct of_entry bst_bpe_inst_atk_rate_map[BST_BPE_INST_LEVELS]; +extern const struct of_entry bst_bpe_inst_hold_time_map[BST_BPE_INST_LEVELS]; +extern const struct of_entry bst_bpe_inst_rls_rate_map[BST_BPE_INST_LEVELS]; +extern const struct of_entry bst_bpe_misc_map[BST_BPE_MISC_PARAMS]; +extern const struct of_entry bst_bpe_il_lim_map[BST_BPE_IL_LIM_PARAMS]; +extern const struct of_entry ldpm_map[LDPM_PARAMS]; +extern const struct of_entry classh_map[CLASSH_PARAMS]; + +static inline const struct of_entry *cs35l45_get_bst_bpe_inst_entry( + enum bst_bpe_inst_level level, + enum bst_bpe_inst_of_param param) +{ + if ((level < L0) || (level > L4)) + return NULL; + + switch (param) { + case BST_BPE_INST_THLD: + return &bst_bpe_inst_thld_map[level]; + case BST_BPE_INST_ILIM: + return &bst_bpe_inst_ilim_map[level]; + case BST_BPE_INST_SS_ILIM: + return &bst_bpe_inst_ss_ilim_map[level]; + case BST_BPE_INST_ATK_RATE: + return &bst_bpe_inst_atk_rate_map[level]; + case BST_BPE_INST_HOLD_TIME: + return &bst_bpe_inst_hold_time_map[level]; + case BST_BPE_INST_RLS_RATE: + return &bst_bpe_inst_rls_rate_map[level]; + default: + return NULL; + } +} + +static inline u32 *cs35l45_get_bst_bpe_inst_param( + struct cs35l45_private *cs35l45, + enum bst_bpe_inst_level level, + enum bst_bpe_inst_of_param param) +{ + struct bst_bpe_inst_lvl_config *cfg; + + switch (level) { + case L0: + cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l0; + break; + case L1: + cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l1; + break; + case L2: + cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l2; + break; + case L3: + cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l3; + break; + case L4: + cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l4; + break; + default: + return NULL; + } + + switch (param) { + case BST_BPE_INST_THLD: + return &cfg->thld; + case BST_BPE_INST_ILIM: + return &cfg->ilim; + case BST_BPE_INST_SS_ILIM: + return &cfg->ss_ilim; + case BST_BPE_INST_ATK_RATE: + return &cfg->atk_rate; + case BST_BPE_INST_HOLD_TIME: + return &cfg->hold_time; + case BST_BPE_INST_RLS_RATE: + return &cfg->rls_rate; + default: + return NULL; + } +} + +static inline u32 *cs35l45_get_bst_bpe_misc_param( + struct cs35l45_private *cs35l45, + enum bst_bpe_misc_of_param param) +{ + struct bst_bpe_misc_config *cfg = &cs35l45->pdata.bst_bpe_misc_cfg; + + switch (param) { + case BST_BPE_INST_INF_HOLD_RLS: + return &cfg->bst_bpe_inst_inf_hold_rls; + case BST_BPE_IL_LIM_MODE: + return &cfg->bst_bpe_il_lim_mode; + case BST_BPE_OUT_OPMODE_SEL: + return &cfg->bst_bpe_out_opmode_sel; + case BST_BPE_INST_L3_BYP: + return &cfg->bst_bpe_inst_l3_byp; + case BST_BPE_INST_L2_BYP: + return &cfg->bst_bpe_inst_l2_byp; + case BST_BPE_INST_L1_BYP: + return &cfg->bst_bpe_inst_l1_byp; + case BST_BPE_FILT_SEL: + return &cfg->bst_bpe_filt_sel; + default: + return NULL; + } +} + +static inline u32 *cs35l45_get_bst_bpe_il_lim_param( + struct cs35l45_private *cs35l45, + enum bst_bpe_il_lim_of_param param) +{ + struct bst_bpe_il_lim_config *cfg = &cs35l45->pdata.bst_bpe_il_lim_cfg; + + switch (param) { + case BST_BPE_IL_LIM_THLD_DEL1: + return &cfg->bst_bpe_il_lim_thld_del1; + case BST_BPE_IL_LIM_THLD_DEL2: + return &cfg->bst_bpe_il_lim_thld_del2; + case BST_BPE_IL_LIM1_THLD: + return &cfg->bst_bpe_il_lim1_thld; + case BST_BPE_IL_LIM1_DLY: + return &cfg->bst_bpe_il_lim1_dly; + case BST_BPE_IL_LIM2_DLY: + return &cfg->bst_bpe_il_lim2_dly; + case BST_BPE_IL_LIM_DLY_HYST: + return &cfg->bst_bpe_il_lim_dly_hyst; + case BST_BPE_IL_LIM_THLD_HYST: + return &cfg->bst_bpe_il_lim_thld_hyst; + case BST_BPE_IL_LIM1_ATK_RATE: + return &cfg->bst_bpe_il_lim1_atk_rate; + case BST_BPE_IL_LIM2_ATK_RATE: + return &cfg->bst_bpe_il_lim2_atk_rate; + case BST_BPE_IL_LIM1_RLS_RATE: + return &cfg->bst_bpe_il_lim1_rls_rate; + case BST_BPE_IL_LIM2_RLS_RATE: + return &cfg->bst_bpe_il_lim2_rls_rate; + default: + return NULL; + } +} + +static inline u32 *cs35l45_get_ldpm_param(struct cs35l45_private *cs35l45, + enum ldpm_of_param param) +{ + struct ldpm_config *cfg = &cs35l45->pdata.ldpm_cfg; + + switch (param) { + case LDPM_GP1_BOOST_SEL: + return &cfg->ldpm_gp1_boost_sel; + case LDPM_GP1_AMP_SEL: + return &cfg->ldpm_gp1_amp_sel; + case LDPM_GP1_DELAY: + return &cfg->ldpm_gp1_delay; + case LDPM_GP1_PCM_THLD: + return &cfg->ldpm_gp1_pcm_thld; + case LDPM_GP2_IMON_SEL: + return &cfg->ldpm_gp2_imon_sel; + case LDPM_GP2_VMON_SEL: + return &cfg->ldpm_gp2_vmon_sel; + case LDPM_GP2_DELAY: + return &cfg->ldpm_gp2_delay; + case LDPM_GP2_PCM_THLD: + return &cfg->ldpm_gp2_pcm_thld; + default: + return NULL; + } +} + +static inline u32 *cs35l45_get_classh_param(struct cs35l45_private *cs35l45, + enum classh_of_param param) +{ + struct classh_config *cfg = &cs35l45->pdata.classh_cfg; + + switch (param) { + case CH_HDRM: + return &cfg->ch_hdrm; + case CH_RATIO: + return &cfg->ch_ratio; + case CH_REL_RATE: + return &cfg->ch_rel_rate; + case CH_OVB_THLD1: + return &cfg->ch_ovb_thld1; + case CH_OVB_THLDDELTA: + return &cfg->ch_ovb_thlddelta; + case CH_VDD_BST_MAX: + return &cfg->ch_vdd_bst_max; + case CH_OVB_RATIO: + return &cfg->ch_ovb_ratio; + case CH_THLD1_OFFSET: + return &cfg->ch_thld1_offset; + case AUD_MEM_DEPTH: + return &cfg->aud_mem_depth; + default: + return NULL; + } +} + +#endif /* __CS35L45_H */ diff --git a/techpack/audio/asoc/codecs/cs35l45/wm_adsp.c b/techpack/audio/asoc/codecs/cs35l45/wm_adsp.c new file mode 100644 index 0000000000000..1e8a6e02e09b8 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/wm_adsp.c @@ -0,0 +1,5164 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * wm_adsp.c -- Wolfson ADSP support + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + */ +//#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l45.h" + +#define adsp_crit(_dsp, fmt, ...) \ + dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_err(_dsp, fmt, ...) \ + dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_warn(_dsp, fmt, ...) \ + dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_info(_dsp, fmt, ...) \ + dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_dbg(_dsp, fmt, ...) \ + dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) + +#define compr_err(_obj, fmt, ...) \ + adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ + ##__VA_ARGS__) +#define compr_dbg(_obj, fmt, ...) \ + adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ + ##__VA_ARGS__) + +#define ADSP1_CONTROL_1 0x00 +#define ADSP1_CONTROL_2 0x02 +#define ADSP1_CONTROL_3 0x03 +#define ADSP1_CONTROL_4 0x04 +#define ADSP1_CONTROL_5 0x06 +#define ADSP1_CONTROL_6 0x07 +#define ADSP1_CONTROL_7 0x08 +#define ADSP1_CONTROL_8 0x09 +#define ADSP1_CONTROL_9 0x0A +#define ADSP1_CONTROL_10 0x0B +#define ADSP1_CONTROL_11 0x0C +#define ADSP1_CONTROL_12 0x0D +#define ADSP1_CONTROL_13 0x0F +#define ADSP1_CONTROL_14 0x10 +#define ADSP1_CONTROL_15 0x11 +#define ADSP1_CONTROL_16 0x12 +#define ADSP1_CONTROL_17 0x13 +#define ADSP1_CONTROL_18 0x14 +#define ADSP1_CONTROL_19 0x16 +#define ADSP1_CONTROL_20 0x17 +#define ADSP1_CONTROL_21 0x18 +#define ADSP1_CONTROL_22 0x1A +#define ADSP1_CONTROL_23 0x1B +#define ADSP1_CONTROL_24 0x1C +#define ADSP1_CONTROL_25 0x1E +#define ADSP1_CONTROL_26 0x20 +#define ADSP1_CONTROL_27 0x21 +#define ADSP1_CONTROL_28 0x22 +#define ADSP1_CONTROL_29 0x23 +#define ADSP1_CONTROL_30 0x24 +#define ADSP1_CONTROL_31 0x26 + +/* + * ADSP1 Control 19 + */ +#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ +#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ +#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ + + +/* + * ADSP1 Control 30 + */ +#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ +#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ +#define ADSP1_START 0x0001 /* DSP1_START */ +#define ADSP1_START_MASK 0x0001 /* DSP1_START */ +#define ADSP1_START_SHIFT 0 /* DSP1_START */ +#define ADSP1_START_WIDTH 1 /* DSP1_START */ + +/* + * ADSP1 Control 31 + */ +#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2_CONTROL 0x0 +#define ADSP2_CLOCKING 0x1 +#define ADSP2V2_CLOCKING 0x2 +#define ADSP2_STATUS1 0x4 +#define ADSP2_WDMA_CONFIG_1 0x30 +#define ADSP2_WDMA_CONFIG_2 0x31 +#define ADSP2V2_WDMA_CONFIG_2 0x32 +#define ADSP2_RDMA_CONFIG_1 0x34 + +#define ADSP2_SCRATCH0 0x40 +#define ADSP2_SCRATCH1 0x41 +#define ADSP2_SCRATCH2 0x42 +#define ADSP2_SCRATCH3 0x43 + +#define ADSP2V2_SCRATCH0_1 0x40 +#define ADSP2V2_SCRATCH2_3 0x42 + +/* + * ADSP2 Control + */ + +#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ +#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ +#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ +#define ADSP2_START 0x0001 /* DSP1_START */ +#define ADSP2_START_MASK 0x0001 /* DSP1_START */ +#define ADSP2_START_SHIFT 0 /* DSP1_START */ +#define ADSP2_START_WIDTH 1 /* DSP1_START */ + +/* + * ADSP2 clocking + */ +#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ +#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ +#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +/* + * ADSP2V2 clocking + */ +#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ +#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ +#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ + +/* + * ADSP2 Status 1 + */ +#define ADSP2_RAM_RDY 0x0001 +#define ADSP2_RAM_RDY_MASK 0x0001 +#define ADSP2_RAM_RDY_SHIFT 0 +#define ADSP2_RAM_RDY_WIDTH 1 + +/* + * ADSP2 Lock support + */ +#define ADSP2_LOCK_CODE_0 0x5555 +#define ADSP2_LOCK_CODE_1 0xAAAA + +#define ADSP2_WATCHDOG 0x0A +#define ADSP2_BUS_ERR_ADDR 0x52 +#define ADSP2_REGION_LOCK_STATUS 0x64 +#define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 +#define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 +#define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A +#define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C +#define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E +#define ADSP2_LOCK_REGION_CTRL 0x7A +#define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C + +#define ADSP2_REGION_LOCK_ERR_MASK 0x8000 +#define ADSP2_SLAVE_ERR_MASK 0x4000 +#define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 +#define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 +#define ADSP2_CTRL_ERR_EINT 0x0001 + +#define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF +#define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF +#define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 +#define ADSP2_PMEM_ERR_ADDR_SHIFT 16 +#define ADSP2_WDT_ENA_MASK 0xFFFFFFFD + +#define ADSP2_LOCK_REGION_SHIFT 16 + +#define ADSP_MAX_STD_CTRL_SIZE 512 + +#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100 +#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10 +#define WM_ADSP_ACKED_CTL_MIN_VALUE 0 +#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF + +/* + * Event control messages + */ +#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001 + +/* + * HALO system info + */ +#define HALO_AHBM_WINDOW_DEBUG_0 0x02040 +#define HALO_AHBM_WINDOW_DEBUG_1 0x02044 + +/* + * HALO core + */ +#define HALO_SAMPLE_RATE_RX1 0x00080 +#define HALO_SAMPLE_RATE_TX1 0x00280 +#define HALO_SCRATCH1 0x005c0 +#define HALO_SCRATCH2 0x005c8 +#define HALO_SCRATCH3 0x005d0 +#define HALO_SCRATCH4 0x005d8 +#define HALO_CCM_CORE_CONTROL 0x41000 +#define HALO_CORE_SOFT_RESET 0x00010 +#define HALO_WDT_CONTROL 0x47000 + +/* + * HALO MPU banks + */ +#define HALO_MPU_XMEM_ACCESS_0 0x43000 +#define HALO_MPU_YMEM_ACCESS_0 0x43004 +#define HALO_MPU_WINDOW_ACCESS_0 0x43008 +#define HALO_MPU_XREG_ACCESS_0 0x4300C +#define HALO_MPU_YREG_ACCESS_0 0x43014 +#define HALO_MPU_XMEM_ACCESS_1 0x43018 +#define HALO_MPU_YMEM_ACCESS_1 0x4301C +#define HALO_MPU_WINDOW_ACCESS_1 0x43020 +#define HALO_MPU_XREG_ACCESS_1 0x43024 +#define HALO_MPU_YREG_ACCESS_1 0x4302C +#define HALO_MPU_XMEM_ACCESS_2 0x43030 +#define HALO_MPU_YMEM_ACCESS_2 0x43034 +#define HALO_MPU_WINDOW_ACCESS_2 0x43038 +#define HALO_MPU_XREG_ACCESS_2 0x4303C +#define HALO_MPU_YREG_ACCESS_2 0x43044 +#define HALO_MPU_XMEM_ACCESS_3 0x43048 +#define HALO_MPU_YMEM_ACCESS_3 0x4304C +#define HALO_MPU_WINDOW_ACCESS_3 0x43050 +#define HALO_MPU_XREG_ACCESS_3 0x43054 +#define HALO_MPU_YREG_ACCESS_3 0x4305C +#define HALO_MPU_XM_VIO_ADDR 0x43100 +#define HALO_MPU_XM_VIO_STATUS 0x43104 +#define HALO_MPU_YM_VIO_ADDR 0x43108 +#define HALO_MPU_YM_VIO_STATUS 0x4310C +#define HALO_MPU_PM_VIO_ADDR 0x43110 +#define HALO_MPU_PM_VIO_STATUS 0x43114 +#define HALO_MPU_LOCK_CONFIG 0x43140 + +/* + * HALO_AHBM_WINDOW_DEBUG_1 + */ +#define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00 +#define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8 +#define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff + +/* + * HALO_SAMPLE_RATE_[RX|TX]n + */ +#define HALO_DSP_RATE_SHIFT 0 +#define HALO_DSP_RATE_MASK 0x1f + +/* + * HALO_CCM_CORE_CONTROL + */ +#define HALO_CORE_EN 0x00000001 + +/* + * HALO_CORE_SOFT_RESET + */ +#define HALO_CORE_SOFT_RESET_MASK 0x00000001 + +/* + * HALO_WDT_CONTROL + */ +#define HALO_WDT_EN_MASK 0x00000001 + +/* + * HALO_MPU_?M_VIO_STATUS + */ +#define HALO_MPU_VIO_STS_MASK 0x007e0000 +#define HALO_MPU_VIO_STS_SHIFT 17 +#define HALO_MPU_VIO_ERR_WR_MASK 0x00008000 +#define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff +#define HALO_MPU_VIO_ERR_SRC_SHIFT 0 + +static struct wm_adsp_ops wm_adsp1_ops; +static struct wm_adsp_ops wm_adsp2_ops[]; +static struct wm_adsp_ops wm_halo_ops; +static struct wm_adsp_ops wm_vpu_ops; + +struct wm_adsp_buf { + struct list_head list; + void *buf; +}; + +static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len, + struct list_head *list) +{ + struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL); + + if (buf == NULL) + return NULL; + + buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA); + if (!buf->buf) { + kfree(buf); + return NULL; + } + + if (list) + list_add_tail(&buf->list, list); + + return buf; +} + +static void wm_adsp_buf_free(struct list_head *list) +{ + while (!list_empty(list)) { + struct wm_adsp_buf *buf = list_first_entry(list, + struct wm_adsp_buf, + list); + list_del(&buf->list); + kfree(buf->buf); + kfree(buf); + } +} + +// Speaker calibration default value +#define CAL_R_DEFAULT 8392 +#define AMBIENT_DEFAULT 30 +#define CAL_STATUS_DEFAULT 1 + +#define WM_ADSP_FW_MBC_VSS 0 +#define WM_ADSP_FW_HIFI 1 +#define WM_ADSP_FW_TX 2 +#define WM_ADSP_FW_TX_SPK 3 +#define WM_ADSP_FW_RX 4 +#define WM_ADSP_FW_RX_ANC 5 +#define WM_ADSP_FW_CTRL 6 +#define WM_ADSP_FW_ASR 7 +#define WM_ADSP_FW_TRACE 8 +#define WM_ADSP_FW_SPK_PROT 9 +#define WM_ADSP_FW_DIAG 10 +#define WM_ADSP_FW_CALIB 11 +#define WM_ADSP_FW_MISC 12 + +#define WM_ADSP_NUM_FW 13 + +static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = { + [WM_ADSP_FW_MBC_VSS] = "MBC/VSS", + [WM_ADSP_FW_HIFI] = "MasterHiFi", + [WM_ADSP_FW_TX] = "Tx", + [WM_ADSP_FW_TX_SPK] = "Tx Speaker", + [WM_ADSP_FW_RX] = "Rx", + [WM_ADSP_FW_RX_ANC] = "Rx ANC", + [WM_ADSP_FW_CTRL] = "Voice Ctrl", + [WM_ADSP_FW_ASR] = "ASR Assist", + [WM_ADSP_FW_TRACE] = "Dbg Trace", + [WM_ADSP_FW_SPK_PROT] = "Protection", + [WM_ADSP_FW_DIAG] = "Diag", + [WM_ADSP_FW_CALIB] = "Diag Z", + [WM_ADSP_FW_MISC] = "Misc", +}; + +struct wm_adsp_system_config_xm_hdr { + __be32 sys_enable; + __be32 fw_id; + __be32 fw_rev; + __be32 boot_status; + __be32 watchdog; + __be32 dma_buffer_size; + __be32 rdma[6]; + __be32 wdma[8]; + __be32 build_job_name[3]; + __be32 build_job_number; +}; + +struct wm_halo_system_config_xm_hdr { + __be32 halo_heartbeat; + __be32 build_job_name[3]; + __be32 build_job_number; +}; + +struct wm_adsp_alg_xm_struct { + __be32 magic; + __be32 smoothing; + __be32 threshold; + __be32 host_buf_ptr; + __be32 start_seq; + __be32 high_water_mark; + __be32 low_water_mark; + __be64 smoothed_power; +}; + +struct wm_adsp_host_buf_coeff_v1 { + __be32 host_buf_ptr; /* Host buffer pointer */ + __be32 versions; /* Version numbers */ + __be32 name[4]; /* The buffer name */ +}; + +struct wm_adsp_buffer { + __be32 buf1_base; /* Base addr of first buffer area */ + __be32 buf1_size; /* Size of buf1 area in DSP words */ + __be32 buf2_base; /* Base addr of 2nd buffer area */ + __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */ + __be32 buf3_base; /* Base addr of buf3 area */ + __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */ + __be32 high_water_mark; /* Point at which IRQ is asserted */ + __be32 irq_count; /* bits 1-31 count IRQ assertions */ + __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */ + __be32 next_write_index; /* word index of next write */ + __be32 next_read_index; /* word index of next read */ + __be32 error; /* error if any */ + __be32 oldest_block_index; /* word index of oldest surviving */ + __be32 requested_rewind; /* how many blocks rewind was done */ + __be32 reserved_space; /* internal */ + __be32 min_free; /* min free space since stream start */ + __be32 blocks_written[2]; /* total blocks written (64 bit) */ + __be32 words_written[2]; /* total words written (64 bit) */ +}; + +struct wm_adsp_compr; + +struct wm_adsp_compr_buf { + struct list_head list; + struct wm_adsp *dsp; + struct wm_adsp_compr *compr; + + int num_regions; + const struct wm_adsp_buffer_region_def *region_defs; + struct wm_adsp_buffer_region *regions; + u32 host_buf_ptr; + + u32 error; + u32 irq_count; + int read_index; + int avail; + int host_buf_mem_type; + + char *name; +}; + +struct wm_adsp_compr { + struct list_head list; + struct wm_adsp *dsp; + struct wm_adsp_compr_buf *buf; + + struct snd_compr_stream *stream; + struct snd_compressed_buffer size; + + u32 *raw_buf; + unsigned int copied_total; + + unsigned int sample_rate; + + const char *name; +}; + +#define WM_ADSP_DATA_WORD_SIZE_DEFAULT 3 +#define WM_ADSP_DATA_WORD_SIZE_VPU 4 + +#define WM_ADSP_DATA_WORD_MASK_DEFAULT 0x00ffffffu +#define WM_ADSP_DATA_WORD_MASK_VPU 0xffffffffu + +#define WM_ADSP_MIN_FRAGMENTS 1 +#define WM_ADSP_MAX_FRAGMENTS 256 +#define WM_ADSP_MIN_FRAGMENT_SIZE_WORDS 64 +#define WM_ADSP_MAX_FRAGMENT_SIZE_WORDS 4096 + +#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7 + +#define HOST_BUFFER_FIELD(field) \ + (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32)) + +#define ALG_XM_FIELD(field) \ + (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32)) + +#define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1 + +#define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00 +#define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8 + +static int wm_adsp_buffer_init(struct wm_adsp *dsp); +static int wm_adsp_buffer_free(struct wm_adsp *dsp); + +struct wm_adsp_buffer_region { + unsigned int offset; + unsigned int cumulative_size; + unsigned int mem_type; + unsigned int base_addr; +}; + +struct wm_adsp_buffer_region_def { + unsigned int mem_type; + unsigned int base_offset; + unsigned int size_offset; +}; + +static const struct wm_adsp_buffer_region_def default_regions[] = { + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(buf1_base), + .size_offset = HOST_BUFFER_FIELD(buf1_size), + }, + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(buf2_base), + .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size), + }, + { + .mem_type = WMFW_ADSP2_YM, + .base_offset = HOST_BUFFER_FIELD(buf3_base), + .size_offset = HOST_BUFFER_FIELD(buf_total_size), + }, +}; + +static const struct wm_adsp_buffer_region_def vpu_regions[] = { + { + .mem_type = WMFW_VPU_DM, + .base_offset = HOST_BUFFER_FIELD(buf1_base), + .size_offset = HOST_BUFFER_FIELD(buf1_size), + }, + { + .mem_type = WMFW_VPU_DM, + .base_offset = HOST_BUFFER_FIELD(buf2_base), + .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size), + }, + { + .mem_type = WMFW_VPU_DM, + .base_offset = HOST_BUFFER_FIELD(buf3_base), + .size_offset = HOST_BUFFER_FIELD(buf_total_size), + }, +}; + +struct wm_adsp_fw_caps { + u32 id; + struct snd_codec_desc desc; +}; + +static const struct wm_adsp_fw_caps ctrl_caps[] = { + { + .id = SND_AUDIOCODEC_BESPOKE, + .desc = { + .max_ch = 8, + .sample_rates = { 16000 }, + .num_sample_rates = 1, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + }, +}; + +static const struct wm_adsp_fw_caps trace_caps[] = { + { + .id = SND_AUDIOCODEC_BESPOKE, + .desc = { + .max_ch = 8, + .sample_rates = { + 4000, 8000, 11025, 12000, 16000, 22050, + 24000, 32000, 44100, 48000, 64000, 88200, + 96000, 176400, 192000 + }, + .num_sample_rates = 15, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + }, +}; + +static const struct { + const char *file; + int compr_direction; + int num_caps; + const struct wm_adsp_fw_caps *caps; + bool voice_trigger; +} wm_adsp_fw[WM_ADSP_NUM_FW] = { + [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, + [WM_ADSP_FW_HIFI] = { .file = "hifi" }, + [WM_ADSP_FW_TX] = { .file = "tx" }, + [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" }, + [WM_ADSP_FW_RX] = { .file = "rx" }, + [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" }, + [WM_ADSP_FW_CTRL] = { + .file = "ctrl", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(ctrl_caps), + .caps = ctrl_caps, + .voice_trigger = true, + }, + [WM_ADSP_FW_ASR] = { .file = "asr" }, + [WM_ADSP_FW_TRACE] = { + .file = "trace", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(trace_caps), + .caps = trace_caps, + }, + [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" }, + [WM_ADSP_FW_DIAG] = { .file = "diag" }, + [WM_ADSP_FW_CALIB] = { .file = "diag-z" }, + [WM_ADSP_FW_MISC] = { .file = "misc" }, +}; + +struct wm_coeff_ctl_ops { + int (*xget)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*xput)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +}; + +struct wm_coeff_ctl { + const char *name; + const char *fw_name; + /* Subname is needed to match with firmware */ + const char *subname; + unsigned int subname_len; + struct wm_adsp_alg_region alg_region; + struct wm_coeff_ctl_ops ops; + struct wm_adsp *dsp; + unsigned int enabled:1; + struct list_head list; + void *cache; + unsigned int offset; + size_t len; + unsigned int set:1; + struct soc_bytes_ext bytes_ext; + unsigned int flags; + unsigned int type; +}; + +static const char *wm_adsp_mem_region_name(unsigned int type) +{ + switch (type) { + case WMFW_ADSP1_PM: + return "PM"; + case WMFW_HALO_PM_PACKED: + return "PM_PACKED"; + case WMFW_ADSP1_DM: + return "DM"; + case WMFW_ADSP2_XM: + return "XM"; + case WMFW_HALO_XM_PACKED: + return "XM_PACKED"; + case WMFW_ADSP2_YM: + return "YM"; + case WMFW_HALO_YM_PACKED: + return "YM_PACKED"; + case WMFW_ADSP1_ZM: + return "ZM"; + case WMFW_VPU_DM: + return "DM"; + default: + return NULL; + } +} + +#ifdef CONFIG_DEBUG_FS +static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + kfree(dsp->wmfw_file_name); + dsp->wmfw_file_name = tmp; +} + +static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + kfree(dsp->bin_file_name); + dsp->bin_file_name = tmp; +} + +static void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ + kfree(dsp->wmfw_file_name); + kfree(dsp->bin_file_name); + dsp->wmfw_file_name = NULL; + dsp->bin_file_name = NULL; +} + +static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->wmfw_file_name || !dsp->booted) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->wmfw_file_name, + strlen(dsp->wmfw_file_name)); + + mutex_unlock(&dsp->pwr_lock); + return ret; +} + +static ssize_t wm_adsp_debugfs_bin_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->bin_file_name || !dsp->booted) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->bin_file_name, + strlen(dsp->bin_file_name)); + + mutex_unlock(&dsp->pwr_lock); + return ret; +} + +static const struct { + const char *name; + const struct file_operations fops; +} wm_adsp_debugfs_fops[] = { + { + .name = "wmfw_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_wmfw_read, + }, + }, + { + .name = "bin_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_bin_read, + }, + }, +}; + +static void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_component *component) +{ + struct dentry *root = NULL; + int i; + + root = debugfs_create_dir(dsp->name, component->debugfs_root); + + debugfs_create_bool("booted", 0444, root, &dsp->booted); + debugfs_create_bool("running", 0444, root, &dsp->running); + debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id); + debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version); + + for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) + debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, root, + dsp, &wm_adsp_debugfs_fops[i].fops); + + dsp->debugfs_root = root; +} + +static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ + wm_adsp_debugfs_clear(dsp); + debugfs_remove_recursive(dsp->debugfs_root); +} +#else +static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_component *component) +{ +} + +static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ +} + +static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ +} +#endif + +int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_fw_get); + +int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + int ret = 0; + + if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw) + return 0; + + if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW) + return -EINVAL; + + mutex_lock(&dsp[e->shift_l].pwr_lock); + + if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list)) + ret = -EBUSY; + else + dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0]; + + mutex_unlock(&dsp[e->shift_l].pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_fw_put); + +const struct soc_enum wm_adsp_fw_enum[] = { + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), +}; +EXPORT_SYMBOL_GPL(wm_adsp_fw_enum); + +static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, + int type) +{ + int i; + + for (i = 0; i < dsp->num_mems; i++) + if (dsp->mem[i].type == type) + return &dsp->mem[i]; + + return NULL; +} + +static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem, + unsigned int offset) +{ + switch (mem->type) { + case WMFW_ADSP1_PM: + return mem->base + (offset * 3); + case WMFW_ADSP1_DM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_ADSP1_ZM: + return mem->base + (offset * 2); + default: + WARN(1, "Unknown memory region type"); + return offset; + } +} + +static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem, + unsigned int offset) +{ + switch (mem->type) { + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + return mem->base + (offset * 4); + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + return (mem->base + (offset * 3)) & ~0x3; + case WMFW_HALO_PM_PACKED: + return mem->base + (offset * 5); + default: + WARN(1, "Unknown memory region type"); + return offset; + } +} + +static unsigned int wm_vpu_region_to_reg(struct wm_adsp_region const *mem, + unsigned int offset) +{ + switch (mem->type) { + case WMFW_VPU_DM: + return mem->base + (offset * 4); + default: + WARN(1, "Unknown memory region type"); + return offset; + } +} + +static void wm_adsp_read_fw_status(struct wm_adsp *dsp, + int noffs, unsigned int *offs) +{ + unsigned int i; + int ret; + + for (i = 0; i < noffs; ++i) { + ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); + return; + } + } +} + +static void wm_adsp2_show_fw_status(struct wm_adsp *dsp) +{ + unsigned int offs[] = { + ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3, + }; + + wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + offs[0], offs[1], offs[2], offs[3]); +} + +static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) +{ + unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 }; + + wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + offs[0] & 0xFFFF, offs[0] >> 16, + offs[1] & 0xFFFF, offs[1] >> 16); +} + +static void wm_halo_show_fw_status(struct wm_adsp *dsp) +{ + unsigned int offs[] = { + HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4, + }; + + wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + offs[0], offs[1], offs[2], offs[3]); +} + +static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext) +{ + return container_of(ext, struct wm_coeff_ctl, bytes_ext); +} + +static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) +{ + const struct wm_adsp_alg_region *alg_region = &ctl->alg_region; + struct wm_adsp *dsp = ctl->dsp; + const struct wm_adsp_region *mem; + + mem = wm_adsp_find_region(dsp, alg_region->type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", + alg_region->type); + return -EINVAL; + } + + *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset); + + return 0; +} + +static int wm_coeff_info(struct snd_kcontrol *kctl, + struct snd_ctl_elem_info *uinfo) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE; + uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE; + uinfo->value.integer.step = 1; + uinfo->count = 1; + break; + default: + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = ctl->len; + break; + } + + return 0; +} + +static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl, + unsigned int event_id) +{ + struct wm_adsp *dsp = ctl->dsp; + u32 val = cpu_to_be32(event_id); + unsigned int reg; + int i, ret; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", + event_id, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); + + ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); + return ret; + } + + /* + * Poll for ack, we initially poll at ~1ms intervals for firmwares + * that respond quickly, then go to ~10ms polls. A firmware is unlikely + * to ack instantly so we do the first 1ms delay before reading the + * control to avoid a pointless bus transaction + */ + for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) { + switch (i) { + case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1: + usleep_range(1000, 2000); + i++; + break; + default: + usleep_range(10000, 20000); + i += 10; + break; + } + + ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); + return ret; + } + + if (val == 0) { + adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); + return 0; + } + } + + adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", + reg, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), + ctl->offset); + + return -ETIMEDOUT; +} + +static int wm_coeff_write_ctrl_raw(struct wm_coeff_ctl *ctl, + const void *buf, size_t len) +{ + struct wm_adsp *dsp = ctl->dsp; + void *scratch, *temp; + size_t to_write = PAGE_SIZE; + int ret; + unsigned int reg; + unsigned int addr_div; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + scratch = kmalloc(PAGE_SIZE, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + addr_div = 2; + break; + default: + addr_div = 1; + break; + } + + temp = (void *)buf; + while (len > 0) { + if (len < to_write) + to_write = len; + + memcpy(scratch, temp, to_write); + + ret = regmap_raw_write(dsp->regmap, reg, scratch, to_write); + if (ret) { + adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", + to_write, reg, ret); + kfree(scratch); + return ret; + } + + adsp_dbg(dsp, "Wrote %zu bytes to %x\n", to_write, reg); + + temp += to_write; + reg += to_write / addr_div; + len -= to_write; + } + + kfree(scratch); + + return 0; +} + +static int wm_coeff_write_ctrl(struct wm_coeff_ctl *ctl, + const void *buf, size_t len) +{ + int ret = 0; + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + ret = -EPERM; + else if (buf != ctl->cache) + memcpy(ctl->cache, buf, len); + + ctl->set = 1; + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_ctrl_raw(ctl, buf, len); + + return ret; +} + +static int wm_coeff_put(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + ret = wm_coeff_write_ctrl(ctl, p, ctl->len); + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_tlv_put(struct snd_kcontrol *kctl, + const unsigned int __user *bytes, unsigned int size) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (copy_from_user(ctl->cache, bytes, size)) + ret = -EFAULT; + else + ret = wm_coeff_write_ctrl(ctl, ctl->cache, size); + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_put_acked(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + unsigned int val = ucontrol->value.integer.value[0]; + int ret; + + if (val == 0) + return 0; /* 0 means no event */ + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_acked_control(ctl, val); + else + ret = -EPERM; + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_read_ctrl_raw(struct wm_coeff_ctl *ctl, + void *buf, size_t len) +{ + struct wm_adsp *dsp = ctl->dsp; + void *scratch, *temp; + size_t to_read = PAGE_SIZE, remain = len; + int ret; + unsigned int reg; + unsigned int addr_div; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + addr_div = 2; + break; + default: + addr_div = 1; + break; + } + + temp = scratch; + remain = len; + while (remain > 0) { + if (remain < to_read) + to_read = remain; + + ret = regmap_raw_read(dsp->regmap, reg, temp, to_read); + if (ret) { + adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", + to_read, reg, ret); + kfree(scratch); + return ret; + } + + adsp_dbg(dsp, "Read %zu bytes from %x\n", to_read, reg); + + temp += to_read; + reg += to_read / addr_div; + remain -= to_read; + } + + memcpy(buf, scratch, len); + kfree(scratch); + + return 0; +} + +static int wm_coeff_read_ctrl(struct wm_coeff_ctl *ctl, void *buf, size_t len) +{ + int ret = 0; + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + if (ctl->enabled && ctl->dsp->running) + return wm_coeff_read_ctrl_raw(ctl, buf, len); + else + return -EPERM; + } else { + if (!ctl->flags && ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len); + + if (buf != ctl->cache) + memcpy(buf, ctl->cache, len); + } + + return ret; +} + +static int wm_coeff_get(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret; + + mutex_lock(&ctl->dsp->pwr_lock); + ret = wm_coeff_read_ctrl(ctl, p, ctl->len); + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_tlv_get(struct snd_kcontrol *kctl, + unsigned int __user *bytes, unsigned int size) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, size); + + if (!ret && copy_to_user(bytes, ctl->cache, size)) + ret = -EFAULT; + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* + * Although it's not useful to read an acked control, we must satisfy + * user-side assumptions that all controls are readable and that a + * write of the same value should be filtered out (it's valid to send + * the same event number again to the firmware). We therefore return 0, + * meaning "no event" so valid event numbers will always be a change + */ + ucontrol->value.integer.value[0] = 0; + + return 0; +} + +struct wmfw_ctl_work { + struct wm_adsp *dsp; + struct wm_coeff_ctl *ctl; + struct work_struct work; +}; + +static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len) +{ + unsigned int out, rd, wr, vol; + + if (len > ADSP_MAX_STD_CTRL_SIZE) { + rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ; + wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE; + vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; + + out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK; + } else { + rd = SNDRV_CTL_ELEM_ACCESS_READ; + wr = SNDRV_CTL_ELEM_ACCESS_WRITE; + vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; + + out = 0; + } + + if (in) { + out |= rd; + if (in & WMFW_CTL_FLAG_WRITEABLE) + out |= wr; + if (in & WMFW_CTL_FLAG_VOLATILE) + out |= vol; + } else { + out |= rd | wr | vol; + } + + return out; +} + +static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl) +{ + struct snd_kcontrol_new *kcontrol; + int ret; + + if (!ctl || !ctl->name) + return -EINVAL; + + kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); + if (!kcontrol) + return -ENOMEM; + + kcontrol->name = ctl->name; + kcontrol->info = wm_coeff_info; + kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; + kcontrol->tlv.c = snd_soc_bytes_tlv_callback; + kcontrol->private_value = (unsigned long)&ctl->bytes_ext; + kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len); + + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + kcontrol->get = wm_coeff_get_acked; + kcontrol->put = wm_coeff_put_acked; + break; + default: + if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { + ctl->bytes_ext.max = ctl->len; + ctl->bytes_ext.get = wm_coeff_tlv_get; + ctl->bytes_ext.put = wm_coeff_tlv_put; + } else { + kcontrol->get = wm_coeff_get; + kcontrol->put = wm_coeff_put; + } + break; + } + + ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1); + if (ret < 0) + goto err_kcontrol; + + kfree(kcontrol); + + return 0; + +err_kcontrol: + kfree(kcontrol); + return ret; +} + +static int wm_coeff_init_control_caches(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (!ctl->enabled || ctl->set) + continue; + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + continue; + + /* + * For readable controls populate the cache from the DSP memory. + * For non-readable controls the cache was zero-filled when + * created so we don't need to do anything. + */ + if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) { + ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static int wm_coeff_sync_controls(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + adsp_dbg(dsp, "%s\n", __func__); + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (!ctl->enabled) + continue; + if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) { + ret = wm_coeff_write_ctrl_raw(ctl, ctl->cache, + ctl->len); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static void wm_adsp_signal_event_controls(struct wm_adsp *dsp, + unsigned int event) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) + continue; + + if (!ctl->enabled) + continue; + + ret = wm_coeff_write_acked_control(ctl, event); + if (ret) + adsp_warn(dsp, + "Failed to send 0x%x event to alg 0x%x (%d)\n", + event, ctl->alg_region.alg, ret); + } +} + +static void wm_adsp_ctl_work(struct work_struct *work) +{ + struct wmfw_ctl_work *ctl_work = container_of(work, + struct wmfw_ctl_work, + work); + + wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl); + kfree(ctl_work); +} + +static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl) +{ + kfree(ctl->cache); + kfree(ctl->name); + kfree(ctl->subname); + kfree(ctl); +} + +static int wm_adsp_create_control(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region, + unsigned int offset, unsigned int len, + const char *subname, unsigned int subname_len, + unsigned int flags, unsigned int type) +{ + struct wm_coeff_ctl *ctl; + struct wmfw_ctl_work *ctl_work; + char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; + const char *region_name; + const char *fw_txt; + int ret; + + region_name = wm_adsp_mem_region_name(alg_region->type); + if (!region_name) { + adsp_err(dsp, "Unknown region type: %d\n", alg_region->type); + return -EINVAL; + } + + fw_txt = wm_adsp_fw_text[dsp->fw]; + + switch (dsp->fw_ver) { + case 0: + case 1: + snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x", + dsp->name, region_name, alg_region->alg); + subname = NULL; /* don't append subname */ + break; + case 2: + ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, + "%s%c %.12s %x", dsp->name, *region_name, + fw_txt, alg_region->alg); + break; + default: + ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, + "%s %.12s %x", dsp->name, + fw_txt, alg_region->alg); + break; + } + + if (subname) { + int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2; + int skip = 0; + + if (dsp->component->name_prefix) + avail -= strlen(dsp->component->name_prefix) + 1; + + /* Truncate the subname from the start if it is too long */ + if (subname_len > avail) + skip = subname_len - avail; + + snprintf(name + ret, + SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s", + subname_len - skip, subname + skip); + } + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (!strcmp(ctl->name, name)) { + if (!ctl->enabled) + ctl->enabled = 1; + return 0; + } + } + + ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); + if (!ctl) + return -ENOMEM; + ctl->fw_name = fw_txt; + ctl->alg_region = *alg_region; + ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL); + if (!ctl->name) { + ret = -ENOMEM; + goto err_ctl; + } + if (subname) { + ctl->subname_len = subname_len; + ctl->subname = kmemdup(subname, + strlen(subname) + 1, GFP_KERNEL); + if (!ctl->subname) { + ret = -ENOMEM; + goto err_ctl_name; + } + } + ctl->enabled = 1; + ctl->set = 0; + ctl->ops.xget = wm_coeff_get; + ctl->ops.xput = wm_coeff_put; + ctl->dsp = dsp; + + ctl->flags = flags; + ctl->type = type; + ctl->offset = offset; + ctl->len = len; + ctl->cache = kzalloc(ctl->len, GFP_KERNEL); + if (!ctl->cache) { + ret = -ENOMEM; + goto err_ctl_subname; + } + + list_add(&ctl->list, &dsp->ctl_list); + + if (flags & WMFW_CTL_FLAG_SYS) + return 0; + + ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL); + if (!ctl_work) { + ret = -ENOMEM; + goto err_ctl_cache; + } + + ctl_work->dsp = dsp; + ctl_work->ctl = ctl; + INIT_WORK(&ctl_work->work, wm_adsp_ctl_work); + schedule_work(&ctl_work->work); + + return 0; + +err_ctl_cache: + kfree(ctl->cache); +err_ctl_subname: + kfree(ctl->subname); +err_ctl_name: + kfree(ctl->name); +err_ctl: + kfree(ctl); + + return ret; +} + +struct wm_coeff_parsed_alg { + int id; + const u8 *name; + int name_len; + int ncoeff; +}; + +int wm_adsp_handle_fw_event(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret = 0, serviced = 0; + u32 val = 0; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_FWEVENT) + continue; + if (!dsp->fwevent_cb) { + adsp_err(dsp, + "FW event callback not registered: %s\n", + ctl->name); + return -EINVAL; + } + + ret = wm_coeff_read_ctrl_raw(ctl, &val, ctl->len); + if (ret < 0) + return ret; + + val = be32_to_cpu(val); + if (val == 0xFFFFFFu) + continue; + + dsp->fwevent_cb(dsp, val); + + val = cpu_to_be32(0xFFFFFFu); + ret = wm_coeff_write_ctrl_raw(ctl, &val, ctl->len); + if (ret < 0) + return ret; + serviced++; + + } + + return serviced; +} +EXPORT_SYMBOL_GPL(wm_adsp_handle_fw_event); + +struct wm_coeff_parsed_coeff { + int offset; + int mem_type; + const u8 *name; + int name_len; + int ctl_type; + int flags; + int len; +}; + +static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str) +{ + int length; + + switch (bytes) { + case 1: + length = **pos; + break; + case 2: + length = le16_to_cpu(*((__le16 *)*pos)); + break; + default: + return 0; + } + + if (str) + *str = *pos + bytes; + + *pos += ((length + bytes) + 3) & ~0x03; + + return length; +} + +static int wm_coeff_parse_int(int bytes, const u8 **pos) +{ + int val = 0; + + switch (bytes) { + case 2: + val = le16_to_cpu(*((__le16 *)*pos)); + break; + case 4: + val = le32_to_cpu(*((__le32 *)*pos)); + break; + default: + break; + } + + *pos += bytes; + + return val; +} + +static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_alg *blk) +{ + const struct wmfw_adsp_alg_data *raw; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_alg_data *)*data; + *data = raw->data; + + blk->id = le32_to_cpu(raw->id); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ncoeff = le32_to_cpu(raw->ncoeff); + break; + default: + blk->id = wm_coeff_parse_int(sizeof(raw->id), data); + blk->name_len = wm_coeff_parse_string(sizeof(u8), data, + &blk->name); + wm_coeff_parse_string(sizeof(u16), data, NULL); + blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data); + break; + } + + adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); + adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); +} + +static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_coeff *blk) +{ + const struct wmfw_adsp_coeff_data *raw; + const u8 *tmp; + int length; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_coeff_data *)*data; + *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size); + + blk->offset = le16_to_cpu(raw->hdr.offset); + blk->mem_type = le16_to_cpu(raw->hdr.type); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ctl_type = le16_to_cpu(raw->ctl_type); + blk->flags = le16_to_cpu(raw->flags); + blk->len = le32_to_cpu(raw->len); + break; + default: + tmp = *data; + blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp); + blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp); + length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp); + blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp, + &blk->name); + wm_coeff_parse_string(sizeof(u8), &tmp, NULL); + wm_coeff_parse_string(sizeof(u16), &tmp, NULL); + blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp); + blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp); + blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp); + + *data = *data + sizeof(raw->hdr) + length; + break; + } + + adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); + adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); + adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); + adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); + adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); +} + +static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp, + const struct wm_coeff_parsed_coeff *coeff_blk, + unsigned int f_required, + unsigned int f_illegal) +{ + if ((coeff_blk->flags & f_illegal) || + ((coeff_blk->flags & f_required) != f_required)) { + adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", + coeff_blk->flags, coeff_blk->ctl_type); + return -EINVAL; + } + + return 0; +} + +static int wm_adsp_parse_coeff(struct wm_adsp *dsp, + const struct wmfw_region *region) +{ + struct wm_adsp_alg_region alg_region = {}; + struct wm_coeff_parsed_alg alg_blk; + struct wm_coeff_parsed_coeff coeff_blk; + const u8 *data = region->data; + int i, ret; + + wm_coeff_parse_alg(dsp, &data, &alg_blk); + for (i = 0; i < alg_blk.ncoeff; i++) { + wm_coeff_parse_coeff(dsp, &data, &coeff_blk); + + switch (coeff_blk.ctl_type) { + case SNDRV_CTL_ELEM_TYPE_BYTES: + break; + case WMFW_CTL_TYPE_ACKED: + if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) + continue; /* ignore */ + + ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + case WMFW_CTL_TYPE_HOSTEVENT: + case WMFW_CTL_TYPE_FWEVENT: + ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, + WMFW_CTL_FLAG_SYS | + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + case WMFW_CTL_TYPE_HOST_BUFFER: + ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, + WMFW_CTL_FLAG_SYS | + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + default: + adsp_err(dsp, "Unknown control type: %d\n", + coeff_blk.ctl_type); + return -EINVAL; + } + + alg_region.type = coeff_blk.mem_type; + alg_region.alg = alg_blk.id; + + ret = wm_adsp_create_control(dsp, &alg_region, + coeff_blk.offset, + coeff_blk.len, + coeff_blk.name, + coeff_blk.name_len, + coeff_blk.flags, + coeff_blk.ctl_type); + if (ret < 0) + adsp_err(dsp, "Failed to create control: %.*s, %d\n", + coeff_blk.name_len, coeff_blk.name, ret); + } + + return 0; +} + +static int wm_adsp_write_blocks(struct wm_adsp *dsp, const u8 *data, size_t len, + unsigned int reg, struct list_head *list, + size_t burst_multiple) + +{ + size_t to_write = PAGE_SIZE - (PAGE_SIZE % burst_multiple); + size_t remain = len; + struct wm_adsp_buf *buf; + unsigned int addr_div; + int ret; + + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + addr_div = 2; + break; + default: + addr_div = 1; + break; + } + + while (remain > 0) { + if (remain < to_write) + to_write = remain; + + buf = wm_adsp_buf_alloc(data, to_write, list); + if (!buf) { + adsp_err(dsp, "Out of memory\n"); + return -ENOMEM; + } + + ret = regmap_raw_write_async(dsp->regmap, reg, + buf->buf, to_write); + if (ret != 0) { + adsp_err(dsp, + "Failed to write %zd bytes at %d\n", + to_write, reg); + + return ret; + } + + data += to_write; + reg += to_write / addr_div; + remain -= to_write; + } + + return 0; +} + +static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp, + const char * const file, + unsigned int pos, + const struct firmware *firmware) +{ + const struct wmfw_adsp1_sizes *adsp1_sizes; + + adsp1_sizes = (void *)&firmware->data[pos]; + + adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, + le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm), + le32_to_cpu(adsp1_sizes->zm)); + + return pos + sizeof(*adsp1_sizes); +} + +static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp, + const char * const file, + unsigned int pos, + const struct firmware *firmware) +{ + const struct wmfw_adsp2_sizes *adsp2_sizes; + + adsp2_sizes = (void *)&firmware->data[pos]; + + adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, + le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym), + le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm)); + + return pos + sizeof(*adsp2_sizes); +} + +static unsigned int wm_vpu_parse_sizes(struct wm_adsp *dsp, + const char * const file, + unsigned int pos, + const struct firmware *firmware) +{ + const struct wmfw_vpu_sizes *vpu_sizes; + + vpu_sizes = (void *)&firmware->data[pos]; + + return pos + sizeof(*vpu_sizes); +} + +static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version) +{ + switch (version) { + case 0: + adsp_warn(dsp, "Deprecated file format %d\n", version); + return true; + case 1: + case 2: + return true; + default: + return false; + } +} + +static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version) +{ + switch (version) { + case 3: + return true; + default: + return false; + } +} + +static int wm_adsp_load(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + const struct firmware *firmware; + struct regmap *regmap = dsp->regmap; + unsigned int pos = 0; + const struct wmfw_header *header; + const struct wmfw_adsp1_sizes *adsp1_sizes; + const struct wmfw_footer *footer; + const struct wmfw_region *region; + const struct wm_adsp_region *mem; + const char *region_name; + char *file, *text = NULL; + unsigned int reg; + int regions = 0; + int ret, offset, type; + unsigned int burst_multiple; + + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name, + wm_adsp_fw[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + + ret = request_firmware(&firmware, file, dsp->dev); + if (ret != 0) { + adsp_err(dsp, "Failed to request '%s'\n", file); + goto out; + } + ret = -EINVAL; + + pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); + if (pos >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", + file, firmware->size); + goto out_fw; + } + + header = (void *)&firmware->data[0]; + + if (memcmp(&header->magic[0], "WMFW", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + if (!dsp->ops->validate_version(dsp, header->ver)) { + adsp_err(dsp, "%s: unknown file format %d\n", + file, header->ver); + goto out_fw; + } + + adsp_info(dsp, "Firmware version: %d\n", header->ver); + dsp->fw_ver = header->ver; + + if (header->core != dsp->type) { + adsp_err(dsp, "%s: invalid core %d != %d\n", + file, header->core, dsp->type); + goto out_fw; + } + + pos = sizeof(*header); + pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); + + footer = (void *)&firmware->data[pos]; + pos += sizeof(*footer); + + if (le32_to_cpu(header->len) != pos) { + adsp_err(dsp, "%s: unexpected header length %d\n", + file, le32_to_cpu(header->len)); + goto out_fw; + } + + adsp_dbg(dsp, "%s: timestamp %llu\n", file, + le64_to_cpu(footer->timestamp)); + + while (pos < firmware->size && + sizeof(*region) < firmware->size - pos) { + region = (void *)&(firmware->data[pos]); + region_name = "Unknown"; + reg = 0; + burst_multiple = 4; + text = NULL; + offset = le32_to_cpu(region->offset) & 0xffffff; + type = be32_to_cpu(region->type) & 0xff; + + switch (type) { + case WMFW_NAME_TEXT: + region_name = "Firmware name"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); + break; + case WMFW_ALGORITHM_DATA: + region_name = "Algorithm"; + ret = wm_adsp_parse_coeff(dsp, region); + if (ret != 0) + goto out_fw; + break; + case WMFW_INFO_TEXT: + region_name = "Information"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); + break; + case WMFW_ABSOLUTE: + region_name = "Absolute"; + reg = offset; + break; + case WMFW_ADSP1_PM: + case WMFW_ADSP1_DM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_ADSP1_ZM: + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No region of type: %x\n", type); + goto out_fw; + } + + region_name = wm_adsp_mem_region_name(type); + reg = dsp->ops->region_to_reg(mem, offset); + break; + case WMFW_HALO_PM_PACKED: + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No region of type: %x\n", type); + goto out_fw; + } + + region_name = wm_adsp_mem_region_name(type); + reg = dsp->ops->region_to_reg(mem, offset); + burst_multiple = 20; + break; + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No region of type: %x\n", type); + goto out_fw; + } + + region_name = wm_adsp_mem_region_name(type); + reg = dsp->ops->region_to_reg(mem, offset); + burst_multiple = 12; + break; + default: + adsp_warn(dsp, + "%s.%d: Unknown region type %x at %d(%x)\n", + file, regions, type, pos, pos); + break; + } + + adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, + regions, le32_to_cpu(region->len), offset, + region_name); + + if (le32_to_cpu(region->len) > + firmware->size - pos - sizeof(*region)) { + adsp_err(dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, regions, region_name, + le32_to_cpu(region->len), firmware->size); + ret = -EINVAL; + goto out_fw; + } + + if (text) { + memcpy(text, region->data, le32_to_cpu(region->len)); + adsp_info(dsp, "%s: %s\n", file, text); + kfree(text); + text = NULL; + } + + if (reg) { + ret = wm_adsp_write_blocks(dsp, region->data, + le32_to_cpu(region->len), + reg, &buf_list, + burst_multiple); + if (ret != 0) { + adsp_err(dsp, + "%s.%d: Failed writing data at %d in %s: %d\n", + file, regions, + offset, region_name, ret); + goto out_fw; + } + } + + pos += le32_to_cpu(region->len) + sizeof(*region); + regions++; + } + + ret = regmap_async_complete(regmap); + if (ret != 0) { + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + goto out_fw; + } + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", + file, regions, pos - firmware->size); + + wm_adsp_debugfs_save_wmfwname(dsp, file); + +out_fw: + regmap_async_complete(regmap); + wm_adsp_buf_free(&buf_list); + release_firmware(firmware); + kfree(text); +out: + kfree(file); + + return ret; +} + +/* + * Find wm_coeff_ctl with input name as its subname + * If not found, return NULL + */ +static struct wm_coeff_ctl *wm_adsp_get_ctl(struct wm_adsp *dsp, + const char *name, int type, + unsigned int alg) +{ + struct wm_coeff_ctl *pos, *rslt = NULL; + + list_for_each_entry(pos, &dsp->ctl_list, list) { + if (!pos->subname) + continue; + if (strncmp(pos->subname, name, pos->subname_len) == 0 && + pos->alg_region.alg == alg && + pos->alg_region.type == type && + pos->enabled) { + rslt = pos; + break; + } + } + + return rslt; +} + +int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type, + unsigned int alg, void *buf, size_t len) +{ + struct wm_coeff_ctl *ctl; + struct snd_kcontrol *kcontrol; + char ctl_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; + int ret; + + ctl = wm_adsp_get_ctl(dsp, name, type, alg); + if (!ctl) { + adsp_err(dsp, "'%s' name=%s type=%d alg=%x \n", ctl_name,name,type,alg); + return -EINVAL; + } + + if (len > ctl->len) + return -EINVAL; + + ret = wm_coeff_write_ctrl(ctl, buf, len); + if (ret) + return ret; + + if (ctl->flags & WMFW_CTL_FLAG_SYS) + return 0; + + if (dsp->component->name_prefix) + snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s", + dsp->component->name_prefix, ctl->name); + else + snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s", + ctl->name); + + kcontrol = snd_soc_card_get_kcontrol(dsp->component->card, ctl_name); + if (!kcontrol) { + adsp_err(dsp, "Can't find kcontrol '%s'\n", ctl_name); + return -EINVAL; + } + + snd_ctl_notify(dsp->component->card->snd_card, + SNDRV_CTL_EVENT_MASK_VALUE, &kcontrol->id); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_write_ctl); + +int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type, + unsigned int alg, void *buf, size_t len) +{ + struct wm_coeff_ctl *ctl; + + ctl = wm_adsp_get_ctl(dsp, name, type, alg); + if (!ctl) + return -EINVAL; + + if (len > ctl->len) + return -EINVAL; + + return wm_coeff_read_ctrl(ctl, buf, len); +} +EXPORT_SYMBOL_GPL(wm_adsp_read_ctl); + +static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region) +{ + struct wm_coeff_ctl *ctl; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] && + alg_region->alg == ctl->alg_region.alg && + alg_region->type == ctl->alg_region.type) { + ctl->alg_region.base = alg_region->base; + } + } +} + +static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs, + const struct wm_adsp_region *mem, + unsigned int pos, unsigned int len) +{ + void *alg; + unsigned int reg; + int ret; + __be32 val; + + if (n_algs == 0) { + adsp_err(dsp, "No algorithms\n"); + return ERR_PTR(-EINVAL); + } + + if (n_algs > 1024) { + adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); + return ERR_PTR(-EINVAL); + } + + /* Read the terminator first to validate the length */ + reg = dsp->ops->region_to_reg(mem, pos + len); + + ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list end: %d\n", + ret); + return ERR_PTR(ret); + } + + if (be32_to_cpu(val) != 0xbedead) + adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", + reg, be32_to_cpu(val)); + + /* Convert length from DSP words to bytes */ + len *= sizeof(u32); + + alg = kzalloc(len, GFP_KERNEL | GFP_DMA); + if (!alg) + return ERR_PTR(-ENOMEM); + + reg = dsp->ops->region_to_reg(mem, pos); + + ret = regmap_raw_read(dsp->regmap, reg, alg, len); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list: %d\n", ret); + kfree(alg); + return ERR_PTR(ret); + } + + return alg; +} + +static struct wm_adsp_alg_region * + wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id) +{ + struct wm_adsp_alg_region *alg_region; + + list_for_each_entry(alg_region, &dsp->alg_regions, list) { + if (id == alg_region->alg && type == alg_region->type) + return alg_region; + } + + return NULL; +} + +static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp, + int type, __be32 id, + __be32 base) +{ + struct wm_adsp_alg_region *alg_region; + + alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL); + if (!alg_region) + return ERR_PTR(-ENOMEM); + + alg_region->type = type; + alg_region->alg = be32_to_cpu(id); + alg_region->base = be32_to_cpu(base); + + list_add_tail(&alg_region->list, &dsp->alg_regions); + + if (dsp->fw_ver > 0) + wm_adsp_ctl_fixup_base(dsp, alg_region); + + return alg_region; +} + +static void wm_adsp_free_alg_regions(struct wm_adsp *dsp) +{ + struct wm_adsp_alg_region *alg_region; + + while (!list_empty(&dsp->alg_regions)) { + alg_region = list_first_entry(&dsp->alg_regions, + struct wm_adsp_alg_region, + list); + list_del(&alg_region->list); + kfree(alg_region); + } +} + +static void wmfw_parse_id_header(struct wm_adsp *dsp, + struct wmfw_id_hdr *fw, int nalgs) +{ + dsp->fw_id = be32_to_cpu(fw->id); + dsp->fw_id_version = be32_to_cpu(fw->ver); + + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", + dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, + nalgs); +} + +static void wmfw_v3_parse_id_header(struct wm_adsp *dsp, + struct wmfw_v3_id_hdr *fw, int nalgs) +{ + dsp->fw_id = be32_to_cpu(fw->id); + dsp->fw_id_version = be32_to_cpu(fw->ver); + dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); + + adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", + dsp->fw_id, dsp->fw_vendor_id, + (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, + nalgs); +} + +static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions, + int *type, __be32 *base) +{ + struct wm_adsp_alg_region *alg_region; + int i; + + for (i = 0; i < nregions; i++) { + alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + } + + return 0; +} + +static int wm_adsp1_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp1_id_hdr adsp1_id; + struct wmfw_adsp1_alg_hdr *adsp1_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, + sizeof(adsp1_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + n_algs = be32_to_cpu(adsp1_id.n_algs); + + wmfw_parse_id_header(dsp, &adsp1_id.fw, n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, + adsp1_id.fw.id, adsp1_id.zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, + adsp1_id.fw.id, adsp1_id.dm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + /* Calculate offset and length in DSP words */ + pos = sizeof(adsp1_id) / sizeof(u32); + len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32); + + adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); + if (IS_ERR(adsp1_alg)) + return PTR_ERR(adsp1_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", + i, be32_to_cpu(adsp1_alg[i].alg.id), + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp1_alg[i].dm), + be32_to_cpu(adsp1_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, + adsp1_alg[i].alg.id, + adsp1_alg[i].dm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].dm); + len -= be32_to_cpu(adsp1_alg[i].dm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region DM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, + adsp1_alg[i].alg.id, + adsp1_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].zm); + len -= be32_to_cpu(adsp1_alg[i].zm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp1_alg); + return ret; +} + +static int wm_adsp2_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp2_id_hdr adsp2_id; + struct wmfw_adsp2_alg_hdr *adsp2_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, + sizeof(adsp2_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + n_algs = be32_to_cpu(adsp2_id.n_algs); + + wmfw_parse_id_header(dsp, &adsp2_id.fw, n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + adsp2_id.fw.id, adsp2_id.xm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + adsp2_id.fw.id, adsp2_id.ym); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_id.fw.id, adsp2_id.zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + /* Calculate offset and length in DSP words */ + pos = sizeof(adsp2_id) / sizeof(u32); + len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32); + + adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); + if (IS_ERR(adsp2_alg)) + return PTR_ERR(adsp2_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, + "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", + i, be32_to_cpu(adsp2_alg[i].alg.id), + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp2_alg[i].xm), + be32_to_cpu(adsp2_alg[i].ym), + be32_to_cpu(adsp2_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + adsp2_alg[i].alg.id, + adsp2_alg[i].xm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].xm); + len -= be32_to_cpu(adsp2_alg[i].xm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region XM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + adsp2_alg[i].alg.id, + adsp2_alg[i].ym); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].ym); + len -= be32_to_cpu(adsp2_alg[i].ym); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region YM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_alg[i].alg.id, + adsp2_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].zm); + len -= be32_to_cpu(adsp2_alg[i].zm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp2_alg); + return ret; +} + +static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id, + __be32 xm_base, __be32 ym_base) +{ + int types[] = { + WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED, + WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED + }; + __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; + + return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases); +} + +static int wm_halo_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_halo_id_hdr halo_id; + struct wmfw_halo_alg_hdr *halo_alg; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, + sizeof(halo_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + n_algs = be32_to_cpu(halo_id.n_algs); + + wmfw_v3_parse_id_header(dsp, &halo_id.fw, n_algs); + + ret = wm_halo_create_regions(dsp, halo_id.fw.id, + halo_id.xm_base, halo_id.ym_base); + if (ret) + return ret; + + /* Calculate offset and length in DSP words */ + pos = sizeof(halo_id) / sizeof(u32); + len = (sizeof(*halo_alg) * n_algs) / sizeof(u32); + + halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); + if (IS_ERR(halo_alg)) + return PTR_ERR(halo_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, + "%d: ID %x v%d.%d.%d XM@%x YM@%x\n", + i, be32_to_cpu(halo_alg[i].alg.id), + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(halo_alg[i].alg.ver) & 0xff, + be32_to_cpu(halo_alg[i].xm_base), + be32_to_cpu(halo_alg[i].ym_base)); + + ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id, + halo_alg[i].xm_base, + halo_alg[i].ym_base); + if (ret) + goto out; + } + +out: + kfree(halo_alg); + return ret; +} + +static int wm_vpu_setup_algs(struct wm_adsp *vpu) +{ + const struct wm_adsp_region *mem; + struct wmfw_vpu_id_hdr vpu_id; + struct wmfw_vpu_alg_hdr *vpu_alg; + unsigned int pos, len, block_rev; + struct wm_adsp_alg_region *alg_region; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(vpu, WMFW_VPU_DM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = regmap_raw_read(vpu->regmap, mem->base, &vpu_id, sizeof(vpu_id)); + if (ret != 0) { + adsp_err(vpu, "Failed to read algorithm info: %d\n", ret); + return ret; + } + + block_rev = be32_to_cpu(vpu_id.fw.block_rev) >> 16; + switch (block_rev) { + case 3: + break; + default: + adsp_err(vpu, "Unknown firmware ID block version 0x%x\n", + block_rev); + return -EINVAL; + } + + n_algs = be32_to_cpu(vpu_id.n_algs); + + wmfw_v3_parse_id_header(vpu, &vpu_id.fw, n_algs); + + alg_region = wm_adsp_create_region(vpu, WMFW_VPU_DM, + vpu_id.fw.id, + vpu_id.dm_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(vpu_id) / sizeof(u32); + len = (sizeof(*vpu_alg) * n_algs) / sizeof(u32); + + vpu_alg = wm_adsp_read_algs(vpu, n_algs, mem, pos, len); + if (IS_ERR(vpu_alg)) + return PTR_ERR(vpu_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(vpu, "%d: ID %x v%d.%d.%d DM@%x\n", + i, + be32_to_cpu(vpu_alg[i].alg.id), + (be32_to_cpu(vpu_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(vpu_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(vpu_alg[i].alg.ver) & 0xff, + be32_to_cpu(vpu_alg[i].dm_base)); + + alg_region = wm_adsp_create_region(vpu, WMFW_VPU_DM, + vpu_alg[i].alg.id, + vpu_alg[i].dm_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + } + +out: + kfree(vpu_alg); + return ret; +} + +static int wm_adsp_load_coeff(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + struct regmap *regmap = dsp->regmap; + struct wmfw_coeff_hdr *hdr; + struct wmfw_coeff_item *blk; + const struct firmware *firmware; + const struct wm_adsp_region *mem; + struct wm_adsp_alg_region *alg_region; + const char *region_name; + int ret, pos, blocks, type, offset, reg; + char *file; + unsigned int burst_multiple; + + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name, + wm_adsp_fw[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + + ret = request_firmware(&firmware, file, dsp->dev); + if (ret != 0) { + adsp_warn(dsp, "Failed to request '%s'\n", file); + ret = 0; + goto out; + } + ret = -EINVAL; + + if (sizeof(*hdr) >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", + file, firmware->size); + goto out_fw; + } + + hdr = (void *)&firmware->data[0]; + if (memcmp(hdr->magic, "WMDR", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + switch (be32_to_cpu(hdr->rev) & 0xff) { + case 1: + break; + default: + adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", + file, be32_to_cpu(hdr->rev) & 0xff); + ret = -EINVAL; + goto out_fw; + } + + adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, + (le32_to_cpu(hdr->ver) >> 16) & 0xff, + (le32_to_cpu(hdr->ver) >> 8) & 0xff, + le32_to_cpu(hdr->ver) & 0xff); + + pos = le32_to_cpu(hdr->len); + + blocks = 0; + while (pos < firmware->size && + sizeof(*blk) < firmware->size - pos) { + blk = (void *)(&firmware->data[pos]); + + type = le16_to_cpu(blk->type); + offset = le16_to_cpu(blk->offset); + + adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", + file, blocks, le32_to_cpu(blk->id), + (le32_to_cpu(blk->ver) >> 16) & 0xff, + (le32_to_cpu(blk->ver) >> 8) & 0xff, + le32_to_cpu(blk->ver) & 0xff); + adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", + file, blocks, le32_to_cpu(blk->len), offset, type); + + reg = 0; + burst_multiple = 4; + region_name = "Unknown"; + switch (type) { + case (WMFW_NAME_TEXT << 8): + case (WMFW_INFO_TEXT << 8): + case (WMFW_METADATA << 8): + break; + case (WMFW_ABSOLUTE << 8): + /* + * Old files may use this for global + * coefficients. + */ + if (le32_to_cpu(blk->id) == dsp->fw_id && + offset == 0) { + region_name = "global coefficients"; + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No ZM\n"); + break; + } + reg = dsp->ops->region_to_reg(mem, 0); + + } else { + region_name = "register"; + reg = offset; + } + break; + + case WMFW_HALO_PM_PACKED: + burst_multiple += 8; /* plus the 8 below yields 20 */ + /* fall through */ + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + burst_multiple += 8; /* yields 12 */ + /* fall through */ + case WMFW_ADSP1_DM: + case WMFW_ADSP1_ZM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_VPU_DM: + adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", + file, blocks, le32_to_cpu(blk->len), + type, le32_to_cpu(blk->id)); + + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", type); + break; + } + + alg_region = wm_adsp_find_alg_region(dsp, type, + le32_to_cpu(blk->id)); + if (alg_region) { + reg = alg_region->base; + reg = dsp->ops->region_to_reg(mem, reg); + reg += offset; + } else { + adsp_err(dsp, "No %x for algorithm %x\n", + type, le32_to_cpu(blk->id)); + } + break; + + default: + adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", + file, blocks, type, pos); + break; + } + + if (reg) { + if (le32_to_cpu(blk->len) > + firmware->size - pos - sizeof(*blk)) { + adsp_err(dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, blocks, region_name, + le32_to_cpu(blk->len), + firmware->size); + ret = -EINVAL; + goto out_fw; + } + + adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", + file, blocks, le32_to_cpu(blk->len), + reg); + + ret = wm_adsp_write_blocks(dsp, blk->data, + le32_to_cpu(blk->len), + reg, &buf_list, + burst_multiple); + if (ret != 0) { + adsp_err(dsp, + "%s.%d: Failed to write to %x in %s: %d\n", + file, blocks, reg, region_name, ret); + } + } + + pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; + blocks++; + } + + ret = regmap_async_complete(regmap); + if (ret != 0) + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", + file, blocks, pos - firmware->size); + + wm_adsp_debugfs_save_binname(dsp, file); + +out_fw: + regmap_async_complete(regmap); + release_firmware(firmware); + wm_adsp_buf_free(&buf_list); +out: + kfree(file); + return ret; +} + +static int wm_adsp_create_name(struct wm_adsp *dsp) +{ + char *p; + + if (!dsp->name) { + dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", + dsp->num); + if (!dsp->name) + return -ENOMEM; + } + + if (!dsp->fwf_name) { + p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL); + if (!p) + return -ENOMEM; + + dsp->fwf_name = p; + for (; *p != 0; ++p) + *p = tolower(*p); + } + + return 0; +} + +static int wm_adsp_common_init(struct wm_adsp *dsp) +{ + int ret; + + ret = wm_adsp_create_name(dsp); + if (ret) + return ret; + + INIT_LIST_HEAD(&dsp->alg_regions); + INIT_LIST_HEAD(&dsp->ctl_list); + INIT_LIST_HEAD(&dsp->compr_list); + INIT_LIST_HEAD(&dsp->buffer_list); + + mutex_init(&dsp->pwr_lock); + + return 0; +} + +int wm_adsp1_init(struct wm_adsp *dsp) +{ + dsp->ops = &wm_adsp1_ops; + + return wm_adsp_common_init(dsp); +} +EXPORT_SYMBOL_GPL(wm_adsp1_init); + +int wm_adsp1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + int ret; + unsigned int val; + + dsp->component = component; + + mutex_lock(&dsp->pwr_lock); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, ADSP1_SYS_ENA); + + /* + * For simplicity set the DSP clock rate to be the + * SYSCLK rate rather than making it configurable. + */ + if (dsp->sysclk_reg) { + ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); + if (ret != 0) { + adsp_err(dsp, "Failed to read SYSCLK state: %d\n", + ret); + goto err_mutex; + } + + val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; + + ret = regmap_update_bits(dsp->regmap, + dsp->base + ADSP1_CONTROL_31, + ADSP1_CLK_SEL_MASK, val); + if (ret != 0) { + adsp_err(dsp, "Failed to set clock rate: %d\n", + ret); + goto err_mutex; + } + } + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp1_setup_algs(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err_ena; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err_ena; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err_ena; + + dsp->booted = true; + + /* Start the core running */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, + ADSP1_CORE_ENA | ADSP1_START); + + dsp->running = true; + break; + + case SND_SOC_DAPM_PRE_PMD: + dsp->running = false; + dsp->booted = false; + + /* Halt the core */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, + ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); + + list_for_each_entry(ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + + wm_adsp_free_alg_regions(dsp); + break; + + default: + break; + } + + mutex_unlock(&dsp->pwr_lock); + + return 0; + +err_ena: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); +err_mutex: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp1_event); + +static int wm_adsp2v2_enable_core(struct wm_adsp *dsp) +{ + unsigned int val; + int ret, count; + + /* Wait for the RAM to start, should be near instantaneous */ + for (count = 0; count < 10; ++count) { + ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); + if (ret != 0) + return ret; + + if (val & ADSP2_RAM_RDY) + break; + + usleep_range(250, 500); + } + + if (!(val & ADSP2_RAM_RDY)) { + adsp_err(dsp, "Failed to start DSP RAM\n"); + return -EBUSY; + } + + adsp_dbg(dsp, "RAM ready after %d polls\n", count); + + return 0; +} + +static int wm_adsp2_enable_core(struct wm_adsp *dsp) +{ + int ret; + + ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, ADSP2_SYS_ENA); + if (ret != 0) + return ret; + + return wm_adsp2v2_enable_core(dsp); +} + +static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions) +{ + struct regmap *regmap = dsp->regmap; + unsigned int code0, code1, lock_reg; + + if (!(lock_regions & WM_ADSP2_REGION_ALL)) + return 0; + + lock_regions &= WM_ADSP2_REGION_ALL; + lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; + + while (lock_regions) { + code0 = code1 = 0; + if (lock_regions & BIT(0)) { + code0 = ADSP2_LOCK_CODE_0; + code1 = ADSP2_LOCK_CODE_1; + } + if (lock_regions & BIT(1)) { + code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT; + code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT; + } + regmap_write(regmap, lock_reg, code0); + regmap_write(regmap, lock_reg, code1); + lock_regions >>= 2; + lock_reg += 2; + } + + return 0; +} + +static int wm_adsp2_enable_memory(struct wm_adsp *dsp) +{ + return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, ADSP2_MEM_ENA); +} + +static void wm_adsp2_disable_memory(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); +} + +static void wm_adsp2_disable_core(struct wm_adsp *dsp) +{ + regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, 0); +} + +static void wm_adsp2v2_disable_core(struct wm_adsp *dsp) +{ + regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); +} + +static void wm_adsp_boot_work(struct work_struct *work) +{ + struct wm_adsp *dsp = container_of(work, + struct wm_adsp, + boot_work); + int ret; + + mutex_lock(&dsp->pwr_lock); + + if (dsp->ops->enable_memory) { + ret = dsp->ops->enable_memory(dsp); + if (ret != 0) + goto err_mutex; + } + + if (dsp->ops->enable_core) { + ret = dsp->ops->enable_core(dsp); + if (ret != 0) + goto err_mem; + } + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err_ena; + + ret = dsp->ops->setup_algs(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err_ena; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err_ena; + + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); + + dsp->booted = true; + + mutex_unlock(&dsp->pwr_lock); + + return; + +err_ena: + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); +err_mem: + if (dsp->ops->disable_memory) + dsp->ops->disable_memory(dsp); +err_mutex: + mutex_unlock(&dsp->pwr_lock); +} + +static int wm_halo_set_rate_block(struct wm_adsp *dsp, + unsigned int rate_base, + unsigned int n_rates, + const u8 *rate_cache) +{ + unsigned int addr = dsp->base + rate_base, val; + int ret, i; + + mutex_lock(dsp->rate_lock); + + for (i = 0; i < n_rates; ++i) { + val = rate_cache[i] << HALO_DSP_RATE_SHIFT; + + ret = regmap_update_bits(dsp->regmap, + addr + (i * 8), + HALO_DSP_RATE_MASK, + val); + if (ret) { + adsp_err(dsp, "Failed to set rate: %d\n", ret); + mutex_unlock(dsp->rate_lock); + return ret; + } + + adsp_dbg(dsp, "Set rate %d to 0x%x\n", i, val); + } + + udelay(300); + + mutex_unlock(dsp->rate_lock); + + return 0; +} + +static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions) +{ + struct reg_sequence config[] = { + { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, + { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, + { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, + { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, + { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, + { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, + { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, + }; + + return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); +} + +int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret; + + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, + ADSP2_CLK_SEL_MASK, + freq << ADSP2_CLK_SEL_SHIFT); + if (ret) + adsp_err(dsp, "Failed to set clock rate: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk); + +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct wm_adsp *dsp = &dsps[mc->shift - 1]; + + ucontrol->value.integer.value[0] = dsp->preloaded; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get); + +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct wm_adsp *dsp = &dsps[mc->shift - 1]; + char preload[32]; + + snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); + + dsp->preloaded = ucontrol->value.integer.value[0]; + + if (ucontrol->value.integer.value[0]) + snd_soc_component_force_enable_pin(component, preload); + else + snd_soc_component_disable_pin(component, preload); + + snd_soc_dapm_sync(dapm); + + flush_work(&dsp->boot_work); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put); + +static void wm_adsp_stop_watchdog(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, + ADSP2_WDT_ENA_MASK, 0); +} + +static void wm_halo_stop_watchdog(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, + HALO_WDT_EN_MASK, 0); +} + +int wm_adsp_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + queue_work(system_unbound_wq, &dsp->boot_work); + break; + case SND_SOC_DAPM_PRE_PMD: + mutex_lock(&dsp->pwr_lock); + + wm_adsp_debugfs_clear(dsp); + + dsp->fw_id = 0; + dsp->fw_id_version = 0; + + dsp->booted = false; + + if (dsp->ops->disable_memory) + dsp->ops->disable_memory(dsp); + + list_for_each_entry(ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Shutdown complete\n"); + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_early_event); + +static int wm_adsp2_start_core(struct wm_adsp *dsp) +{ + return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, + ADSP2_CORE_ENA | ADSP2_START); +} + +static void wm_adsp2_stop_core(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, 0); +} + +static int wm_halo_apply_calibration(struct snd_soc_dapm_widget *w) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret, val; + + adsp_dbg(dsp, "%s: dsp->fw=%d, dsp->ambient=%d, dsp->cal_z=%d, dsp->cal_status=%d, dsp->cal_chksum=%d\n", __func__, dsp->fw, dsp->ambient, dsp->cal_z, dsp->cal_status, dsp->cal_chksum); + + switch(dsp->fw) { + case WM_ADSP_FW_CALIB: + case WM_ADSP_FW_DIAG: + val = cpu_to_be32(dsp->ambient); + ret = wm_adsp_write_ctl(dsp, "CAL_AMBIENT", WMFW_ADSP2_XM, CS35L45_ALGID, (void *)&val, sizeof(__be32)); + if (ret) + adsp_warn(dsp, "%s: Write CAL_AMBIENT, ret=%d\n", __func__, ret); + break; + case WM_ADSP_FW_SPK_PROT: + val = cpu_to_be32(dsp->cal_z); + ret = wm_adsp_write_ctl(dsp, "CAL_R", WMFW_ADSP2_XM, CS35L45_ALGID, (void *)&val, sizeof(__be32)); + if (ret) + adsp_warn(dsp, "%s: Write CAL_R, ret=%d\n", __func__, ret); + + val = cpu_to_be32(dsp->cal_status); + ret = wm_adsp_write_ctl(dsp, "CAL_STATUS", WMFW_ADSP2_XM, CS35L45_ALGID, (void *)&val, sizeof(__be32)); + if (ret) + adsp_warn(dsp, "%s: Write CAL_STATUS ret=%d\n", __func__, ret); + + val = cpu_to_be32(dsp->cal_chksum); + ret = wm_adsp_write_ctl(dsp, "CAL_CHECKSUM", WMFW_ADSP2_XM, CS35L45_ALGID, (void *)&val, sizeof(__be32)); + if (ret) + adsp_warn(dsp, "%s: Write CAL_CHECKSUM ret=%d\n", __func__, ret); + + #if 0 // DC detection + val = cpu_to_be32(150); + ret = wm_adsp_write_ctl(dsp, "DC_OFFSET_HOLD_TIME", WMFW_ADSP2_XM, CS35L45_ALGID, (void *)&val, sizeof(__be32)); + if (ret) + adsp_warn(dsp, "%s: Write DC_OFFSET_HOLD_TIME ret=%d\n", __func__, ret); + #endif + break; + default: + adsp_warn(dsp, "Do thing'\n"); + break; + } + + return 0; +} + +int wm_adsp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + flush_work(&dsp->boot_work); + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->booted) { + ret = -EIO; + goto err; + } + + if (dsp->ops->enable_core) { + ret = dsp->ops->enable_core(dsp); + if (ret != 0) + goto err; + } + + wm_halo_apply_calibration(w); + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; + + if (dsp->ops->lock_memory) { + ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); + if (ret != 0) { + adsp_err(dsp, "Error configuring MPU: %d\n", + ret); + goto err; + } + } + + if (dsp->ops->start_core) { + ret = dsp->ops->start_core(dsp); + if (ret != 0) + goto err; + } + + if (wm_adsp_fw[dsp->fw].num_caps != 0) { + ret = wm_adsp_buffer_init(dsp); + if (ret < 0) + goto err; + } + + dsp->running = true; + + mutex_unlock(&dsp->pwr_lock); + adsp_dbg(dsp, "Execution started\n"); + break; + + case SND_SOC_DAPM_PRE_PMD: + /* Tell the firmware to cleanup */ + wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); + + if (dsp->ops->stop_watchdog) + dsp->ops->stop_watchdog(dsp); + + /* Log firmware state, it can be useful for analysis */ + if (dsp->ops->show_fw_status) + dsp->ops->show_fw_status(dsp); + + mutex_lock(&dsp->pwr_lock); + + dsp->running = false; + + if (dsp->ops->stop_core) + dsp->ops->stop_core(dsp); + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); + + if (wm_adsp_fw[dsp->fw].num_caps != 0) + wm_adsp_buffer_free(dsp); + + dsp->fatal_error = false; + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Execution stopped\n"); + break; + + default: + break; + } + + return 0; +err: + if (dsp->ops->stop_core) + dsp->ops->stop_core(dsp); + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); + mutex_unlock(&dsp->pwr_lock); + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_event); + +static int wm_halo_start_core(struct wm_adsp *dsp) +{ + int ret; + + adsp_dbg(dsp, "Setting RX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_RX1, + dsp->n_rx_channels, + dsp->rx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set RX rates.\n"); + return ret; + } + + adsp_dbg(dsp, "Setting TX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_TX1, + dsp->n_tx_channels, + dsp->tx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set TX rates.\n"); + return ret; + } + + return regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, HALO_CORE_EN); +} + +static void wm_halo_stop_core(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, 0); + + /* reset halo core with CORE_SOFT_RESET */ + regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, + HALO_CORE_SOFT_RESET_MASK, 1); +} + +static int wm_adsp_cal_z_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->cal_z; + adsp_dbg(dsp, "get cal_z = %d\n", ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_cal_z_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->cal_z = ucontrol->value.enumerated.item[0]; + dsp->cal_chksum = dsp->cal_z + CAL_STATUS_DEFAULT; + + adsp_dbg(dsp, "put cal_z = %d, cal_checksum = %d\n", dsp->cal_z, dsp->cal_chksum); + + return 0; +} + +static int wm_adsp_ambient_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->ambient; + adsp_dbg(dsp, "get ambient = %d\n", ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_ambient_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->ambient = ucontrol->value.enumerated.item[0]; + + adsp_dbg(dsp, "put ambient = %d\n", dsp->ambient); + + return 0; +} + +static int wm_adsp_cal_status_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->cal_status; + adsp_dbg(dsp, "get calib status = %d\n", ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_cal_status_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->cal_status = ucontrol->value.enumerated.item[0]; + + adsp_dbg(dsp, "put calib status = %d\n", dsp->cal_status); + + return 0; +} + +static int wm_adsp_cal_chksum_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->cal_chksum; + adsp_dbg(dsp, "get calib checksum = %d\n", ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_cal_chksum_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->cal_chksum = ucontrol->value.enumerated.item[0]; + + adsp_dbg(dsp, "put calib checksum = %d\n", dsp->cal_chksum); + + return 0; +} + +const struct snd_kcontrol_new wm_adsp_cal_controls[] = { + /* In Halo DSP, values are 24-bit */ + SOC_SINGLE_EXT("DSP Set CAL_Z", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_z_get, wm_adsp_cal_z_put), + SOC_SINGLE_EXT("DSP Set AMBIENT", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_ambient_get, wm_adsp_ambient_put), + SOC_SINGLE_EXT("DSP Set CAL_STATUS", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_status_get, wm_adsp_cal_status_put), + SOC_SINGLE_EXT("DSP Set CAL_CHKSUM", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_chksum_get, wm_adsp_cal_chksum_put), +}; +EXPORT_SYMBOL_GPL(wm_adsp_cal_controls); + +int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component) +{ + char preload[32]; + + if (!dsp->no_preloader) { + snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); + snd_soc_component_disable_pin(component, preload); + } + + wm_adsp2_init_debugfs(dsp, component); + + dsp->component = component; + + snd_soc_add_component_controls(component, wm_adsp_cal_controls, ARRAY_SIZE(wm_adsp_cal_controls)); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_component_probe); + +int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component) +{ + wm_adsp2_cleanup_debugfs(dsp); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_component_remove); + +int wm_adsp2_init(struct wm_adsp *dsp) +{ + int ret; + + ret = wm_adsp_common_init(dsp); + if (ret) + return ret; + + switch (dsp->rev) { + case 0: + /* + * Disable the DSP memory by default when in reset for a small + * power saving. + */ + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); + if (ret) { + adsp_err(dsp, + "Failed to clear memory retention: %d\n", ret); + return ret; + } + + dsp->ops = &wm_adsp2_ops[0]; + break; + case 1: + dsp->ops = &wm_adsp2_ops[1]; + break; + default: + dsp->ops = &wm_adsp2_ops[2]; + break; + } + + INIT_WORK(&dsp->boot_work, wm_adsp_boot_work); + + dsp->data_word_size = WM_ADSP_DATA_WORD_SIZE_DEFAULT; + dsp->data_word_mask = WM_ADSP_DATA_WORD_MASK_DEFAULT; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_init); + +int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock) +{ + int ret; + + ret = wm_adsp_common_init(dsp); + if (ret) + return ret; + + dsp->ops = &wm_halo_ops; + + INIT_WORK(&dsp->boot_work, wm_adsp_boot_work); + + dsp->rate_lock = rate_lock; + dsp->rx_rate_cache = kcalloc(dsp->n_rx_channels, sizeof(u8), + GFP_KERNEL); + dsp->tx_rate_cache = kcalloc(dsp->n_tx_channels, sizeof(u8), + GFP_KERNEL); + + dsp->data_word_size = WM_ADSP_DATA_WORD_SIZE_DEFAULT; + dsp->data_word_mask = WM_ADSP_DATA_WORD_MASK_DEFAULT; + + // Preset speaker calibration default value + dsp->ambient = AMBIENT_DEFAULT; + dsp->cal_z = CAL_R_DEFAULT; + dsp->cal_status = CAL_STATUS_DEFAULT; + dsp->cal_chksum = CAL_R_DEFAULT + CAL_STATUS_DEFAULT; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_halo_init); + +int wm_vpu_init(struct wm_adsp *vpu) +{ + int ret; + + ret = wm_adsp_common_init(vpu); + if (ret) + return ret; + + vpu->ops = &wm_vpu_ops; + + INIT_WORK(&vpu->boot_work, wm_adsp_boot_work); + + vpu->data_word_size = WM_ADSP_DATA_WORD_SIZE_VPU; + vpu->data_word_mask = WM_ADSP_DATA_WORD_MASK_VPU; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_vpu_init); + +void wm_adsp2_remove(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + + while (!list_empty(&dsp->ctl_list)) { + ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl, + list); + list_del(&ctl->list); + wm_adsp_free_ctl_blk(ctl); + } + + kfree(dsp->rx_rate_cache); + kfree(dsp->tx_rate_cache); +} +EXPORT_SYMBOL_GPL(wm_adsp2_remove); + +static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr) +{ + return compr->buf != NULL; +} + +static int wm_adsp_compr_attach(struct wm_adsp_compr *compr) +{ + struct wm_adsp_compr_buf *buf = NULL, *tmp; + + if (compr->dsp->fatal_error) + return -EINVAL; + + list_for_each_entry(tmp, &compr->dsp->buffer_list, list) { + if (!tmp->name || !strcmp(compr->name, tmp->name)) { + buf = tmp; + break; + } + } + + if (!buf) + return -EINVAL; + + compr->buf = buf; + buf->compr = compr; + + return 0; +} + +static void wm_adsp_compr_detach(struct wm_adsp_compr *compr) +{ + if (!compr) + return; + + /* Wake the poll so it can see buffer is no longer attached */ + if (compr->stream) + snd_compr_fragment_elapsed(compr->stream); + + if (wm_adsp_compr_attached(compr)) { + compr->buf->compr = NULL; + compr->buf = NULL; + } +} + +int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream) +{ + struct wm_adsp_compr *compr, *tmp; + struct snd_soc_pcm_runtime *rtd = stream->private_data; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + if (wm_adsp_fw[dsp->fw].num_caps == 0) { + adsp_err(dsp, "%s: Firmware does not support compressed API\n", + rtd->codec_dai->name); + ret = -ENXIO; + goto out; + } + + if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) { + adsp_err(dsp, "%s: Firmware does not support stream direction\n", + rtd->codec_dai->name); + ret = -EINVAL; + goto out; + } + + list_for_each_entry(tmp, &dsp->compr_list, list) { + if (!strcmp(tmp->name, rtd->codec_dai->name)) { + adsp_err(dsp, "%s: Only a single stream supported per dai\n", + rtd->codec_dai->name); + ret = -EBUSY; + goto out; + } + } + + compr = kzalloc(sizeof(*compr), GFP_KERNEL); + if (!compr) { + ret = -ENOMEM; + goto out; + } + + compr->dsp = dsp; + compr->stream = stream; + compr->name = rtd->codec_dai->name; + + list_add_tail(&compr->list, &dsp->compr_list); + + stream->runtime->private_data = compr; + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_open); + +int wm_adsp_compr_free(struct snd_compr_stream *stream) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + + mutex_lock(&dsp->pwr_lock); + + wm_adsp_compr_detach(compr); + list_del(&compr->list); + + kfree(compr->raw_buf); + kfree(compr); + + mutex_unlock(&dsp->pwr_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_free); + +static int wm_adsp_compr_check_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + const struct wm_adsp_fw_caps *caps; + const struct snd_codec_desc *desc; + int i, j; + + if (params->buffer.fragment_size < (WM_ADSP_MIN_FRAGMENT_SIZE_WORDS + * dsp->data_word_size) || + params->buffer.fragment_size > (WM_ADSP_MAX_FRAGMENT_SIZE_WORDS + * dsp->data_word_size) || + params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS || + params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS || + params->buffer.fragment_size % dsp->data_word_size) { + compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n", + params->buffer.fragment_size, + params->buffer.fragments); + + return -EINVAL; + } + + for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) { + caps = &wm_adsp_fw[dsp->fw].caps[i]; + desc = &caps->desc; + + if (caps->id != params->codec.id) + continue; + + if (stream->direction == SND_COMPRESS_PLAYBACK) { + if (desc->max_ch < params->codec.ch_out) + continue; + } else { + if (desc->max_ch < params->codec.ch_in) + continue; + } + + if (!(desc->formats & (1 << params->codec.format))) + continue; + + for (j = 0; j < desc->num_sample_rates; ++j) + if (desc->sample_rates[j] == params->codec.sample_rate) + return 0; + } + + compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n", + params->codec.id, params->codec.ch_in, params->codec.ch_out, + params->codec.sample_rate, params->codec.format); + return -EINVAL; +} + +static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr) +{ + return compr->size.fragment_size / compr->dsp->data_word_size; +} + +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + unsigned int size; + int ret; + + ret = wm_adsp_compr_check_params(stream, params); + if (ret) + return ret; + + compr->size = params->buffer; + + compr_dbg(compr, "fragment_size=%d fragments=%d\n", + compr->size.fragment_size, compr->size.fragments); + + size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf); + compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL); + if (!compr->raw_buf) + return -ENOMEM; + + compr->sample_rate = params->codec.sample_rate; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params); + +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int fw = compr->dsp->fw; + int i; + + if (wm_adsp_fw[fw].caps) { + for (i = 0; i < wm_adsp_fw[fw].num_caps; i++) + caps->codecs[i] = wm_adsp_fw[fw].caps[i].id; + + caps->num_codecs = i; + caps->direction = wm_adsp_fw[fw].compr_direction; + + caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE_WORDS + * dsp->data_word_size; + caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE_WORDS + * dsp->data_word_size; + caps->min_fragments = WM_ADSP_MIN_FRAGMENTS; + caps->max_fragments = WM_ADSP_MAX_FRAGMENTS; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps); + +static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, + unsigned int num_words, u32 *data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); + unsigned int i, reg; + unsigned int data_word_mask = dsp->data_word_mask; + int ret; + + if (!mem) + return -EINVAL; + + reg = dsp->ops->region_to_reg(mem, mem_addr); + + ret = regmap_raw_read(dsp->regmap, reg, data, + sizeof(*data) * num_words); + if (ret < 0) + return ret; + + for (i = 0; i < num_words; ++i) + data[i] = be32_to_cpu(data[i]) & data_word_mask; + + return 0; +} + +static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 *data) +{ + return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data); +} + +static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); + unsigned int reg; + + if (!mem) + return -EINVAL; + + reg = dsp->ops->region_to_reg(mem, mem_addr); + + data = cpu_to_be32(data & dsp->data_word_mask); + + return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data)); +} + +static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 *data) +{ + return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type, + buf->host_buf_ptr + field_offset, data); +} + +static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 data) +{ + return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type, + buf->host_buf_ptr + field_offset, data); +} + +static void wm_adsp_remove_padding(u32 *buf, int nwords, int data_word_size) +{ + u8 *pack_in = (u8 *)buf; + u8 *pack_out = (u8 *)buf; + int i, j; + + /* Remove the padding bytes from the data read from the DSP */ + for (i = 0; i < nwords; i++) { + for (j = 0; j < data_word_size; j++) + *pack_out++ = *pack_in++; + + pack_in += sizeof(*buf) - data_word_size; + } +} + +static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf) +{ + struct wm_adsp_buffer_region *region; + u32 offset = 0; + int i, ret; + + switch (buf->dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + case WMFW_HALO: + buf->num_regions = ARRAY_SIZE(default_regions); + buf->region_defs = default_regions; + break; + case WMFW_VPU: + buf->num_regions = ARRAY_SIZE(vpu_regions); + buf->region_defs = vpu_regions; + break; + default: + return -EINVAL; + } + + buf->regions = kcalloc(buf->num_regions, sizeof(*buf->regions), + GFP_KERNEL); + if (!buf->regions) + return -ENOMEM; + + for (i = 0; i < buf->num_regions; ++i) { + region = &buf->regions[i]; + + region->offset = offset; + region->mem_type = buf->region_defs[i].mem_type; + + ret = wm_adsp_buffer_read(buf, buf->region_defs[i].base_offset, + ®ion->base_addr); + if (ret < 0) + return ret; + + ret = wm_adsp_buffer_read(buf, buf->region_defs[i].size_offset, + &offset); + if (ret < 0) + return ret; + + region->cumulative_size = offset; + + compr_dbg(buf, + "region=%d type=%d base=%08x off=%08x size=%08x\n", + i, region->mem_type, region->base_addr, + region->offset, region->cumulative_size); + } + + return 0; +} + +static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf) +{ + buf->irq_count = 0xFFFFFFFF; + buf->read_index = -1; + buf->avail = 0; +} + +static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf; + + buf = kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) + return NULL; + + buf->dsp = dsp; + + wm_adsp_buffer_clear(buf); + + list_add_tail(&buf->list, &dsp->buffer_list); + + return buf; +} + +static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp) +{ + struct wm_adsp_alg_region *alg_region; + struct wm_adsp_compr_buf *buf; + u32 xmalg, addr, magic; + int i, ret; + + alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id); + if (!alg_region) { + adsp_err(dsp, "No algorithm region found\n"); + return -EINVAL; + } + + buf = wm_adsp_buffer_alloc(dsp); + if (!buf) + return -ENOMEM; + + xmalg = dsp->ops->sys_config_size / sizeof(__be32); + + addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic); + if (ret < 0) + return ret; + + if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC) + return -ENODEV; + + addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr); + for (i = 0; i < 5; ++i) { + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, + &buf->host_buf_ptr); + if (ret < 0) + return ret; + + if (buf->host_buf_ptr) + break; + + usleep_range(1000, 2000); + } + + if (!buf->host_buf_ptr) + return -EIO; + + buf->host_buf_mem_type = WMFW_ADSP2_XM; + + ret = wm_adsp_buffer_populate(buf); + if (ret < 0) + return ret; + + compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr); + + return 0; +} + +static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl) +{ + struct wm_adsp_host_buf_coeff_v1 coeff_v1; + struct wm_adsp_compr_buf *buf; + unsigned int val, reg; + int ret, i; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + for (i = 0; i < 5; ++i) { + ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val)); + if (ret < 0) + return ret; + + if (val) + break; + + usleep_range(1000, 2000); + } + + if (!val) { + adsp_err(ctl->dsp, "Failed to acquire host buffer\n"); + return -EIO; + } + + buf = wm_adsp_buffer_alloc(ctl->dsp); + if (!buf) + return -ENOMEM; + + buf->host_buf_mem_type = ctl->alg_region.type; + buf->host_buf_ptr = be32_to_cpu(val); + + ret = wm_adsp_buffer_populate(buf); + if (ret < 0) + return ret; + + /* + * v0 host_buffer coefficients didn't have versioning, so if the + * control is one word, assume version 0. + */ + if (ctl->len == 4) { + compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr); + return 0; + } + + ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1, + sizeof(coeff_v1)); + if (ret < 0) + return ret; + + coeff_v1.versions = be32_to_cpu(coeff_v1.versions); + val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK; + val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT; + + if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) { + adsp_err(ctl->dsp, + "Host buffer coeff ver %u > supported version %u\n", + val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(coeff_v1.name); i++) + coeff_v1.name[i] = be32_to_cpu(coeff_v1.name[i]); + + wm_adsp_remove_padding((u32 *)&coeff_v1.name, + ARRAY_SIZE(coeff_v1.name), + ctl->dsp->data_word_size); + + buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part, + (char *)&coeff_v1.name); + + compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n", + buf->host_buf_ptr, val); + + return val; +} + +static int wm_adsp_buffer_init(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER) + continue; + + if (!ctl->enabled) + continue; + + ret = wm_adsp_buffer_parse_coeff(ctl); + if (ret < 0) { + adsp_err(dsp, "Failed to parse coeff: %d\n", ret); + goto error; + } else if (ret == 0) { + /* Only one buffer supported for version 0 */ + return 0; + } + } + + if (list_empty(&dsp->buffer_list)) { + /* Fall back to legacy support */ + ret = wm_adsp_buffer_parse_legacy(dsp); + if (ret) { + adsp_err(dsp, "Failed to parse legacy: %d\n", ret); + goto error; + } + } + + return 0; + +error: + wm_adsp_buffer_free(dsp); + return ret; +} + +static int wm_adsp_buffer_free(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf, *tmp; + + list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) { + wm_adsp_compr_detach(buf->compr); + + kfree(buf->name); + kfree(buf->regions); + list_del(&buf->list); + kfree(buf); + } + + return 0; +} + +static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf) +{ + int ret; + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error); + if (ret < 0) { + compr_err(buf, "Failed to check buffer error: %d\n", ret); + return ret; + } + if (buf->error != 0) { + compr_err(buf, "Buffer error occurred: %d\n", buf->error); + return -EIO; + } + + return 0; +} + +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int ret = 0; + + compr_dbg(compr, "Trigger: %d\n", cmd); + + mutex_lock(&dsp->pwr_lock); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (!wm_adsp_compr_attached(compr)) { + ret = wm_adsp_compr_attach(compr); + if (ret < 0) { + compr_err(compr, "Failed to link buffer and stream: %d\n", + ret); + break; + } + } + + ret = wm_adsp_buffer_get_error(compr->buf); + if (ret < 0) + break; + + /* Trigger the IRQ at one fragment of data */ + ret = wm_adsp_buffer_write(compr->buf, + HOST_BUFFER_FIELD(high_water_mark), + wm_adsp_compr_frag_words(compr)); + if (ret < 0) { + compr_err(compr, "Failed to set high water mark: %d\n", + ret); + break; + } + break; + case SNDRV_PCM_TRIGGER_STOP: + if (wm_adsp_compr_attached(compr)) + wm_adsp_buffer_clear(compr->buf); + break; + default: + ret = -EINVAL; + break; + } + + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger); + +static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf) +{ + int last_region = buf->num_regions - 1; + + return buf->regions[last_region].cumulative_size; +} + +static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf) +{ + u32 next_read_index, next_write_index; + int write_index, read_index, avail; + int ret; + + /* Only sync read index if we haven't already read a valid index */ + if (buf->read_index < 0) { + ret = wm_adsp_buffer_read(buf, + HOST_BUFFER_FIELD(next_read_index), + &next_read_index); + if (ret < 0) + return ret; + + read_index = sign_extend32(next_read_index, 23); + + if (read_index < 0) { + compr_dbg(buf, "Avail check on unstarted stream\n"); + return 0; + } + + buf->read_index = read_index; + } + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index), + &next_write_index); + if (ret < 0) + return ret; + + write_index = sign_extend32(next_write_index, 23); + + avail = write_index - buf->read_index; + if (avail < 0) + avail += wm_adsp_buffer_size(buf); + + compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n", + buf->read_index, write_index, avail * buf->dsp->data_word_size); + + buf->avail = avail; + + return 0; +} + +int wm_adsp_compr_handle_irq(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf; + struct wm_adsp_compr *compr; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + if (list_empty(&dsp->buffer_list)) { + ret = -ENODEV; + goto out; + } + + adsp_dbg(dsp, "Handling buffer IRQ\n"); + + list_for_each_entry(buf, &dsp->buffer_list, list) { + compr = buf->compr; + + ret = wm_adsp_buffer_get_error(buf); + if (ret < 0) + goto out_notify; /* Wake poll to report error */ + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count), + &buf->irq_count); + if (ret < 0) { + compr_err(buf, "Failed to get irq_count: %d\n", ret); + goto out; + } + + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + compr_err(buf, "Error reading avail: %d\n", ret); + goto out; + } + + if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2) + ret = WM_ADSP_COMPR_VOICE_TRIGGER; + +out_notify: + if (compr && compr->stream) + snd_compr_fragment_elapsed(compr->stream); + } + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq); + +static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf) +{ + int ret; + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count), + &buf->irq_count); + if (ret < 0) + adsp_err(buf->dsp, "Failed to get irq_count: %d\n", ret); + + if (buf->irq_count & 0x01) + return 0; + + compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count); + + buf->irq_count |= 0x01; + + return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack), + buf->irq_count); +} + +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + struct wm_adsp_compr_buf *buf; + int ret = 0; + + compr_dbg(compr, "Pointer request\n"); + + mutex_lock(&dsp->pwr_lock); + + buf = compr->buf; + + if (dsp->fatal_error || !buf || buf->error) { + snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN); + ret = -EIO; + goto out; + } + + if (buf->avail < wm_adsp_compr_frag_words(compr)) { + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + compr_err(compr, "Error reading avail: %d\n", ret); + goto out; + } + + /* + * If we really have less than 1 fragment available tell the + * DSP to inform us once a whole fragment is available. + */ + if (buf->avail < wm_adsp_compr_frag_words(compr)) { + ret = wm_adsp_buffer_get_error(buf); + if (ret < 0) { + if (buf->error) + snd_compr_stop_error(stream, + SNDRV_PCM_STATE_XRUN); + goto out; + } + + ret = wm_adsp_buffer_reenable_irq(buf); + if (ret < 0) { + compr_err(compr, "Failed to re-enable buffer IRQ: %d\n", + ret); + goto out; + } + } + } + + tstamp->copied_total = compr->copied_total; + tstamp->copied_total += buf->avail * dsp->data_word_size; + tstamp->sampling_rate = compr->sample_rate; + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); + +static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) +{ + struct wm_adsp_compr_buf *buf = compr->buf; + unsigned int adsp_addr; + int mem_type, nwords, max_read; + int i, ret; + int data_word_size = buf->dsp->data_word_size; + + /* Calculate read parameters */ + for (i = 0; i < buf->num_regions; ++i) + if (buf->read_index < buf->regions[i].cumulative_size) + break; + + if (i == buf->num_regions) + return -EINVAL; + + mem_type = buf->regions[i].mem_type; + adsp_addr = buf->regions[i].base_addr + + (buf->read_index - buf->regions[i].offset); + + max_read = wm_adsp_compr_frag_words(compr); + nwords = buf->regions[i].cumulative_size - buf->read_index; + + if (nwords > target) + nwords = target; + if (nwords > buf->avail) + nwords = buf->avail; + if (nwords > max_read) + nwords = max_read; + if (!nwords) + return 0; + + /* Read data from DSP */ + ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr, + nwords, compr->raw_buf); + if (ret < 0) + return ret; + + wm_adsp_remove_padding(compr->raw_buf, nwords, data_word_size); + + /* update read index to account for words read */ + buf->read_index += nwords; + if (buf->read_index == wm_adsp_buffer_size(buf)) + buf->read_index = 0; + + ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index), + buf->read_index); + if (ret < 0) + return ret; + + /* update avail to account for words read */ + buf->avail -= nwords; + + return nwords; +} + +static int wm_adsp_compr_read(struct wm_adsp_compr *compr, + char __user *buf, size_t count) +{ + struct wm_adsp *dsp = compr->dsp; + int ntotal = 0; + int nwords, nbytes; + + compr_dbg(compr, "Requested read of %zu bytes\n", count); + + if (dsp->fatal_error || !compr->buf || compr->buf->error) { + snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN); + return -EIO; + } + + count /= dsp->data_word_size; + + do { + nwords = wm_adsp_buffer_capture_block(compr, count); + if (nwords < 0) { + compr_err(compr, "Failed to capture block: %d\n", + nwords); + return nwords; + } + + nbytes = nwords * dsp->data_word_size; + + compr_dbg(compr, "Read %d bytes\n", nbytes); + + if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) { + compr_err(compr, "Failed to copy data to user: %d, %d\n", + ntotal, nbytes); + return -EFAULT; + } + + count -= nwords; + ntotal += nbytes; + } while (nwords > 0 && count > 0); + + compr->copied_total += ntotal; + + return ntotal; +} + +int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf, + size_t count) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int ret; + + mutex_lock(&dsp->pwr_lock); + + if (stream->direction == SND_COMPRESS_CAPTURE) + ret = wm_adsp_compr_read(compr, buf, count); + else + ret = -ENOTSUPP; + + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_copy); + +static void wm_adsp_fatal_error(struct wm_adsp *dsp) +{ + struct wm_adsp_compr *compr; + + dsp->fatal_error = true; + + list_for_each_entry(compr, &dsp->compr_list, list) { + if (compr->stream) + snd_compr_fragment_elapsed(compr->stream); + } +} + +irqreturn_t wm_adsp2_bus_error(int irq, void *data) +{ + struct wm_adsp *dsp = (struct wm_adsp *)data; + unsigned int val; + struct regmap *regmap = dsp->regmap; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); + if (ret) { + adsp_err(dsp, + "Failed to read Region Lock Ctrl register: %d\n", ret); + goto error; + } + + if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { + adsp_err(dsp, "watchdog timeout error\n"); + dsp->ops->stop_watchdog(dsp); + wm_adsp_fatal_error(dsp); + } + + if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { + if (val & ADSP2_SLAVE_ERR_MASK) + adsp_err(dsp, "bus error: slave error\n"); + else + adsp_err(dsp, "bus error: region lock error\n"); + + ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); + if (ret) { + adsp_err(dsp, + "Failed to read Bus Err Addr register: %d\n", + ret); + goto error; + } + + adsp_err(dsp, "bus error address = 0x%x\n", + val & ADSP2_BUS_ERR_ADDR_MASK); + + ret = regmap_read(regmap, + dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + &val); + if (ret) { + adsp_err(dsp, + "Failed to read Pmem Xmem Err Addr register: %d\n", + ret); + goto error; + } + + adsp_err(dsp, "xmem error address = 0x%x\n", + val & ADSP2_XMEM_ERR_ADDR_MASK); + adsp_err(dsp, "pmem error address = 0x%x\n", + (val & ADSP2_PMEM_ERR_ADDR_MASK) >> + ADSP2_PMEM_ERR_ADDR_SHIFT); + } + + regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, + ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); + +error: + mutex_unlock(&dsp->pwr_lock); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_adsp2_bus_error); + +irqreturn_t wm_halo_bus_error(int irq, void *data) +{ + struct wm_adsp *dsp = (struct wm_adsp *)data; + struct regmap *regmap = dsp->regmap; + unsigned int fault[6]; + struct reg_sequence clear[] = { + { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, + { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, + { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, + }; + int ret; + + mutex_lock(&dsp->pwr_lock); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, + fault); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", + *fault & HALO_AHBM_FLAGS_ERR_MASK, + (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >> + HALO_AHBM_CORE_ERR_ADDR_SHIFT); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, + fault); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); + + ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, + fault, ARRAY_SIZE(fault)); + if (ret) { + adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); + adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); + adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); + + ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); + if (ret) + adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); + +exit_unlock: + mutex_unlock(&dsp->pwr_lock); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_halo_bus_error); + +irqreturn_t wm_halo_wdt_expire(int irq, void *data) +{ + struct wm_adsp *dsp = data; + + mutex_lock(&dsp->pwr_lock); + + adsp_warn(dsp, "WDT Expiry Fault\n"); + dsp->ops->stop_watchdog(dsp); + wm_adsp_fatal_error(dsp); + + mutex_unlock(&dsp->pwr_lock); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_halo_wdt_expire); + +static struct wm_adsp_ops wm_adsp1_ops = { + .validate_version = wm_adsp_validate_version, + .parse_sizes = wm_adsp1_parse_sizes, + .region_to_reg = wm_adsp_region_to_reg, +}; + +static struct wm_adsp_ops wm_adsp2_ops[] = { + { + .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_adsp_validate_version, + .setup_algs = wm_adsp2_setup_algs, + .region_to_reg = wm_adsp_region_to_reg, + + .show_fw_status = wm_adsp2_show_fw_status, + + .enable_memory = wm_adsp2_enable_memory, + .disable_memory = wm_adsp2_disable_memory, + + .enable_core = wm_adsp2_enable_core, + .disable_core = wm_adsp2_disable_core, + + .start_core = wm_adsp2_start_core, + .stop_core = wm_adsp2_stop_core, + + }, + { + .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_adsp_validate_version, + .setup_algs = wm_adsp2_setup_algs, + .region_to_reg = wm_adsp_region_to_reg, + + .show_fw_status = wm_adsp2v2_show_fw_status, + + .enable_memory = wm_adsp2_enable_memory, + .disable_memory = wm_adsp2_disable_memory, + .lock_memory = wm_adsp2_lock, + + .enable_core = wm_adsp2v2_enable_core, + .disable_core = wm_adsp2v2_disable_core, + + .start_core = wm_adsp2_start_core, + .stop_core = wm_adsp2_stop_core, + }, + { + .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_adsp_validate_version, + .setup_algs = wm_adsp2_setup_algs, + .region_to_reg = wm_adsp_region_to_reg, + + .show_fw_status = wm_adsp2v2_show_fw_status, + .stop_watchdog = wm_adsp_stop_watchdog, + + .enable_memory = wm_adsp2_enable_memory, + .disable_memory = wm_adsp2_disable_memory, + .lock_memory = wm_adsp2_lock, + + .enable_core = wm_adsp2v2_enable_core, + .disable_core = wm_adsp2v2_disable_core, + + .start_core = wm_adsp2_start_core, + .stop_core = wm_adsp2_stop_core, + }, +}; + +static struct wm_adsp_ops wm_halo_ops = { + .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_halo_validate_version, + .setup_algs = wm_halo_setup_algs, + .region_to_reg = wm_halo_region_to_reg, + + .show_fw_status = wm_halo_show_fw_status, + .stop_watchdog = wm_halo_stop_watchdog, + + .lock_memory = wm_halo_configure_mpu, + + .start_core = wm_halo_start_core, + .stop_core = wm_halo_stop_core, +}; + +static struct wm_adsp_ops wm_vpu_ops = { + .parse_sizes = wm_vpu_parse_sizes, + .validate_version = wm_halo_validate_version, + .setup_algs = wm_vpu_setup_algs, + .region_to_reg = wm_vpu_region_to_reg, +}; + +MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/cs35l45/wm_adsp.h b/techpack/audio/asoc/codecs/cs35l45/wm_adsp.h new file mode 100644 index 0000000000000..084a7aa0cd6c3 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/wm_adsp.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * wm_adsp.h -- Wolfson ADSP support + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + */ + +#ifndef __WM_ADSP_H +#define __WM_ADSP_H + +#include +#include +#include + +#include "wmfw.h" + +/* Return values for wm_adsp_compr_handle_irq */ +#define WM_ADSP_COMPR_OK 0 +#define WM_ADSP_COMPR_VOICE_TRIGGER 1 + +#define WM_ADSP2_REGION_0 BIT(0) +#define WM_ADSP2_REGION_1 BIT(1) +#define WM_ADSP2_REGION_2 BIT(2) +#define WM_ADSP2_REGION_3 BIT(3) +#define WM_ADSP2_REGION_4 BIT(4) +#define WM_ADSP2_REGION_5 BIT(5) +#define WM_ADSP2_REGION_6 BIT(6) +#define WM_ADSP2_REGION_7 BIT(7) +#define WM_ADSP2_REGION_8 BIT(8) +#define WM_ADSP2_REGION_9 BIT(9) +#define WM_ADSP2_REGION_1_9 (WM_ADSP2_REGION_1 | \ + WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \ + WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | \ + WM_ADSP2_REGION_6 | WM_ADSP2_REGION_7 | \ + WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9) +#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9) + +struct wm_adsp_region { + int type; + unsigned int base; +}; + +struct wm_adsp_alg_region { + struct list_head list; + unsigned int alg; + int type; + unsigned int base; +}; + +struct wm_adsp_compr; +struct wm_adsp_compr_buf; +struct wm_adsp_ops; + +struct wm_adsp { + const char *part; + const char *name; + const char *fwf_name; + int rev; + int num; + int type; + struct device *dev; + struct regmap *regmap; + struct snd_soc_component *component; + + struct wm_adsp_ops *ops; + + unsigned int base; + unsigned int base_sysinfo; + unsigned int sysclk_reg; + unsigned int sysclk_mask; + unsigned int sysclk_shift; + + // Speaker calibration parameters + int cal_z; + int ambient; + int cal_status; + int cal_chksum; + + struct list_head alg_regions; + + unsigned int fw_id; + unsigned int fw_id_version; + unsigned int fw_vendor_id; + + const struct wm_adsp_region *mem; + int num_mems; + + int fw; + int fw_ver; + + bool no_preloader; + bool preloaded; + bool booted; + bool running; + bool fatal_error; + + struct list_head ctl_list; + + struct work_struct boot_work; + + struct list_head compr_list; + struct list_head buffer_list; + + struct mutex pwr_lock; + + unsigned int lock_regions; + + unsigned int n_rx_channels; + unsigned int n_tx_channels; + + struct mutex *rate_lock; + u8 *rx_rate_cache; + u8 *tx_rate_cache; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; + char *wmfw_file_name; + char *bin_file_name; +#endif + unsigned int data_word_mask; + int data_word_size; + + void (*fwevent_cb)(struct wm_adsp *dsp, int eventid); +}; + +struct wm_adsp_ops { + unsigned int sys_config_size; + + bool (*validate_version)(struct wm_adsp *dsp, unsigned int version); + unsigned int (*parse_sizes)(struct wm_adsp *dsp, + const char * const file, + unsigned int pos, + const struct firmware *firmware); + int (*setup_algs)(struct wm_adsp *dsp); + unsigned int (*region_to_reg)(struct wm_adsp_region const *mem, + unsigned int offset); + + void (*show_fw_status)(struct wm_adsp *dsp); + void (*stop_watchdog)(struct wm_adsp *dsp); + + int (*enable_memory)(struct wm_adsp *dsp); + void (*disable_memory)(struct wm_adsp *dsp); + int (*lock_memory)(struct wm_adsp *dsp, unsigned int lock_regions); + + int (*enable_core)(struct wm_adsp *dsp); + void (*disable_core)(struct wm_adsp *dsp); + + int (*start_core)(struct wm_adsp *dsp); + void (*stop_core)(struct wm_adsp *dsp); +}; + +#define WM_ADSP_PRELOADER(wname, num, event_fn) \ +{ .id = snd_soc_dapm_supply, .name = wname " Preloader", \ + .reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \ + .subseq = 100, /* Ensure we run after SYSCLK supply widget */ } + +#define WM_ADSP1(wname, num) \ + SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, num, 0, NULL, 0, \ + wm_adsp1_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD) + +#define WM_ADSP2_PRELOAD_SWITCH(wname, num) \ + SOC_SINGLE_EXT(wname " Preload Switch", SND_SOC_NOPM, num, 1, 0, \ + wm_adsp2_preloader_get, wm_adsp2_preloader_put) + +#define WM_ADSP2(wname, num, event_fn) \ + SND_SOC_DAPM_SPK(wname " Preload", NULL), \ + WM_ADSP_PRELOADER(wname, num, event_fn), \ +{ .id = snd_soc_dapm_out_drv, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp_event, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } + +#define WM_HALO(wname, num, event_fn) \ + WM_ADSP2(wname, num, event_fn) + +#define WM_ADSP_FW_CONTROL(dspname, num) \ + SOC_ENUM_EXT(dspname " Firmware", wm_adsp_fw_enum[num], \ + wm_adsp_fw_get, wm_adsp_fw_put) + +extern const struct soc_enum wm_adsp_fw_enum[]; + +int wm_adsp1_init(struct wm_adsp *dsp); +int wm_adsp2_init(struct wm_adsp *dsp); +void wm_adsp2_remove(struct wm_adsp *dsp); +int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component); +int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component); +int wm_vpu_init(struct wm_adsp *vpu); +int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock); + +int wm_adsp1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +int wm_adsp_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +irqreturn_t wm_adsp2_bus_error(int irq, void *data); +irqreturn_t wm_halo_bus_error(int irq, void *data); +irqreturn_t wm_halo_wdt_expire(int irq, void *data); + +int wm_adsp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq); + +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream); +int wm_adsp_compr_free(struct snd_compr_stream *stream); +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params); +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps); +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd); +int wm_adsp_compr_handle_irq(struct wm_adsp *dsp); +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp); +int wm_adsp_compr_copy(struct snd_compr_stream *stream, + char __user *buf, size_t count); +int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type, + unsigned int alg, void *buf, size_t len); +int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type, + unsigned int alg, void *buf, size_t len); + +extern int wm_adsp_handle_fw_event(struct wm_adsp *dsp); + +#endif diff --git a/techpack/audio/asoc/codecs/cs35l45/wmfw.h b/techpack/audio/asoc/codecs/cs35l45/wmfw.h new file mode 100644 index 0000000000000..03d56e4792411 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l45/wmfw.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * wmfw.h - Wolfson firmware format information + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + */ + +#ifndef __WMFW_H +#define __WMFW_H + +#include + +#define WMFW_MAX_ALG_NAME 256 +#define WMFW_MAX_ALG_DESCR_NAME 256 + +#define WMFW_MAX_COEFF_NAME 256 +#define WMFW_MAX_COEFF_DESCR_NAME 256 + +#define WMFW_CTL_FLAG_SYS 0x8000 +#define WMFW_CTL_FLAG_VOLATILE 0x0004 +#define WMFW_CTL_FLAG_WRITEABLE 0x0002 +#define WMFW_CTL_FLAG_READABLE 0x0001 + +/* Non-ALSA coefficient types start at 0x1000 */ +#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */ +#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */ +#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */ +#define WMFW_CTL_TYPE_FWEVENT 0x1004 /* firmware event control */ + +struct wmfw_header { + char magic[4]; + __le32 len; + __le16 rev; + u8 core; + u8 ver; +} __packed; + +struct wmfw_footer { + __le64 timestamp; + __le32 checksum; +} __packed; + +struct wmfw_adsp1_sizes { + __le32 dm; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_adsp2_sizes { + __le32 xm; + __le32 ym; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_vpu_sizes { + __le32 dm; +} __packed; + +struct wmfw_region { + union { + __be32 type; + __le32 offset; + }; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_id_hdr { + __be32 core_id; + __be32 core_rev; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_v3_id_hdr { + __be32 core_id; + __be32 block_rev; + __be32 vendor_id; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 dm; + __be32 n_algs; +} __packed; + +struct wmfw_adsp2_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 xm; + __be32 ym; + __be32 n_algs; +} __packed; + +struct wmfw_halo_id_hdr { + struct wmfw_v3_id_hdr fw; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; + __be32 n_algs; +} __packed; + +struct wmfw_vpu_id_hdr { + struct wmfw_v3_id_hdr fw; + __be32 dm_base; + __be32 dm_size; + __be32 n_algs; +} __packed; + +struct wmfw_alg_hdr { + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 dm; +} __packed; + +struct wmfw_adsp2_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 xm; + __be32 ym; +} __packed; + +struct wmfw_vpu_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 dm_base; + __be32 dm_size; +} __packed; + +struct wmfw_halo_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; +} __packed; + +struct wmfw_adsp_alg_data { + __le32 id; + u8 name[WMFW_MAX_ALG_NAME]; + u8 descr[WMFW_MAX_ALG_DESCR_NAME]; + __le32 ncoeff; + u8 data[]; +} __packed; + +struct wmfw_adsp_coeff_data { + struct { + __le16 offset; + __le16 type; + __le32 size; + } hdr; + u8 name[WMFW_MAX_COEFF_NAME]; + u8 descr[WMFW_MAX_COEFF_DESCR_NAME]; + __le16 ctl_type; + __le16 flags; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_coeff_hdr { + u8 magic[4]; + __le32 len; + union { + __be32 rev; + __le32 ver; + }; + union { + __be32 core; + __le32 core_ver; + }; + u8 data[]; +} __packed; + +struct wmfw_coeff_item { + __le16 offset; + __le16 type; + __le32 id; + __le32 ver; + __le32 sr; + __le32 len; + u8 data[]; +} __packed; + +#define WMFW_ADSP1 1 +#define WMFW_ADSP2 2 +#define WMFW_HALO 4 +#define WMFW_VPU 0x45 + +#define WMFW_ABSOLUTE 0xf0 +#define WMFW_ALGORITHM_DATA 0xf2 +#define WMFW_METADATA 0xfc +#define WMFW_NAME_TEXT 0xfe +#define WMFW_INFO_TEXT 0xff + +#define WMFW_ADSP1_PM 2 +#define WMFW_ADSP1_DM 3 +#define WMFW_ADSP1_ZM 4 + +#define WMFW_ADSP2_PM 2 +#define WMFW_ADSP2_ZM 4 +#define WMFW_ADSP2_XM 5 +#define WMFW_ADSP2_YM 6 + +#define WMFW_HALO_PM_PACKED 0x10 +#define WMFW_HALO_XM_PACKED 0x11 +#define WMFW_HALO_YM_PACKED 0x12 + +#define WMFW_VPU_DM 0x30 + +#endif