spmi: spmi-pmic-arb: Add support to set interrupt ownership
The MID_SEL register routes the interrupt to the configured MID. On a multi-SOC system a PMIC interrupt may be assigned to secondary SOC (on another MID). Make sure the interrupt gets assigned to the right MID while registering for it. Change-Id: I87cc890af051dbe8e1c81662800f1c39b50290da Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */
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#include <linux/bitmap.h>
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#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/debugfs.h>
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@ -157,6 +157,7 @@ struct spmi_pmic_arb {
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u8 channel;
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u8 channel;
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int irq;
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int irq;
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u8 ee;
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u8 ee;
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u8 mid;
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u16 min_apid;
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u16 min_apid;
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u16 max_apid;
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u16 max_apid;
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u32 *mapping_table;
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u32 *mapping_table;
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@ -463,6 +464,7 @@ enum qpnpint_regs {
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QPNPINT_REG_EN_SET = 0x15,
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QPNPINT_REG_EN_SET = 0x15,
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QPNPINT_REG_EN_CLR = 0x16,
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QPNPINT_REG_EN_CLR = 0x16,
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QPNPINT_REG_LATCHED_STS = 0x18,
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QPNPINT_REG_LATCHED_STS = 0x18,
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QPNPINT_REG_MID_SEL = 0x1A,
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};
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};
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struct spmi_pmic_arb_qpnpint_type {
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struct spmi_pmic_arb_qpnpint_type {
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@ -722,6 +724,13 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain,
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return -ENODEV;
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return -ENODEV;
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}
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}
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/*
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* Make sure the interrupt is assigned to primary SOC by writing the
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* MID value to MID_SEL register.
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*/
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if (pmic_arb->mid != EINVAL)
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qpnpint_spmi_write(d, QPNPINT_REG_MID_SEL, &pmic_arb->mid, 1);
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buf = BIT(irq);
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buf = BIT(irq);
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qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1);
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qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1);
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qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1);
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qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1);
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@ -1441,7 +1450,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
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struct resource *res;
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struct resource *res;
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void __iomem *core;
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void __iomem *core;
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u32 *mapping_table;
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u32 *mapping_table;
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u32 channel, ee, hw_ver;
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u32 channel, ee, hw_ver, mid = 0;
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int err;
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int err;
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ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
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ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
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@ -1556,6 +1565,17 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
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}
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}
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pmic_arb->ee = ee;
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pmic_arb->ee = ee;
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pmic_arb->mid = EINVAL;
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err = of_property_read_u32(pdev->dev.of_node, "qcom,mid", &mid);
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if (!err && mid <= 3) {
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pmic_arb->mid = mid;
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} else if (err != -EINVAL) {
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dev_err(&pdev->dev, "invalid MID (%u) specified\n", mid);
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err = -EINVAL;
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goto err_put_ctrl;
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}
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mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
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mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
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sizeof(*mapping_table), GFP_KERNEL);
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sizeof(*mapping_table), GFP_KERNEL);
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if (!mapping_table) {
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if (!mapping_table) {
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