drivers: irqchip: Add support to make mpm as module
To make the mpm driver as module driver, register the mpm driver to platform bus driver and create the both gic and gpio irq domains in its probe function. Also add the support for mpm pin to gic irq number translation to send irq info to its parent gic domain. Also add the select and match function support to gpio chip domain to differentiate it from gic interrupt domain. Change-Id: I433f3a5b895d0ca074bae986ad5154892d7a31c4 Signed-off-by: Raghavendra Kakarla <rkakarla@codeaurora.org>
This commit is contained in:
Raghavendra Kakarla
Gerrit - the friendly Code Review server
parent
67371f6ddc
commit
5f6b8a2b36
@ -494,7 +494,7 @@ config TI_SCI_INTA_IRQCHIP
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TI System Controller, say Y here. Otherwise, say N.
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config QCOM_MPM
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bool "QCOM MPM"
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tristate "QCOM MPM"
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depends on ARCH_QCOM
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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@ -98,7 +98,8 @@ obj-$(CONFIG_NDS32) += irq-ativic32.o
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obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
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obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o
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obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
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obj-$(CONFIG_QCOM_MPM) += qcom-mpm.o
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obj-$(CONFIG_QCOM_MPM) += mpm.o
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mpm-objs += qcom-mpm.o qcom-mpm-holi.o
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obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
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obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
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16
drivers/irqchip/qcom-mpm-holi.c
Normal file
16
drivers/irqchip/qcom-mpm-holi.c
Normal file
@ -0,0 +1,16 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <soc/qcom/mpm.h>
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const struct mpm_pin mpm_holi_gic_chip_data[] = {
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{2, 222}, /* tsens0_tsens_critical_int */
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{5, 328}, /* lpass_irq_out_sdc */
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{12, 454}, /* qmp_usb3_lfps_rxterm_irq_cx */
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{86, 215}, /* mpm_wake,spmi_m */
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{93, 292}, /* eud_p0_dpse_int_mx */
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{94, 292}, /* eud_p0_dmse_int_mx */
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{-1},
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};
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@ -48,6 +48,7 @@
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#define QCOM_MPM_REG_WIDTH DIV_ROUND_UP(num_mpm_irqs, 32)
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#define MPM_REGISTER(reg, index) ((reg * QCOM_MPM_REG_WIDTH + index + 2) * (4))
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#define GPIO_NO_WAKE_IRQ ~0U
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#define MPM_NO_PARENT_IRQ ~0U
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struct msm_mpm_device_data {
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struct device *dev;
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@ -63,19 +64,43 @@ static struct msm_mpm_device_data msm_mpm_dev_data;
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static unsigned int *mpm_to_irq;
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static DEFINE_SPINLOCK(mpm_lock);
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static irq_hw_number_t get_parent_hwirq(struct irq_domain *d,
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irq_hw_number_t hwirq)
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{
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struct mpm_pin *mpm_data = NULL;
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int i = 0;
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if (!d)
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return GPIO_NO_WAKE_IRQ;
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if (d->host_data) {
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mpm_data = d->host_data;
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for (i = 0; (mpm_data[i].pin >= 0); i++) {
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if (mpm_data[i].pin == hwirq)
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return mpm_data[i].hwirq;
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}
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}
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return GPIO_NO_WAKE_IRQ;
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}
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static void msm_get_mpm_pin(struct irq_data *d, int *mpm_pin, bool is_mpmgic)
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{
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struct mpm_pin *mpm_data = NULL;
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int i = 0, j = 0;
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irq_hw_number_t hwirq;
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if (!d)
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if (!d || !d->domain)
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return;
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if (is_mpmgic && d->domain->host_data) {
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mpm_data = d->domain->host_data;
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hwirq = get_parent_hwirq(d->domain, d->hwirq);
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if (hwirq == GPIO_NO_WAKE_IRQ)
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return;
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for (i = 0; (mpm_data[i].pin >= 0) &&
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(j < MAX_MPM_PIN_PER_IRQ); i++) {
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if (mpm_data[i].hwirq == d->hwirq) {
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if (mpm_data[i].hwirq == hwirq) {
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mpm_pin[j] = mpm_data[i].pin;
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mpm_to_irq[mpm_data[i].pin] = d->irq;
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j++;
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@ -242,16 +267,31 @@ static int msm_mpm_gic_chip_set_type(struct irq_data *d, unsigned int type)
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return irq_chip_set_type_parent(d, type);
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}
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int msm_mpm_gic_chip_set_affinity(struct irq_data *data,
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const struct cpumask *dest, bool force)
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{
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data = data->parent_data;
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if (data->chip->irq_set_affinity)
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return data->chip->irq_set_affinity(data, dest, force);
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return -ENXIO;
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}
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void msm_mpm_gic_chip_eoi(struct irq_data *data)
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{
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data = data->parent_data;
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data->chip->irq_eoi(data);
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}
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static struct irq_chip msm_mpm_gic_chip = {
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.name = "mpm-gic",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_eoi = msm_mpm_gic_chip_eoi,
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.irq_mask = msm_mpm_gic_chip_mask,
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.irq_disable = msm_mpm_gic_chip_mask,
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.irq_unmask = msm_mpm_gic_chip_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = msm_mpm_gic_chip_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_affinity = msm_mpm_gic_chip_set_affinity,
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};
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static struct irq_chip msm_mpm_gpio_chip = {
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@ -261,7 +301,6 @@ static struct irq_chip msm_mpm_gpio_chip = {
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.irq_unmask = msm_mpm_gpio_chip_unmask,
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.irq_set_type = msm_mpm_gpio_chip_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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};
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static int msm_mpm_gpio_chip_translate(struct irq_domain *d,
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@ -298,49 +337,40 @@ static int msm_mpm_gpio_chip_alloc(struct irq_domain *domain,
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return 0;
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}
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static int msm_mpm_gpio_chip_match(struct irq_domain *d,
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struct device_node *node,
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enum irq_domain_bus_token bus_token)
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{
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return (bus_token == DOMAIN_BUS_WAKEUP);
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}
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static int msm_mpm_gpio_chip_select(struct irq_domain *d,
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struct irq_fwspec *node,
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enum irq_domain_bus_token bus_token)
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{
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return (bus_token == DOMAIN_BUS_WAKEUP);
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}
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static const struct irq_domain_ops msm_mpm_gpio_chip_domain_ops = {
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.translate = msm_mpm_gpio_chip_translate,
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.alloc = msm_mpm_gpio_chip_alloc,
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.free = irq_domain_free_irqs_common,
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.match = msm_mpm_gpio_chip_match,
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.select = msm_mpm_gpio_chip_select,
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};
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static int msm_mpm_gic_chip_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count < 3)
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return -EINVAL;
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switch (fwspec->param[0]) {
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case 0: /* SPI */
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*hwirq = fwspec->param[1] + 32;
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break;
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case 1: /* PPI */
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*hwirq = fwspec->param[1] + 16;
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break;
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case GIC_IRQ_TYPE_LPI: /* LPI */
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*hwirq = fwspec->param[1];
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break;
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default:
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return -EINVAL;
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}
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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if (is_fwnode_irqchip(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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return -EINVAL;
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}
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@ -351,7 +381,7 @@ static int msm_mpm_gic_chip_alloc(struct irq_domain *domain,
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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irq_hw_number_t hwirq, parent_hwirq;
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unsigned int type;
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int ret;
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@ -362,8 +392,15 @@ static int msm_mpm_gic_chip_alloc(struct irq_domain *domain,
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&msm_mpm_gic_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_hwirq = get_parent_hwirq(domain, hwirq);
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if (parent_hwirq == MPM_NO_PARENT_IRQ)
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return 0;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 3;
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parent_fwspec.param[0] = 0;
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parent_fwspec.param[1] = parent_hwirq;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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@ -381,66 +418,38 @@ static inline void msm_mpm_send_interrupt(void)
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wmb();
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}
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static inline void msm_mpm_timer_write(uint32_t *expiry)
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void msm_mpm_timer_write(uint32_t *expiry)
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{
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writel_relaxed(expiry[0], msm_mpm_dev_data.mpm_request_reg_base);
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writel_relaxed(expiry[1], msm_mpm_dev_data.mpm_request_reg_base + 0x4);
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}
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static void msm_mpm_enter_sleep(struct cpumask *cpumask)
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void msm_mpm_enter_sleep(struct cpumask *cpumask)
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{
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msm_mpm_send_interrupt();
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irq_set_affinity(msm_mpm_dev_data.ipc_irq, cpumask);
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}
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int i = 0;
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struct irq_chip *irq_chip;
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struct irq_data *irq_data;
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static void system_pm_exit_sleep(bool success)
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{
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msm_rpm_exit_sleep();
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}
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static int system_pm_update_wakeup(bool from_idle)
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{
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uint32_t lo = ~0U, hi = ~0U;
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u64 wakeup;
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/* Read the hardware to get the most accurate value */
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arch_timer_mem_get_cval(&lo, &hi);
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wakeup = lo;
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wakeup |= ((uint64_t)(hi) << 32);
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msm_mpm_timer_write((uint32_t *)&wakeup);
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trace_mpm_wakeup_time(from_idle, wakeup, arch_counter_get_cntvct());
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return 0;
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}
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static int system_pm_enter_sleep(struct cpumask *mask)
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{
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int ret = 0, i = 0;
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ret = msm_rpm_enter_sleep(0, mask);
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if (ret)
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return ret;
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for (i = 0; i < QCOM_MPM_REG_WIDTH; i++)
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msm_mpm_write(MPM_REG_STATUS, i, 0);
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msm_mpm_enter_sleep(mask);
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msm_mpm_send_interrupt();
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return ret;
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irq_data = irq_get_irq_data(msm_mpm_dev_data.ipc_irq);
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if (!irq_data)
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return;
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irq_chip = irq_data->chip;
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if (!irq_data)
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return;
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if (cpumask)
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irq_chip->irq_set_affinity(irq_data, cpumask, true);
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}
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static bool system_pm_sleep_allowed(void)
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{
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return !msm_rpm_waiting_for_ack();
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}
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static struct system_pm_ops pm_ops = {
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.enter = system_pm_enter_sleep,
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.exit = system_pm_exit_sleep,
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.update_wakeup = system_pm_update_wakeup,
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.sleep_allowed = system_pm_sleep_allowed,
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};
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/*
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* Triggered by RPM when system resumes from deep sleep
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*/
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@ -534,8 +543,7 @@ static int msm_mpm_init(struct device_node *node)
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goto set_wake_irq_err;
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}
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return register_system_pm_ops(&pm_ops);
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return 0;
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set_wake_irq_err:
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free_irq(dev->ipc_irq, msm_mpm_irq);
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ipc_irq_err:
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@ -547,12 +555,16 @@ reg_base_err:
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}
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static const struct of_device_id mpm_gic_chip_data_table[] = {
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{
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.compatible = "qcom,mpm-gic-holi",
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.data = mpm_holi_gic_chip_data,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, mpm_gic_chip_data_table);
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static int __init mpm_gic_chip_init(struct device_node *node,
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struct device_node *parent)
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static int msm_mpm_irqchip_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain;
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const struct of_device_id *id;
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@ -592,6 +604,14 @@ static int __init mpm_gic_chip_init(struct device_node *node,
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}
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msm_mpm_dev_data.gic_chip_domain->name = "qcom,mpm-gic";
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msm_mpm_dev_data.gpio_chip_domain = irq_domain_create_linear(
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of_node_to_fwnode(node), num_mpm_irqs,
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&msm_mpm_gpio_chip_domain_ops, NULL);
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if (!msm_mpm_dev_data.gpio_chip_domain)
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return -ENOMEM;
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msm_mpm_dev_data.gpio_chip_domain->name = "qcom,mpm-gpio";
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ret = msm_mpm_init(node);
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if (!ret)
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@ -602,22 +622,37 @@ mpm_map_err:
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kfree(mpm_to_irq);
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return ret;
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}
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IRQCHIP_DECLARE(mpm_gic_chip, "qcom,mpm-gic", mpm_gic_chip_init);
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static int __init mpm_gpio_chip_init(struct device_node *node,
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struct device_node *parent)
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#ifdef MODULE
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static int mpm_driver_probe(struct platform_device *pdev)
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{
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msm_mpm_dev_data.gpio_chip_domain = irq_domain_create_linear(
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of_node_to_fwnode(node), num_mpm_irqs,
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&msm_mpm_gpio_chip_domain_ops, NULL);
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struct device_node *node = pdev->dev.of_node, *parent;
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if (!msm_mpm_dev_data.gpio_chip_domain)
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return -ENOMEM;
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parent = of_irq_find_parent(node);
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if (!parent) {
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pr_err("%s(): no parent for mpm-gic\n", node->full_name);
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return -ENXIO;
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}
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irq_domain_update_bus_token(msm_mpm_dev_data.gpio_chip_domain,
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DOMAIN_BUS_WAKEUP);
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msm_mpm_dev_data.gpio_chip_domain->name = "qcom,mpm-gpio";
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return msm_mpm_irqchip_init(node, parent);
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return 0;
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}
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IRQCHIP_DECLARE(mpm_gpio_chip, "qcom,mpm-gpio", mpm_gpio_chip_init);
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static const struct of_device_id mpm_of_match[] = {
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{ .compatible = "qcom,mpm" },
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{},
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};
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struct platform_driver mpm_driver = {
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.probe = mpm_driver_probe,
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.driver = {
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.name = "qcom-mpm",
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.of_match_table = mpm_of_match,
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},
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};
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module_platform_driver(mpm_driver);
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#else
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IRQCHIP_DECLARE(mpm_gpio_chip, "qcom,mpm", msm_mpm_irqchip_init);
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#endif
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MODULE_DESCRIPTION("Qualcomm Technologies, Inc. (QTI) MPM Driver");
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MODULE_LICENSE("GPL v2");
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@ -14,4 +14,7 @@ struct mpm_pin {
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irq_hw_number_t hwirq;
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};
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void msm_mpm_timer_write(uint32_t *expiry);
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void msm_mpm_enter_sleep(struct cpumask *cpumask);
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extern const struct mpm_pin mpm_holi_gic_chip_data[];
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#endif /* __QCOM_MPM_H__ */
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