Merge "disp: msm: fix kw issues in sde driver"
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621a624d8c
@ -2086,7 +2086,7 @@ static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
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struct sde_rm_hw_iter pp_iter, qdss_iter;
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struct sde_rm_hw_iter dsc_iter, vdc_iter;
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struct sde_rm_hw_request request_hw;
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int i;
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int i, j;
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sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
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for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
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@ -2102,7 +2102,7 @@ static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
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if (phys) {
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sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
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SDE_HW_BLK_QDSS);
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for (i = 0; i < QDSS_MAX; i++) {
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for (j = 0; j < QDSS_MAX; j++) {
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if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
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phys->hw_qdss =
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(struct sde_hw_qdss *)qdss_iter.hw;
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@ -2156,7 +2156,7 @@ static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
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struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
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enum sde_intf_mode intf_mode;
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int ret;
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bool is_cmd_mode;
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bool is_cmd_mode = false;
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if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
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is_cmd_mode = true;
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@ -385,9 +385,7 @@ static int _dce_dsc_setup_single(struct sde_encoder_virt *sde_enc,
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SDE_DEBUG("mode_3d %s, on CTL_%d PP-%d merge3d:%d\n",
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!disable_merge_3d ? "enabled" : "disabled",
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hw_ctl->idx - CTL_0, hw_pp->idx - PINGPONG_0,
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hw_pp->merge_3d ?
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hw_pp->merge_3d->idx - MERGE_3D_0 :
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-1);
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hw_pp->merge_3d->idx - MERGE_3D_0);
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}
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return 0;
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@ -330,8 +330,8 @@ static void _sde_encoder_phys_cmd_setup_irq_hw_idx(
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int ret = 0;
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if (!phys_enc->sde_kms || !phys_enc->hw_pp || !phys_enc->hw_ctl) {
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SDE_ERROR("invalid args %d %d\n", !phys_enc,
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phys_enc ? !phys_enc->hw_pp : 0);
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SDE_ERROR("invalid args %d %d %d\n", !phys_enc->sde_kms,
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!phys_enc->hw_pp, !phys_enc->hw_ctl);
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return;
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}
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@ -500,7 +500,7 @@ static int _sde_encoder_phys_cmd_handle_ppdone_timeout(
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u32 pending_kickoff_cnt;
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unsigned long lock_flags;
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if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl)
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if (!phys_enc->hw_pp || !phys_enc->hw_ctl)
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return -EINVAL;
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conn = phys_enc->connector;
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@ -846,11 +846,9 @@ static void _sde_plane_setup_scaler3(struct sde_plane *psde,
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bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
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bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
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if (!psde || !pstate || !fmt ||
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!chroma_subsmpl_h || !chroma_subsmpl_v) {
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SDE_ERROR("psde %d pstate %d fmt %d smp_h %d smp_v %d\n",
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!!psde, !!pstate, !!fmt, chroma_subsmpl_h,
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chroma_subsmpl_v);
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if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
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SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
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chroma_subsmpl_h, chroma_subsmpl_v);
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return;
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}
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@ -93,7 +93,7 @@ static struct sde_dsc_v1_1_table_index_lut {
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int scr_ver;
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u32 bpc;
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u32 bpp;
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enum sde_dsc_ratio_type type;
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u32 type;
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} sde_dsc_v1_1_index_map[] = {
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{0, 8, 8, DSC_V11_8BPC_8BPP},
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{0, 10, 8, DSC_V11_10BPC_8BPP},
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@ -108,7 +108,7 @@ static struct sde_dsc_v1_2_table_index_lut {
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u32 fmt;
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u32 bpc;
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u32 bpp;
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enum sde_dsc_ratio_type type;
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u32 type;
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} sde_dsc_v1_2_index_map[] = {
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{MSM_CHROMA_444, 8, 8, DSC_V12_444_8BPC_8BPP},
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{MSM_CHROMA_444, 10, 8, DSC_V12_444_10BPC_8BPP},
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