disp: msm: typecast variables as long long for 64 bit operations
Define 64 bit variables as unsigned long long to ensure 8 bytes in 32 bit builds. Change-Id: I723ae0c4ba6a0de07c92d14eeef95bde095c8e3d Signed-off-by: Venkata Prahlad Valluru <vvalluru@codeaurora.org>
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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@ -565,11 +565,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_5nm *pll,
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switch (rsc->pll_revision) {
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case DSI_PLL_5NM:
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default:
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if (pll_freq <= 1000000000)
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if (pll_freq <= 1000000000ULL)
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regs->pll_clock_inverters = 0xA0;
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else if (pll_freq <= 2500000000)
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else if (pll_freq <= 2500000000ULL)
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regs->pll_clock_inverters = 0x20;
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else if (pll_freq <= 3500000000)
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else if (pll_freq <= 3500000000ULL)
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regs->pll_clock_inverters = 0x00;
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else
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regs->pll_clock_inverters = 0x40;
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@ -664,16 +664,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_5nm *pll,
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switch (rsc->pll_revision) {
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case DSI_PLL_5NM:
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default:
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if (vco_rate < 3100000000)
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if (vco_rate < 3100000000ULL)
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DSI_PLL_REG_W(pll_base,
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PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
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else
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DSI_PLL_REG_W(pll_base,
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PLL_ANALOG_CONTROLS_FIVE_1, 0x03);
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if (vco_rate < 1520000000)
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if (vco_rate < 1520000000ULL)
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DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08);
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else if (vco_rate < 2990000000)
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else if (vco_rate < 2990000000ULL)
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DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);
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else
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DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01);
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@ -423,8 +423,8 @@ void sde_demura_backlight_cfg(struct sde_hw_dspp *dspp, u64 val)
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return;
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}
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demura_base = dspp->cap->sblk->demura.base;
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backlight = (val & REG_MASK(11));
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backlight |= ((val & REG_MASK_SHIFT(11, 32)) >> 16);
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backlight = (val & REG_MASK_ULL(11));
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backlight |= ((val & REG_MASK_SHIFT_ULL(11, 32)) >> 16);
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SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->demura.base + 0x8,
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backlight);
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}
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@ -880,7 +880,8 @@ static int check_support_v1(enum sde_reg_dma_features feature,
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if (!is_supported)
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return -EINVAL;
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if (feature >= REG_DMA_FEATURES_MAX || blk >= BIT(REG_DMA_BLK_MAX)) {
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if (feature >= REG_DMA_FEATURES_MAX
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|| blk >= BIT_ULL(REG_DMA_BLK_MAX)) {
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*is_supported = false;
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return ret;
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}
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@ -12,6 +12,7 @@
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#include "sde_hwio.h"
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#include "sde_hw_lm.h"
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#include "sde_dbg.h"
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#include "sde_hw_util.h"
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/* Reserve space of 128 words for LUT dma payload set-up */
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#define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128)
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@ -84,8 +85,6 @@
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#define DEMURA_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg)) + \
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REG_DMA_HEADERS_BUFFER_SZ)
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#define REG_MASK(n) ((BIT(n)) - 1)
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#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
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#define APPLY_MASK_AND_SHIFT(x, n, shift) ((x & (REG_MASK(n))) << (shift))
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#define REG_DMA_VIG_GAMUT_OP_MASK 0x300
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#define REG_DMA_VIG_IGC_OP_MASK 0x1001F
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@ -4926,8 +4925,8 @@ static int __reg_dmav1_setup_demurav1_cfg0_c_params(
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}
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for (i = 0; i < len; i++) {
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temp[i * 2] = p[i] & REG_MASK(32);
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temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT(10, 32)) >> 32;
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temp[i * 2] = p[i] & REG_MASK_ULL(32);
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temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT_ULL(10, 32)) >> 32;
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DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",
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i * 2, temp[i * 2]);
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DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_UTIL_H
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@ -12,7 +12,9 @@
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#include "sde_hw_catalog.h"
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#define REG_MASK(n) ((BIT(n)) - 1)
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#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
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#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
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#define REG_MASK_ULL(n) ((BIT_ULL(n)) - 1)
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#define REG_MASK_SHIFT_ULL(n, shift) ((REG_MASK_ULL(n)) << (shift))
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#define LP_DDR4_TYPE 0x7
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struct sde_format_extended;
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