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Import NXP SR100 ultra wideband driver

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From branch: zijin-s-oss

Change-Id: I084b089a42715b903f4aae103b95e2cb20ad9d88
This commit is contained in:
Giovanni Ricca 2022-09-10 01:44:33 +05:30
parent c65543d317
commit 72bfdb9894
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6 changed files with 1248 additions and 0 deletions
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2
drivers/Kconfig
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@ -230,4 +230,6 @@ source "drivers/interconnect/Kconfig"
source "drivers/counter/Kconfig"
source "drivers/uwb-sr100/Kconfig"
endmenu

1
drivers/Makefile
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@ -186,3 +186,4 @@ obj-$(CONFIG_SIOX) += siox/
obj-$(CONFIG_GNSS) += gnss/
obj-$(CONFIG_INTERCONNECT) += interconnect/
obj-$(CONFIG_COUNTER) += counter/
obj-$(CONFIG_NXP_SR100) += uwb-sr100/

8
drivers/uwb-sr100/Kconfig Normal file
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@ -0,0 +1,8 @@
#
# Nxp SPI SR100 devices
#
config NXP_SR100
tristate "Nxp SPI driver for SR100 devices"

5
drivers/uwb-sr100/Makefile Normal file
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@ -0,0 +1,5 @@
#
# Makefile for the kernel nfc device drivers.
#
obj-$(CONFIG_NXP_SR100) += sr100.o

1181
drivers/uwb-sr100/sr100.c Normal file
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File diff suppressed because it is too large Load Diff

51
drivers/uwb-sr100/sr100.h Normal file
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@ -0,0 +1,51 @@
/*====================================================================================*/
/* */
/* Copyright 2018-2019 NXP */
/* */
/* This program is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU General Public License as published by */
/* the Free Software Foundation; either version 2 of the License, or */
/* (at your option) any later version. */
/* */
/* This program is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* GNU General Public License for more details. */
/* */
/* You should have received a copy of the GNU General Public License */
/* along with this program; if not, write to the Free Software */
/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
/* */
/*====================================================================================*/
#define SR100_MAGIC 0xEA
#define SR100_SET_PWR _IOW(SR100_MAGIC, 0x01, long)
#define SR100_SET_DBG _IOW(SR100_MAGIC, 0x02, long)
#define SR100_SET_POLL _IOW(SR100_MAGIC, 0x03, long)
#define SR100_SET_FWD _IOW(SR100_MAGIC, 0x04, long)
#define SR100_GET_THROUGHPUT _IOW(SR100_MAGIC, 0x05, long)
#define SR100_ESE_RESET _IOW(SR100_MAGIC, 0x06, long)
#define NORMAL_MODE_HEADER_LEN 4
#define HBCI_MODE_HEADER_LEN 4
#define NORMAL_MODE_LEN_OFFSET 3
#define UCI_NORMAL_PKT_SIZE 0
#define EXTND_LEN_INDICATOR_OFFSET 1
#define EXTND_LEN_INDICATOR_OFFSET_MASK 0x80
#define EXTENDED_LENGTH_OFFSET 2
struct sr100_spi_platform_data {
unsigned int irq_gpio;
unsigned int ce_gpio;
unsigned int spi_handshake_gpio;
unsigned int rtc_sync_gpio;
unsigned int vdd_1v8_gpio; /* to control VDD for super interposer board */
unsigned int vdd_1v8_rf_gpio;
unsigned int vbat_3v6_gpio;
};
enum {
PWR_DISABLE = 0,
PWR_ENABLE,
ABORT_READ_PENDING
};