counter: stm32-timer-cnt: fix ceiling write max value
commit e4c3e133294c0a292d21073899b05ebf530169bd upstream.
The ceiling value isn't checked before writing it into registers. The user
could write a value higher than the counter resolution (e.g. 16 or 32 bits
indicated by max_arr). This makes most significant bits to be truncated.
Fix it by checking the max_arr to report a range error [1] to the user.
[1] https://lkml.org/lkml/2021/2/12/358
Fixes: ad29937e20
("counter: Add STM32 Timer quadrature encoder")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Cc: <Stable@vger.kernel.org>
Link: https://lore.kernel.org/r/1614696235-24088-1-git-send-email-fabrice.gasnier@foss.st.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
850ca1c013
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@ -25,6 +25,7 @@ struct stm32_timer_cnt {
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struct regmap *regmap;
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struct regmap *regmap;
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struct clk *clk;
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struct clk *clk;
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u32 ceiling;
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u32 ceiling;
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u32 max_arr;
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};
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};
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/**
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/**
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@ -189,6 +190,9 @@ static ssize_t stm32_count_ceiling_write(struct counter_device *counter,
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if (ret)
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if (ret)
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return ret;
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return ret;
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if (ceiling > priv->max_arr)
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return -ERANGE;
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/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
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/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
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regmap_write(priv->regmap, TIM_ARR, ceiling);
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regmap_write(priv->regmap, TIM_ARR, ceiling);
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@ -366,6 +370,7 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev)
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priv->regmap = ddata->regmap;
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priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
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priv->clk = ddata->clk;
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priv->ceiling = ddata->max_arr;
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priv->ceiling = ddata->max_arr;
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priv->max_arr = ddata->max_arr;
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priv->counter.name = dev_name(dev);
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priv->counter.name = dev_name(dev);
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priv->counter.parent = dev;
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priv->counter.parent = dev;
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