Merge "msm: camera: sensor: Remove true/false redefinitions" into camera-kernel.lnx.1.0
This commit is contained in:
commit
79ba868415
@ -30,16 +30,12 @@
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#define NUM_MASTERS 2
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#define NUM_MASTERS 2
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#define NUM_QUEUES 2
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#define NUM_QUEUES 2
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#define TRUE 1
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#define FALSE 0
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#define ACTUATOR_DRIVER_I2C "i2c_actuator"
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#define ACTUATOR_DRIVER_I2C "i2c_actuator"
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#define CAMX_ACTUATOR_DEV_NAME "cam-actuator-driver"
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#define CAMX_ACTUATOR_DEV_NAME "cam-actuator-driver"
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#define MSM_ACTUATOR_MAX_VREGS (10)
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#define MSM_ACTUATOR_MAX_VREGS (10)
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#define ACTUATOR_MAX_POLL_COUNT 10
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#define ACTUATOR_MAX_POLL_COUNT 10
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enum cam_actuator_apply_state_t {
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enum cam_actuator_apply_state_t {
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ACT_APPLY_SETTINGS_NOW,
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ACT_APPLY_SETTINGS_NOW,
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ACT_APPLY_SETTINGS_LATER,
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ACT_APPLY_SETTINGS_LATER,
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@ -49,8 +49,8 @@ static void cam_cci_flush_queue(struct cci_device *cci_dev,
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} else if (rc == 0) {
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} else if (rc == 0) {
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CAM_ERR(CAM_CCI, "wait timeout");
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CAM_ERR(CAM_CCI, "wait timeout");
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/* Set reset pending flag to TRUE */
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/* Set reset pending flag to true */
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cci_dev->cci_master_info[master].reset_pending = TRUE;
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cci_dev->cci_master_info[master].reset_pending = true;
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/* Set proper mask to RESET CMD address based on MASTER */
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/* Set proper mask to RESET CMD address based on MASTER */
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if (master == MASTER_0)
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if (master == MASTER_0)
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@ -69,18 +69,18 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
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if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) {
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struct cam_cci_master_info *cci_master_info;
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struct cam_cci_master_info *cci_master_info;
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if (cci_dev->cci_master_info[MASTER_0].reset_pending == TRUE) {
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if (cci_dev->cci_master_info[MASTER_0].reset_pending == true) {
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cci_master_info = &cci_dev->cci_master_info[MASTER_0];
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cci_master_info = &cci_dev->cci_master_info[MASTER_0];
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cci_dev->cci_master_info[MASTER_0].reset_pending =
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cci_dev->cci_master_info[MASTER_0].reset_pending =
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FALSE;
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false;
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if (!cci_master_info->status)
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if (!cci_master_info->status)
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complete(&cci_master_info->reset_complete);
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complete(&cci_master_info->reset_complete);
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cci_master_info->status = 0;
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cci_master_info->status = 0;
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}
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}
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if (cci_dev->cci_master_info[MASTER_1].reset_pending == TRUE) {
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if (cci_dev->cci_master_info[MASTER_1].reset_pending == true) {
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cci_master_info = &cci_dev->cci_master_info[MASTER_1];
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cci_master_info = &cci_dev->cci_master_info[MASTER_1];
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cci_dev->cci_master_info[MASTER_1].reset_pending =
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cci_dev->cci_master_info[MASTER_1].reset_pending =
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FALSE;
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false;
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if (!cci_master_info->status)
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if (!cci_master_info->status)
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complete(&cci_master_info->reset_complete);
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complete(&cci_master_info->reset_complete);
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cci_master_info->status = 0;
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cci_master_info->status = 0;
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@ -205,12 +205,12 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
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CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_1");
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CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_1");
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK) {
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cci_dev->cci_master_info[MASTER_0].reset_pending = TRUE;
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cci_dev->cci_master_info[MASTER_0].reset_pending = true;
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cam_io_w_mb(CCI_M0_RESET_RMSK,
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cam_io_w_mb(CCI_M0_RESET_RMSK,
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base + CCI_RESET_CMD_ADDR);
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base + CCI_RESET_CMD_ADDR);
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}
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}
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK) {
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cci_dev->cci_master_info[MASTER_1].reset_pending = TRUE;
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cci_dev->cci_master_info[MASTER_1].reset_pending = true;
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cam_io_w_mb(CCI_M1_RESET_RMSK,
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cam_io_w_mb(CCI_M1_RESET_RMSK,
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base + CCI_RESET_CMD_ADDR);
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base + CCI_RESET_CMD_ADDR);
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}
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}
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@ -316,7 +316,7 @@ static int cam_cci_irq_routine(struct v4l2_subdev *sd, u32 status,
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&cci_dev->soc_info;
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&cci_dev->soc_info;
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ret = cam_cci_irq(soc_info->irq_line->start, cci_dev);
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ret = cam_cci_irq(soc_info->irq_line->start, cci_dev);
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*handled = TRUE;
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*handled = true;
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return 0;
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return 0;
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}
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}
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@ -42,9 +42,6 @@
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#define NUM_MASTERS 2
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#define NUM_MASTERS 2
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#define NUM_QUEUES 2
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#define NUM_QUEUES 2
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#define TRUE 1
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#define FALSE 0
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#define CCI_PINCTRL_STATE_DEFAULT "cci_default"
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#define CCI_PINCTRL_STATE_DEFAULT "cci_default"
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#define CCI_PINCTRL_STATE_SLEEP "cci_suspend"
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#define CCI_PINCTRL_STATE_SLEEP "cci_suspend"
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@ -52,8 +52,8 @@ int cam_cci_init(struct v4l2_subdev *sd,
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for (i = 0; i < NUM_QUEUES; i++)
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for (i = 0; i < NUM_QUEUES; i++)
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reinit_completion(
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reinit_completion(
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&cci_dev->cci_master_info[master].report_q[i]);
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&cci_dev->cci_master_info[master].report_q[i]);
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/* Set reset pending flag to TRUE */
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/* Set reset pending flag to true */
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cci_dev->cci_master_info[master].reset_pending = TRUE;
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cci_dev->cci_master_info[master].reset_pending = true;
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/* Set proper mask to RESET CMD address */
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/* Set proper mask to RESET CMD address */
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if (master == MASTER_0)
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if (master == MASTER_0)
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cam_io_w_mb(CCI_M0_RESET_RMSK,
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cam_io_w_mb(CCI_M0_RESET_RMSK,
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@ -131,7 +131,7 @@ int cam_cci_init(struct v4l2_subdev *sd,
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}
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}
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}
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}
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cci_dev->cci_master_info[master].reset_pending = TRUE;
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cci_dev->cci_master_info[master].reset_pending = true;
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cam_io_w_mb(CCI_RESET_CMD_RMSK, base +
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cam_io_w_mb(CCI_RESET_CMD_RMSK, base +
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CCI_RESET_CMD_ADDR);
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CCI_RESET_CMD_ADDR);
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cam_io_w_mb(0x1, base + CCI_RESET_CMD_ADDR);
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cam_io_w_mb(0x1, base + CCI_RESET_CMD_ADDR);
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@ -28,9 +28,6 @@
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#define NUM_MASTERS 2
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#define NUM_MASTERS 2
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#define NUM_QUEUES 2
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#define NUM_QUEUES 2
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#define TRUE 1
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#define FALSE 0
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#undef CDBG
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#undef CDBG
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#ifdef CAM_SENSOR_DEBUG
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#ifdef CAM_SENSOR_DEBUG
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#define CDBG(fmt, args...) pr_err(fmt, ##args)
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#define CDBG(fmt, args...) pr_err(fmt, ##args)
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