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hvc_dcc: Make dcc driver read/write from CPU0

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Some debuggers, such as Trace32 from Lauterbach GmbH, do not handle
reads/writes from/to DCC on secondary cores.  Each core has its
own DCC device registers, so when a core reads or writes from/to DCC,
it only accesses its own DCC device.  Since kernel code can run on
any core, every time the kernel wants to write to the console, it
might write to a different DCC.

In SMP mode, Trace32 only uses the DCC on core 0.  In AMP mode, it
creates multiple windows, and each window shows the DCC output
only from that core's DCC.  The result is that console output is
either lost or scattered across windows.

Selecting this option will enable code that serializes all console
input and output to core 0.  The DCC driver will create input and
output FIFOs that all cores will use.  Reads and writes from/to DCC
are handled by a workqueue that runs only core 0.

Change-Id: I1e83d254ff2feaf235d212571ed791a9e84e547f
Acked-by: Adam Wallis <awallis@codeaurora.org>
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
This commit is contained in:
Kyle Yan 2016-07-27 10:30:24 -07:00 committed by Raghavendra Rao Ananta
parent 5a400b2dc2
commit 8bfd9a5a70
2 changed files with 193 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/tty/hvc/Kconfig
View File

@ -97,6 +97,27 @@ config HVC_RISCV_SBI
If you don't know what do to here, say Y.
config HVC_DCC_SERIALIZE_SMP
bool "Use DCC only on core 0"
depends on SMP && HVC_DCC
help
Some debuggers, such as Trace32 from Lauterbach GmbH, do not handle
reads/writes from/to DCC on more than one core. Each core has its
own DCC device registers, so when a core reads or writes from/to DCC,
it only accesses its own DCC device. Since kernel code can run on
any core, every time the kernel wants to write to the console, it
might write to a different DCC.
In SMP mode, Trace32 only uses the DCC on core 0. In AMP mode, it
creates multiple windows, and each window shows the DCC output
only from that core's DCC. The result is that console output is
either lost or scattered across windows.
Selecting this option will enable code that serializes all console
input and output to core 0. The DCC driver will create input and
output FIFOs that all cores will use. Reads and writes from/to DCC
are handled by a workqueue that runs only core 0.
config HVCS
tristate "IBM Hypervisor Virtual Console Server support"
depends on PPC_PSERIES && HVC_CONSOLE

173
drivers/tty/hvc/hvc_dcc.c
View File

@ -1,7 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2010, 2014 The Linux Foundation. All rights reserved. */
/* Copyright (c) 2010, 2014, 2019 The Linux Foundation. All rights reserved. */
#include <linux/init.h>
#include <linux/kfifo.h>
#include <linux/spinlock.h>
#include <linux/moduleparam.h>
#include <linux/console.h>
#include <asm/dcc.h>
#include <asm/processor.h>
@ -39,6 +43,12 @@ static int hvc_dcc_get_chars(uint32_t vt, char *buf, int count)
return i;
}
/*
* Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
* then we assume then this function will be called first on core 0. That
* way, dcc_core0_available will be true only if it's available on core 0.
*/
#ifndef CONFIG_HVC_DCC_SERIALIZE_SMP
static bool hvc_dcc_check(void)
{
unsigned long time = jiffies + (HZ / 10);
@ -53,12 +63,173 @@ static bool hvc_dcc_check(void)
return false;
}
#endif
#ifdef CONFIG_HVC_DCC_SERIALIZE_SMP
static bool hvc_dcc_check(void)
{
unsigned long time = jiffies + (HZ / 10);
static bool dcc_core0_available;
/*
* If we're not on core 0, but we previously confirmed that DCC is
* active, then just return true.
*/
if (smp_processor_id() && dcc_core0_available)
return true;
/* Write a test character to check if it is handled */
__dcc_putchar('\n');
while (time_is_after_jiffies(time)) {
if (!(__dcc_getstatus() & DCC_STATUS_TX)) {
dcc_core0_available = true;
return true;
}
}
return false;
}
static void dcc_put_work_fn(struct work_struct *work);
static void dcc_get_work_fn(struct work_struct *work);
static DECLARE_WORK(dcc_pwork, dcc_put_work_fn);
static DECLARE_WORK(dcc_gwork, dcc_get_work_fn);
static DEFINE_SPINLOCK(dcc_lock);
static DEFINE_KFIFO(inbuf, unsigned char, 128);
static DEFINE_KFIFO(outbuf, unsigned char, 1024);
/*
* Workqueue function that writes the output FIFO to the DCC on core 0.
*/
static void dcc_put_work_fn(struct work_struct *work)
{
unsigned char ch;
unsigned long irqflags;
spin_lock_irqsave(&dcc_lock, irqflags);
/* While there's data in the output FIFO, write it to the DCC */
while (kfifo_get(&outbuf, &ch))
hvc_dcc_put_chars(0, &ch, 1);
/* While we're at it, check for any input characters */
while (!kfifo_is_full(&inbuf)) {
if (!hvc_dcc_get_chars(0, &ch, 1))
break;
kfifo_put(&inbuf, ch);
}
spin_unlock_irqrestore(&dcc_lock, irqflags);
}
/*
* Workqueue function that reads characters from DCC and puts them into the
* input FIFO.
*/
static void dcc_get_work_fn(struct work_struct *work)
{
unsigned char ch;
unsigned long irqflags;
/*
* Read characters from DCC and put them into the input FIFO, as
* long as there is room and we have characters to read.
*/
spin_lock_irqsave(&dcc_lock, irqflags);
while (!kfifo_is_full(&inbuf)) {
if (!hvc_dcc_get_chars(0, &ch, 1))
break;
kfifo_put(&inbuf, ch);
}
spin_unlock_irqrestore(&dcc_lock, irqflags);
}
/*
* Write characters directly to the DCC if we're on core 0 and the FIFO
* is empty, or write them to the FIFO if we're not.
*/
static int hvc_dcc0_put_chars(uint32_t vt, const char *buf,
int count)
{
int len;
unsigned long irqflags;
spin_lock_irqsave(&dcc_lock, irqflags);
if (smp_processor_id() || (!kfifo_is_empty(&outbuf))) {
len = kfifo_in(&outbuf, buf, count);
spin_unlock_irqrestore(&dcc_lock, irqflags);
/*
* We just push data to the output FIFO, so schedule the
* workqueue that will actually write that data to DCC.
*/
schedule_work_on(0, &dcc_pwork);
return len;
}
/*
* If we're already on core 0, and the FIFO is empty, then just
* write the data to DCC.
*/
len = hvc_dcc_put_chars(vt, buf, count);
spin_unlock_irqrestore(&dcc_lock, irqflags);
return len;
}
/*
* Read characters directly from the DCC if we're on core 0 and the FIFO
* is empty, or read them from the FIFO if we're not.
*/
static int hvc_dcc0_get_chars(uint32_t vt, char *buf, int count)
{
int len;
unsigned long irqflags;
spin_lock_irqsave(&dcc_lock, irqflags);
if (smp_processor_id() || (!kfifo_is_empty(&inbuf))) {
len = kfifo_out(&inbuf, buf, count);
spin_unlock_irqrestore(&dcc_lock, irqflags);
/*
* If the FIFO was empty, there may be characters in the DCC
* that we haven't read yet. Schedule a workqueue to fill
* the input FIFO, so that the next time this function is
* called, we'll have data.
*/
if (!len)
schedule_work_on(0, &dcc_gwork);
return len;
}
/*
* If we're already on core 0, and the FIFO is empty, then just
* read the data from DCC.
*/
len = hvc_dcc_get_chars(vt, buf, count);
spin_unlock_irqrestore(&dcc_lock, irqflags);
return len;
}
static const struct hv_ops hvc_dcc_get_put_ops = {
.get_chars = hvc_dcc0_get_chars,
.put_chars = hvc_dcc0_put_chars,
};
#else
static const struct hv_ops hvc_dcc_get_put_ops = {
.get_chars = hvc_dcc_get_chars,
.put_chars = hvc_dcc_put_chars,
};
#endif
static int __init hvc_dcc_console_init(void)
{
int ret;