From 931dbd1b072f7b1c45adc73d7add78aeafd1d8f8 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 21 Mar 2023 18:44:03 +0800 Subject: [PATCH] coresight-tmc: increase qdss pcie sw path throughput Increase throughput for qdss pcie sw path. Change-Id: I4bb52e81d2617d8e83d0dcfe525cad2f6f5ca93a Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 +++- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 86987252862f..552e202e7226 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1129,9 +1129,11 @@ tmc_etr_setup_sysfs_buf(struct tmc_drvdata *drvdata) && drvdata->byte_cntr->sw_usb) new_buf = tmc_alloc_etr_buf(drvdata, TMC_ETR_SW_USB_BUF_SIZE, 0, cpu_to_node(0), NULL); - else if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) + else if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE) { new_buf = tmc_alloc_etr_buf(drvdata, TMC_ETR_PCIE_MEM_SIZE, 0, cpu_to_node(0), NULL); + drvdata->size = TMC_ETR_PCIE_MEM_SIZE; + } else new_buf = tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0), NULL); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 0c70b54863bb..e911342ddf31 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -104,7 +104,7 @@ #define TMC_ETR_BAM_PIPE_INDEX 0 #define TMC_ETR_BAM_NR_PIPES 2 -#define TMC_ETR_PCIE_MEM_SIZE 0x400000 +#define TMC_ETR_PCIE_MEM_SIZE 0x2000000 #define TMC_AUTH_NSID_MASK GENMASK(1, 0)