soc: update port config table to handle sva/voip

Update sample interval in 4.8MHZ port config table of soundwire
digital mic slave and TX1 soundwire master port.
Update the block offset of soundwire digital mics 0 and 3 to handle
voip/sva dmic concurrency in both handset and speaker mode.

Change-Id: I85480c3609a72d4be3c4643b0123f09d71b97fef
Signed-off-by: Vignesh Kulothungan <vigneshk@codeaurora.org>
This commit is contained in:
Vignesh Kulothungan 2020-10-07 10:36:05 -07:00 committed by Gerrit - the friendly Code Review server
parent 1f152bcd76
commit 941b438117
2 changed files with 9 additions and 4 deletions

View File

@ -70,7 +70,7 @@ static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = {
/* 4.8 MHz clock */
static struct port_params tx_frame_params_4p8MHz[SWR_MSTR_PORT_LEN] = {
{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{15, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
};

View File

@ -80,11 +80,16 @@ static struct port_params tx_top_mic_9p6MHz[SWR_MSTR_PORT_LEN] = {
{7, 5, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
};
/* 4 Channel configuration */
/* The 4.8MHZ port config is used in
* 1. single mic standalone in "high power" mode
* 2. dual mic standalone in "high power" mode
* 3. sva standalone single/dual/tri/quad in "low-power" mode
* 4. sva single/dmic in "low-power" + single mic in "high power" concurrency
*/
/* SWR DMIC0 */
static struct port_params tx_bottom_mic_4p8MHz[SWR_MSTR_PORT_LEN] = {
{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{7, 5, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
{15, 4, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
};
/* SWR DMIC1 */
@ -102,7 +107,7 @@ static struct port_params tx_back_mic_4p8MHz[SWR_MSTR_PORT_LEN] = {
/* SWR DMIC3 */
static struct port_params tx_top_mic_4p8MHz[SWR_MSTR_PORT_LEN] = {
{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{7, 4, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
{15, 3, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
};
/* 1 Channel configuration */