disp: msm: sde: add underrun line count information
Add underrun line count information for each underrun. Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
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@ -2887,12 +2887,16 @@ static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
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static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
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struct sde_encoder_phys *phy_enc)
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{
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struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
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if (!phy_enc)
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return;
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SDE_ATRACE_BEGIN("encoder_underrun_callback");
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atomic_inc(&phy_enc->underrun_cnt);
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SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
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if (sde_enc->cur_master->ops.get_underrun_line_count)
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sde_enc->cur_master->ops.get_underrun_line_count(
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sde_enc->cur_master);
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trace_sde_encoder_underrun(DRMID(drm_enc),
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atomic_read(&phy_enc->underrun_cnt));
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@ -133,6 +133,8 @@ struct sde_encoder_virt_ops {
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* unitl transaction is complete.
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* @wait_for_active: Wait for display scan line to be in active area
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* @setup_vsync_source: Configure vsync source selection for cmd mode.
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* @get_underrun_line_count: Obtain and log current internal vertical line
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* count and underrun line count
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*/
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struct sde_encoder_phys_ops {
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@ -185,6 +187,7 @@ struct sde_encoder_phys_ops {
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int (*wait_for_active)(struct sde_encoder_phys *phys);
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void (*setup_vsync_source)(struct sde_encoder_phys *phys,
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u32 vsync_source, bool is_dummy);
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u32 (*get_underrun_line_count)(struct sde_encoder_phys *phys);
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};
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/**
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@ -1174,6 +1174,33 @@ static int sde_encoder_phys_vid_get_line_count(
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return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
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}
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static u32 sde_encoder_phys_vid_get_underrun_line_count(
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struct sde_encoder_phys *phys_enc)
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{
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u32 underrun_linecount = 0xebadebad;
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struct intf_status intf_status = {0};
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if (!phys_enc)
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return -EINVAL;
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if (!sde_encoder_phys_vid_is_master(phys_enc) || !phys_enc->hw_intf)
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return -EINVAL;
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if (phys_enc->hw_intf->ops.get_status)
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phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
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&intf_status);
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if (phys_enc->hw_intf->ops.get_underrun_line_count)
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underrun_linecount =
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phys_enc->hw_intf->ops.get_underrun_line_count(
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phys_enc->hw_intf);
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SDE_EVT32(DRMID(phys_enc->parent), underrun_linecount,
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intf_status.frame_count, intf_status.line_count);
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return underrun_linecount;
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}
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static int sde_encoder_phys_vid_wait_for_active(
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struct sde_encoder_phys *phys_enc)
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{
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@ -1268,6 +1295,8 @@ static void sde_encoder_phys_vid_init_ops(struct sde_encoder_phys_ops *ops)
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ops->wait_dma_trigger = sde_encoder_phys_vid_wait_dma_trigger;
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ops->wait_for_active = sde_encoder_phys_vid_wait_for_active;
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ops->prepare_commit = sde_encoder_phys_vid_prepare_for_commit;
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ops->get_underrun_line_count =
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sde_encoder_phys_vid_get_underrun_line_count;
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}
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struct sde_encoder_phys *sde_encoder_phys_vid_init(
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@ -62,6 +62,7 @@
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#define INTF_MISR_SIGNATURE 0x184
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#define INTF_MUX 0x25C
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#define INTF_UNDERRUN_COUNT 0x268
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#define INTF_STATUS 0x26C
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#define INTF_AVR_CONTROL 0x270
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#define INTF_AVR_MODE 0x274
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@ -484,6 +485,23 @@ static u32 sde_hw_intf_get_line_count(struct sde_hw_intf *intf)
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return SDE_REG_READ(c, INTF_LINE_COUNT);
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}
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static u32 sde_hw_intf_get_underrun_line_count(struct sde_hw_intf *intf)
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{
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struct sde_hw_blk_reg_map *c;
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u32 hsync_period;
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if (!intf)
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return 0;
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c = &intf->hw;
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hsync_period = SDE_REG_READ(c, INTF_HSYNC_CTL);
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hsync_period = ((hsync_period & 0xffff0000) >> 16);
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return hsync_period ?
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SDE_REG_READ(c, INTF_UNDERRUN_COUNT) / hsync_period :
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0xebadebad;
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}
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static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
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struct sde_hw_tear_check *te)
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{
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@ -695,6 +713,7 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
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ops->setup_misr = sde_hw_intf_setup_misr;
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ops->collect_misr = sde_hw_intf_collect_misr;
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ops->get_line_count = sde_hw_intf_get_line_count;
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ops->get_underrun_line_count = sde_hw_intf_get_underrun_line_count;
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ops->avr_setup = sde_hw_intf_avr_setup;
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ops->avr_trigger = sde_hw_intf_avr_trigger;
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ops->avr_ctrl = sde_hw_intf_avr_ctrl;
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@ -68,6 +68,8 @@ struct intf_avr_params {
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* @ setup_misr: enables/disables MISR in HW register
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* @ collect_misr: reads and stores MISR data from HW register
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* @ get_line_count: reads current vertical line counter
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* @ get_underrun_line_count: reads current underrun pixel clock count and
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* converts it into line count
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* @bind_pingpong_blk: enable/disable the connection with pingpong which will
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* feed pixels to this interface
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*/
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@ -100,6 +102,7 @@ struct sde_hw_intf_ops {
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* is used for command mode panels
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*/
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u32 (*get_line_count)(struct sde_hw_intf *intf);
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u32 (*get_underrun_line_count)(struct sde_hw_intf *intf);
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void (*bind_pingpong_blk)(struct sde_hw_intf *intf,
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bool enable,
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