From 96262c74ed33949cb978bbb56883ca1938f68155 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Wed, 1 Apr 2020 14:44:47 +0800 Subject: [PATCH] soc: swr: update interval high register Update interval high register. Change-Id: I7c56ba801545f14607796977a976e535cf9da6ca Signed-off-by: Meng Wang --- soc/swr-mstr-ctrl.c | 8 +++++++- soc/swrm_registers.h | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index ae505ad0ddac..f0491b02ad47 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -1275,10 +1275,16 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank) bank)); reg[len] = SWRM_CMD_FIFO_WR_CMD; - val[len++] = SWR_REG_VAL_PACK(mport->sinterval, + val[len++] = SWR_REG_VAL_PACK(mport->sinterval & 0xFF, port_req->dev_num, 0x00, SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id, bank)); + + reg[len] = SWRM_CMD_FIFO_WR_CMD; + val[len++] = SWR_REG_VAL_PACK((mport->sinterval >> 8)& 0xFF, + port_req->dev_num, 0x00, + SWRS_DP_SAMPLE_CONTROL_2_BANK(slv_id, + bank)); /* Assumption: If different channels in the same port * on master is enabled for different slaves, then each * slave offset should be configured differently. diff --git a/soc/swrm_registers.h b/soc/swrm_registers.h index fcfabb2ce44e..ee9a12e6a8b8 100644 --- a/soc/swrm_registers.h +++ b/soc/swrm_registers.h @@ -232,6 +232,8 @@ SWRS_DP_REG_OFFSET(n, m)) #define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x122 + \ SWRS_DP_REG_OFFSET(n, m)) +#define SWRS_DP_SAMPLE_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x123 + \ + SWRS_DP_REG_OFFSET(n, m)) #define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x124 + \ SWRS_DP_REG_OFFSET(n, m)) #define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x125 + \