Merge "clk: qcom: clk-alpha-pll: Add support for Regera print registers"
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983f8387ac
@ -178,6 +178,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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[PLL_OFF_OPMODE] = 0x28,
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[PLL_OFF_STATUS] = 0x38,
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},
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[CLK_ALPHA_PLL_TYPE_REGERA] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_CONFIG_CTL] = 0x10,
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[PLL_OFF_CONFIG_CTL_U] = 0x14,
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[PLL_OFF_CONFIG_CTL_U1] = 0x18,
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[PLL_OFF_TEST_CTL] = 0x1c,
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[PLL_OFF_TEST_CTL_U] = 0x20,
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[PLL_OFF_TEST_CTL_U1] = 0x24,
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[PLL_OFF_OPMODE] = 0x28,
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[PLL_OFF_STATUS] = 0x38,
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},
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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@ -198,7 +211,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define PLL_OPMODE_STANDBY 0x0
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#define PLL_OPMODE_RUN 0x1
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#define PLL_OUT_MASK 0x7
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#define PLL_OUT_MASK 0x7
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#define PLL_OUT_RATE_MARGIN 500
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/* LUCID PLL specific settings and offsets */
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@ -3145,3 +3158,316 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
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.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
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};
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EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
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int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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u32 mode_regval;
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int ret;
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if (!config) {
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pr_err("PLL configuration missing.\n");
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return -EINVAL;
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}
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ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
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if (ret)
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return ret;
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if (mode_regval & PLL_LOCK_DET) {
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pr_warn("PLL is already enabled. Skipping configuration.\n");
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return 0;
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}
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if (config->alpha)
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regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
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if (config->l)
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regmap_write(regmap, PLL_L_VAL(pll), config->l);
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if (config->config_ctl_val)
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regmap_write(regmap, PLL_CONFIG_CTL(pll),
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config->config_ctl_val);
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if (config->config_ctl_hi_val)
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regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
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config->config_ctl_hi_val);
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if (config->config_ctl_hi1_val)
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regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
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config->config_ctl_hi1_val);
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if (config->user_ctl_val)
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regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
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if (config->test_ctl_val)
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regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
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if (config->test_ctl_hi_val)
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regmap_write(regmap, PLL_TEST_CTL_U(pll),
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config->test_ctl_hi_val);
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if (config->test_ctl_hi1_val)
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regmap_write(regmap, PLL_TEST_CTL_U1(pll),
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config->test_ctl_hi1_val);
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/* Set operation mode to OFF */
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regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);
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return 0;
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}
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static int clk_regera_pll_enable(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, l_val;
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int ret;
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ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
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if (ret)
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return ret;
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/* If in FSM mode, just vote for it */
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if (val & PLL_VOTE_FSM_ENA) {
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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return wait_for_pll_enable_active(pll);
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}
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ret = regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l_val);
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if (ret)
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return ret;
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/* PLL has lost it's L value, needs reconfiguration */
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if (!l_val) {
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ret = clk_regera_pll_configure(pll, pll->clkr.regmap,
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pll->config);
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if (ret) {
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pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
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return ret;
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}
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pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",
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clk_hw_get_name(hw));
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}
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/* Get the PLL out of bypass mode */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
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PLL_BYPASSNL, PLL_BYPASSNL);
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if (ret)
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return ret;
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/*
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* H/W requires a 1us delay between disabling the bypass and
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* de-asserting the reset.
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*/
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mb();
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udelay(1);
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ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
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PLL_RESET_N, PLL_RESET_N);
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if (ret)
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return ret;
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/* Set operation mode to RUN */
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regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_OPMODE_RUN);
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ret = wait_for_pll_enable_lock(pll);
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if (ret)
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return ret;
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/* Enable the PLL outputs */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
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ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
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if (ret)
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return ret;
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/* Enable the global PLL outputs */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
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PLL_OUTCTRL, PLL_OUTCTRL);
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if (ret)
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return ret;
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/* Ensure that the write above goes through before returning. */
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mb();
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return ret;
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}
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static void clk_regera_pll_disable(struct clk_hw *hw)
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{
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int ret;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, mask;
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ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
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if (ret)
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return;
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/* If in FSM mode, just unvote it */
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if (val & PLL_VOTE_FSM_ENA) {
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clk_disable_regmap(hw);
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return;
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}
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/* Disable the global PLL output */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
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PLL_OUTCTRL, 0);
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if (ret)
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return;
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/* Disable the PLL outputs */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
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ZONDA_PLL_OUT_MASK, 0);
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/* Put the PLL in bypass and reset */
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mask = PLL_RESET_N | PLL_BYPASSNL;
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ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
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if (ret)
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return;
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/* Place the PLL mode in OFF state */
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regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);
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}
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static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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unsigned long rrate;
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u32 l, regval, alpha_width = pll_alpha_width(pll);
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u64 a;
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int ret;
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ret = regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
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if (ret)
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return ret;
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/* PLL has lost it's L value, needs reconfiguration */
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if (!l) {
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ret = clk_regera_pll_configure(pll, pll->clkr.regmap,
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pll->config);
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if (ret) {
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pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
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return ret;
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}
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pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",
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clk_hw_get_name(hw));
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}
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rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
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/*
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* Due to a limited number of bits for fractional rate programming, the
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* rounded up rate could be marginally higher than the requested rate.
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*/
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if (rrate > (rate + PLL_OUT_RATE_MARGIN) || rrate < rate) {
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pr_err("Call set rate on the PLL with rounded rates!\n");
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return -EINVAL;
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}
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regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
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regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
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/* Return early if the PLL is disabled */
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ret = regmap_read(pll->clkr.regmap, PLL_OPMODE(pll), ®val);
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if (ret)
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return ret;
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if (regval == PLL_OPMODE_STANDBY)
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return 0;
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/* Wait before polling for the frequency latch */
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udelay(5);
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ret = wait_for_pll_enable_lock(pll);
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if (ret)
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return ret;
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/* Wait for PLL output to stabilize */
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udelay(100);
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return 0;
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}
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static unsigned long
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clk_regera_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 l, frac, alpha_width = pll_alpha_width(pll);
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regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
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regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
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return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
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}
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static void clk_regera_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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int size, i, val;
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static struct clk_register_data data[] = {
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{"PLL_MODE", PLL_OFF_MODE},
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{"PLL_L_VAL", PLL_OFF_L_VAL},
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{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
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{"PLL_USER_CTL", PLL_OFF_USER_CTL},
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{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
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{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
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{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},
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{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
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{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
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{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},
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{"PLL_OPMODE", PLL_OFF_OPMODE},
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{"PLL_STATUS", PLL_OFF_STATUS},
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};
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static struct clk_register_data data1[] = {
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{"APSS_PLL_VOTE", 0x0},
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};
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size = ARRAY_SIZE(data);
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for (i = 0; i < size; i++) {
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regmap_read(pll->clkr.regmap, pll->offset +
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pll->regs[data[i].offset], &val);
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seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
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}
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regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],
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&val);
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if (val & PLL_FSM_ENA) {
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regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
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data1[0].offset, &val);
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seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);
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}
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}
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static struct clk_regmap_ops clk_regera_pll_regmap_ops = {
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.list_registers = clk_regera_pll_list_registers,
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};
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static void clk_regera_pll_init(struct clk_hw *hw)
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{
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struct clk_regmap *rclk = to_clk_regmap(hw);
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if (!rclk->ops)
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rclk->ops = &clk_regera_pll_regmap_ops;
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}
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const struct clk_ops clk_regera_pll_ops = {
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.prepare = clk_prepare_regmap,
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.unprepare = clk_unprepare_regmap,
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.pre_rate_change = clk_pre_change_regmap,
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.post_rate_change = clk_post_change_regmap,
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.enable = clk_regera_pll_enable,
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.disable = clk_regera_pll_disable,
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.is_enabled = clk_alpha_pll_is_enabled,
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.recalc_rate = clk_regera_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.set_rate = clk_regera_pll_set_rate,
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.debug_init = clk_common_debug_init,
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.init = clk_regera_pll_init,
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#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG
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.list_rate_vdd_level = clk_list_rate_vdd_level,
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#endif
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};
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EXPORT_SYMBOL_GPL(clk_regera_pll_ops);
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@ -21,6 +21,7 @@ enum {
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CLK_ALPHA_PLL_TYPE_ZONDA,
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CLK_ALPHA_PLL_TYPE_LUCID_5LPE,
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CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,
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CLK_ALPHA_PLL_TYPE_REGERA,
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CLK_ALPHA_PLL_TYPE_MAX,
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};
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@ -153,6 +154,8 @@ extern const struct clk_ops clk_trion_fixed_pll_ops;
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extern const struct clk_ops clk_trion_pll_postdiv_ops;
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extern const struct clk_ops clk_trion_pll_ops;
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extern const struct clk_ops clk_regera_pll_ops;
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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@ -169,4 +172,6 @@ int clk_zonda_5lpe_pll_configure(struct clk_alpha_pll *pll,
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const struct alpha_pll_config *config);
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int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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#endif
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