disp: msm: sde: report intf interrupt status during underrun
Add the INTF interrupt status register value to the underrun line count event log to assist in debugging these issues. Change-Id: I847cb12f8b4565d5f04667e0abda5d051a6194b2 Signed-off-by: Steve Cohen <cohens@codeaurora.org>
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@ -1198,6 +1198,7 @@ static u32 sde_encoder_phys_vid_get_underrun_line_count(
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struct sde_encoder_phys *phys_enc)
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{
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u32 underrun_linecount = 0xebadebad;
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u32 intf_intr_status = 0xebadebad;
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struct intf_status intf_status = {0};
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if (!phys_enc)
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@ -1215,8 +1216,13 @@ static u32 sde_encoder_phys_vid_get_underrun_line_count(
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phys_enc->hw_intf->ops.get_underrun_line_count(
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phys_enc->hw_intf);
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if (phys_enc->hw_intf->ops.get_intr_status)
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intf_intr_status = phys_enc->hw_intf->ops.get_intr_status(
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phys_enc->hw_intf);
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SDE_EVT32(DRMID(phys_enc->parent), underrun_linecount,
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intf_status.frame_count, intf_status.line_count);
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intf_status.frame_count, intf_status.line_count,
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intf_intr_status);
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return underrun_linecount;
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}
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@ -531,6 +531,14 @@ static u32 sde_hw_intf_get_underrun_line_count(struct sde_hw_intf *intf)
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0xebadebad;
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}
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static u32 sde_hw_intf_get_intr_status(struct sde_hw_intf *intf)
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{
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if (!intf)
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return -EINVAL;
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return SDE_REG_READ(&intf->hw, INTF_INTR_STATUS);
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}
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static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
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struct sde_hw_tear_check *te)
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{
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@ -783,6 +791,7 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
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ops->collect_misr = sde_hw_intf_collect_misr;
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ops->get_line_count = sde_hw_intf_get_line_count;
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ops->get_underrun_line_count = sde_hw_intf_get_underrun_line_count;
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ops->get_intr_status = sde_hw_intf_get_intr_status;
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ops->avr_setup = sde_hw_intf_avr_setup;
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ops->avr_trigger = sde_hw_intf_avr_trigger;
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ops->avr_ctrl = sde_hw_intf_avr_ctrl;
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@ -206,6 +206,11 @@ struct sde_hw_intf_ops {
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* Enable processing of 2 pixels per clock
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*/
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void (*enable_wide_bus)(struct sde_hw_intf *intf, bool enable);
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/**
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* Get the INTF interrupt status
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*/
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u32 (*get_intr_status)(struct sde_hw_intf *intf);
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};
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struct sde_hw_intf {
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