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disp: msm: dsi: Add DSI PLL support for 7nm_v4_1 arch

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Add DSI PLL support for 7nm_v4_1 architecture

Change-Id: I4adf1ec6ed40fea16aa80579d34a3c918faa8478
Signed-off-by: Kai Xing <quic_kxing@quicinc.com>
This commit is contained in:
Kai Xing 2022-05-18 07:45:08 +05:30
parent 6a0f0b0f1f
commit a965033fba
4 changed files with 22 additions and 2 deletions
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1
config/konadisp.conf
View File

@ -11,3 +11,4 @@ export CONFIG_QCOM_MDSS_PLL=y
export CONFIG_MSM_SDE_ROTATOR=y export CONFIG_MSM_SDE_ROTATOR=y
export CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y export CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y
export CONFIG_DRM_SDE_RSC=y export CONFIG_DRM_SDE_RSC=y
export CONFIG_DISPLAY_BUILD=y

5
msm/dsi/dsi_pll.c
View File

@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/ */
@ -21,6 +23,7 @@ static int dsi_pll_clock_register(struct platform_device *pdev,
switch (pll_res->pll_revision) { switch (pll_res->pll_revision) {
case DSI_PLL_5NM: case DSI_PLL_5NM:
case DSI_PLL_7NM_V4_1:
rc = dsi_pll_clock_register_5nm(pdev, pll_res); rc = dsi_pll_clock_register_5nm(pdev, pll_res);
break; break;
case DSI_PLL_10NM: case DSI_PLL_10NM:
@ -150,6 +153,8 @@ int dsi_pll_init(struct platform_device *pdev, struct dsi_pll_resource **pll)
if (!strcmp(label, "dsi_pll_5nm")) if (!strcmp(label, "dsi_pll_5nm"))
pll_res->pll_revision = DSI_PLL_5NM; pll_res->pll_revision = DSI_PLL_5NM;
else if (!strcmp(label, "dsi_pll_7nm_v4_1"))
pll_res->pll_revision = DSI_PLL_7NM_V4_1;
else if (!strcmp(label, "dsi_pll_10nm")) else if (!strcmp(label, "dsi_pll_10nm"))
pll_res->pll_revision = DSI_PLL_10NM; pll_res->pll_revision = DSI_PLL_10NM;
else else

3
msm/dsi/dsi_pll.h
View File

@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/ */
@ -54,6 +56,7 @@ struct lpfr_cfg {
enum { enum {
DSI_PLL_5NM, DSI_PLL_5NM,
DSI_PLL_7NM_V4_1,
DSI_PLL_10NM, DSI_PLL_10NM,
DSI_UNKNOWN_PLL, DSI_UNKNOWN_PLL,
}; };

15
msm/dsi/dsi_pll_5nm.c
View File

@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/ */
@ -291,6 +293,13 @@ static inline bool dsi_pll_5nm_is_hw_revision(
true : false; true : false;
} }
static inline bool dsi_pll_7nm_v4_1_is_hw_revision(
struct dsi_pll_resource *rsc)
{
return (rsc->pll_revision == DSI_PLL_7NM_V4_1) ?
true : false;
}
static inline int pll_reg_read(void *context, unsigned int reg, static inline int pll_reg_read(void *context, unsigned int reg,
unsigned int *val) unsigned int *val)
{ {
@ -2591,7 +2600,8 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev,
dsi0pll_vco_clk.priv = pll_res; dsi0pll_vco_clk.priv = pll_res;
dsi0pll_shadow_vco_clk.priv = pll_res; dsi0pll_shadow_vco_clk.priv = pll_res;
if (dsi_pll_5nm_is_hw_revision(pll_res)) { if (dsi_pll_5nm_is_hw_revision(pll_res) ||
dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) {
dsi0pll_vco_clk.min_rate = 600000000; dsi0pll_vco_clk.min_rate = 600000000;
dsi0pll_vco_clk.max_rate = 5000000000; dsi0pll_vco_clk.max_rate = 5000000000;
dsi0pll_shadow_vco_clk.min_rate = 600000000; dsi0pll_shadow_vco_clk.min_rate = 600000000;
@ -2660,7 +2670,8 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev,
dsi1pll_vco_clk.priv = pll_res; dsi1pll_vco_clk.priv = pll_res;
dsi1pll_shadow_vco_clk.priv = pll_res; dsi1pll_shadow_vco_clk.priv = pll_res;
if (dsi_pll_5nm_is_hw_revision(pll_res)) { if (dsi_pll_5nm_is_hw_revision(pll_res) ||
dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) {
dsi1pll_vco_clk.min_rate = 600000000; dsi1pll_vco_clk.min_rate = 600000000;
dsi1pll_vco_clk.max_rate = 5000000000; dsi1pll_vco_clk.max_rate = 5000000000;
dsi1pll_shadow_vco_clk.min_rate = 600000000; dsi1pll_shadow_vco_clk.min_rate = 600000000;