From db072e5fb642755861448eb8f201bf230d78608c Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Wed, 9 Dec 2020 23:54:05 +0530 Subject: [PATCH] msm: kgsl: Fix IFPC abort due to preemption keepalive Consider a scenario when preemption timer expires and while re-checking preemption status in _a6xx_preemption_fault, if preemption is successful, the state is transitioned to complete state. When dispatcher is scheduled, it calls _a6xx_preemption_done. Here, we are not clearing preemption keepalive bit which will prevent GMU to enter into IFPC state. Fix it by clearing this bit. Similar situation can happen when we receive preempt interrupt with non-zero status. Change-Id: I7f2e5a139be766b363bc8d1941b1c6006e6a9ffd Signed-off-by: Kamal Agrawal --- drivers/gpu/msm/adreno_a6xx_preempt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c index 22431a4a90b8..f99e93ca377e 100644 --- a/drivers/gpu/msm/adreno_a6xx_preempt.c +++ b/drivers/gpu/msm/adreno_a6xx_preempt.c @@ -128,6 +128,17 @@ static void _a6xx_preemption_done(struct adreno_device *adreno_dev) adreno_dev->preempt.count++; + /* + * In normal scenarios, preemption keep alive bit is cleared during + * CP interrupt callback. However, if preemption is successful + * immediately after preemption timer expires or there is a preemption + * interrupt with non-zero status, the state is transitioned to complete + * state. Once dispatcher is scheduled, it calls this function. + * We can now safely clear the preemption keepalive bit, allowing + * power collapse to resume its regular activity. + */ + _power_collapse_set(adreno_dev, false); + del_timer_sync(&adreno_dev->preempt.timer); kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_LEVEL_STATUS, &status);