This is the 5.4.13 stable release
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uninitialized status value regression RDMA/bnxt_re: Avoid freeing MR resources if dereg fails RDMA/bnxt_re: Fix Send Work Entry state check while polling completions IB/hfi1: Don't cancel unused work item mtd: rawnand: stm32_fmc2: avoid to lock the CPU bus i2c: bcm2835: Store pointer to bus clock ASoC: SOF: imx8: fix memory allocation failure check on priv->pd_dev ASoC: soc-core: Set dpcm_playback / dpcm_capture ASoC: stm32: spdifrx: fix inconsistent lock state ASoC: stm32: spdifrx: fix race condition in irq handler ASoC: stm32: spdifrx: fix input pin state management pinctrl: lochnagar: select GPIOLIB netfilter: nft_flow_offload: fix underflow in flowtable reference counter ASoC: SOF: imx8: Fix dsp_box offset mtd: onenand: omap2: Pass correct flags for prep_dma_memcpy gpio: zynq: Fix for bug in zynq_gpio_restore_context API pinctrl: meson: Fix wrong shift value when get drive-strength selftests: loopback.sh: skip this test if the driver does not support iommu/vt-d: Unlink device if failed to add to group iommu: Remove device link to group on failure bpf: cgroup: prevent out-of-order release of cgroup bpf fs: move guard_bio_eod() after bio_set_op_attrs scsi: mpt3sas: Fix double free in attach error handling gpio: Fix error message on out-of-range GPIO in lookup table PM / devfreq: tegra: Add COMMON_CLK dependency PCI: amlogic: Fix probed clock names drm/tegra: Fix ordering of cleanup code hsr: add hsr root debugfs directory hsr: rename debugfs file when interface name is changed hsr: reset network header when supervision frame is created s390/qeth: fix qdio teardown after early init error s390/qeth: fix false reporting of VNIC CHAR config failure s390/qeth: Fix vnicc_is_in_use if rx_bcast not set s390/qeth: vnicc Fix init to default s390/qeth: fix initialization on old HW cifs: Adjust indentation in smb2_open_file scsi: smartpqi: Update attribute name to `driver_version` MAINTAINERS: Append missed file to the database ath9k: use iowrite32 over __raw_writel can: j1939: fix address claim code example dt-bindings: reset: Fix brcmstb-reset example reset: brcmstb: Remove resource checks afs: Fix missing cell comparison in afs_test_super() perf vendor events s390: Remove name from L1D_RO_EXCL_WRITES description syscalls/x86: Wire up COMPAT_SYSCALL_DEFINE0 syscalls/x86: Use COMPAT_SYSCALL_DEFINE0 for IA32 (rt_)sigreturn syscalls/x86: Use the correct function type for sys_ni_syscall syscalls/x86: Fix function types in COND_SYSCALL hsr: fix slab-out-of-bounds Read in hsr_debugfs_rename() btrfs: simplify inode locking for RWF_NOWAIT netfilter: nf_tables_offload: release flow_rule on error from commit path netfilter: nft_meta: use 64-bit time arithmetic ASoC: dt-bindings: mt8183: add missing update ASoC: simple_card_utils.h: Add missing include ASoC: fsl_esai: Add spin lock to protect reset, stop and start ASoC: SOF: Intel: Broadwell: clarify mutual exclusion with legacy driver ASoC: core: Fix compile warning with CONFIG_DEBUG_FS=n ASoC: rsnd: fix DALIGN register for SSIU RDMA/hns: Prevent undefined behavior in hns_roce_set_user_sq_size() RDMA/hns: remove a redundant le16_to_cpu RDMA/hns: Modify return value of restrack functions RDMA/counter: Prevent QP counter manual binding in auto mode RDMA/siw: Fix port number endianness in a debug message RDMA/hns: Fix build error again RDMA/hns: Release qp resources when failed to destroy qp xprtrdma: Add unique trace points for posting Local Invalidate WRs xprtrdma: Connection becomes unstable after a reconnect xprtrdma: Fix MR list handling xprtrdma: Close window between waking RPC senders and posting Receives RDMA/hns: Fix to support 64K page for srq RDMA/hns: Bugfix for qpc/cqc timer configuration rdma: Remove nes ABI header RDMA/mlx5: Return proper error value RDMA/srpt: Report the SCSI residual to the initiator uaccess: Add non-pagefault user-space write function bpf: Make use of probe_user_write in probe write helper bpf: skmsg, fix potential psock NULL pointer dereference bpf: Support pre-2.25-binutils objcopy for vmlinux BTF libbpf: Fix Makefile' libbpf symbol mismatch diagnostic afs: Fix use-after-loss-of-ref afs: Fix afs_lookup() to not clobber the version on a new dentry keys: Fix request_key() cache scsi: enclosure: Fix stale device oops with hot replug scsi: sd: Clear sdkp->protection_type if disk is reformatted without PI platform/mellanox: fix potential deadlock in the tmfifo driver platform/x86: asus-wmi: Fix keyboard brightness cannot be set to 0 platform/x86: GPD pocket fan: Use default values when wrong modparams are given asm-generic/nds32: don't redefine cacheflush primitives Documentation/ABI: Fix documentation inconsistency for mlxreg-io sysfs interfaces Documentation/ABI: Add missed attribute for mlxreg-io sysfs interfaces xprtrdma: Fix create_qp crash on device unload xprtrdma: Fix completion wait during device removal xprtrdma: Fix oops in Receive handler after device removal dm: add dm-clone to the documentation index scsi: ufs: Give an unique ID to each ufs-bsg crypto: cavium/nitrox - fix firmware assignment to AE cores crypto: hisilicon - select NEED_SG_DMA_LENGTH in qm Kconfig crypto: arm64/aes-neonbs - add return value of skcipher_walk_done() in __xts_crypt() crypto: virtio - implement missing support for output IVs crypto: algif_skcipher - Use chunksize instead of blocksize crypto: geode-aes - convert to skcipher API and make thread-safe NFSv2: Fix a typo in encode_sattr() nfsd: Fix cld_net->cn_tfm initialization nfsd: v4 support requires CRYPTO_SHA256 NFSv4.x: Handle bad/dead sessions correctly in nfs41_sequence_process() NFSv4.x: Drop the slot if nfs4_delegreturn_prepare waits for layoutreturn iio: imu: st_lsm6dsx: fix gyro gain definitions for LSM9DS1 iio: imu: adis16480: assign bias value only if operation succeeded mei: fix modalias documentation clk: meson: axg-audio: fix regmap last register clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume clk: Fix memory leak in clk_unregister() dmaengine: dw: platform: Mark 'hclk' clock optional clk: imx: pll14xx: Fix quick switch of S/K parameter rsi: fix potential null dereference in rsi_probe() affs: fix a memory leak in affs_remount pinctl: ti: iodelay: fix error checking on pinctrl_count_index_with_args call pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSR pinctrl: sh-pfc: Do not use platform_get_irq() to count interrupts pinctrl: lewisburg: Update pin list according to v1.1v6 PCI: pciehp: Do not disable interrupt twice on suspend Revert "drm/virtio: switch virtio_gpu_wait_ioctl() to gem helper." drm/amdgpu: cleanup creating BOs at fixed location (v2) drm/amdgpu/discovery: reserve discovery data at the top of VRAM scsi: sd: enable compat ioctls for sed-opal arm64: dts: apq8096-db820c: Increase load on l21 for SDCARD gfs2: add compat_ioctl support af_unix: add compat_ioctl support compat_ioctl: handle SIOCOUTQNSD PCI: aardvark: Use LTSSM state to build link training flag PCI: aardvark: Fix PCI_EXP_RTCTL register configuration PCI: dwc: Fix find_next_bit() usage PCI: Fix missing bridge dma_ranges resource list cleanup PCI/PM: Clear PCIe PME Status even for legacy power management tools: PCI: Fix fd leakage PCI/PTM: Remove spurious "d" from granularity message powerpc/powernv: Disable native PCIe port management MIPS: PCI: remember nasid changed by set interrupt affinity MIPS: Loongson: Fix return value of loongson_hwmon_init MIPS: SGI-IP27: Fix crash, when CPUs are disabled via nr_cpus parameter tty: serial: imx: use the sg count from dma_map_sg tty: serial: pch_uart: correct usage of dma_unmap_sg ARM: 8943/1: Fix topology setup in case of CPU hotplug for CONFIG_SCHED_MC media: ov6650: Fix incorrect use of JPEG colorspace media: ov6650: Fix some format attributes not under control media: ov6650: Fix .get_fmt() V4L2_SUBDEV_FORMAT_TRY support media: ov6650: Fix default format not applied on device probe media: rcar-vin: Fix incorrect return statement in rvin_try_format() media: hantro: h264: Fix the frame_num wraparound case media: v4l: cadence: Fix how unsued lanes are handled in 'csi2rx_start()' media: exynos4-is: Fix recursive locking in isp_video_release() media: coda: fix deadlock between decoder picture run and start command media: cedrus: Use correct H264 8x8 scaling list media: hantro: Do not reorder H264 scaling list media: aspeed-video: Fix memory leaks in aspeed_video_probe media: hantro: Set H264 FIELDPIC_FLAG_E flag correctly iommu/mediatek: Correct the flush_iotlb_all callback iommu/mediatek: Add a new tlb_lock for tlb_flush memory: mtk-smi: Add PM suspend and resume ops Revert "ubifs: Fix memory leak bug in alloc_ubifs_info() error path" ubifs: Fixed missed le64_to_cpu() in journal ubifs: do_kill_orphans: Fix a memory leak bug spi: sprd: Fix the incorrect SPI register mtd: spi-nor: fix silent truncation in spi_nor_read() mtd: spi-nor: fix silent truncation in spi_nor_read_raw() spi: pxa2xx: Set controller->max_transfer_size in dma mode spi: atmel: fix handling of cs_change set on non-last xfer spi: rspi: Use platform_get_irq_byname_optional() for optional irqs spi: lpspi: fix memory leak in fsl_lpspi_probe iwlwifi: mvm: consider ieee80211 station max amsdu value rtlwifi: Remove unnecessary NULL check in rtl_regd_init iwlwifi: mvm: fix support for single antenna diversity sch_cake: Add missing NLA policy entry TCA_CAKE_SPLIT_GSO f2fs: fix potential overflow NFSD fixing possible null pointer derefering in copy offload rtc: msm6242: Fix reading of 10-hour digit rtc: brcmstb-waketimer: add missed clk_disable_unprepare rtc: bd70528: Add MODULE ALIAS to autoload module gpio: mpc8xxx: Add platform device to gpiochip->parent scsi: libcxgbi: fix NULL pointer dereference in cxgbi_device_destroy() scsi: target/iblock: Fix protection error with blocks greater than 512B selftests: firmware: Fix it to do root uid check and skip rseq/selftests: Turn off timeout setting riscv: export flush_icache_all to modules mips: cacheinfo: report shared CPU map mips: Fix gettimeofday() in the vdso library tomoyo: Suppress RCU warning at list_for_each_entry_rcu(). MIPS: Prevent link failure with kcov instrumentation drm/arm/mali: make malidp_mw_connector_helper_funcs static rxrpc: Unlock new call in rxrpc_new_incoming_call() rather than the caller rxrpc: Don't take call->user_mutex in rxrpc_new_incoming_call() rxrpc: Fix missing security check on incoming calls dmaengine: k3dma: Avoid null pointer traversal s390/qeth: lock the card while changing its hsuid ioat: ioat_alloc_ring() failure handling. drm/amdgpu: enable gfxoff for raven1 refresh media: intel-ipu3: Align struct ipu3_uapi_awb_fr_config_s to 32 bytes kbuild/deb-pkg: annotate libelf-dev dependency as :native hexagon: parenthesize registers in asm predicates hexagon: work around compiler crash ocfs2: call journal flush to mark journal as empty after journal recovery when mount Linux 5.4.13 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I90734cd9d80f000e05a8109a529916ae641cdede
This commit is contained in:
Greg Kroah-Hartman
commit
b0b02162a4
@ -29,13 +29,13 @@ Description: This file shows the system fans direction:
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|
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The files are read only.
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||||
|
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What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable
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What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
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Date: November 2018
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KernelVersion: 5.0
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Contact: Vadim Pasternak <vadimpmellanox.com>
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Description: These files show with which CPLD versions have been burned
|
||||
on LED board.
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||||
on LED or Gearbox board.
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The files are read only.
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@ -121,6 +121,15 @@ Description: These files show the system reset cause, as following: ComEx
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The files are read only.
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What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version
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Date: November 2018
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KernelVersion: 5.0
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Contact: Vadim Pasternak <vadimpmellanox.com>
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Description: These files show with which CPLD versions have been burned
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on LED board.
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The files are read only.
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Date: June 2019
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KernelVersion: 5.3
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Contact: Vadim Pasternak <vadimpmellanox.com>
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@ -4,7 +4,7 @@ KernelVersion: 3.10
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Contact: Samuel Ortiz <sameo@linux.intel.com>
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linux-mei@linux.intel.com
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Description: Stores the same MODALIAS value emitted by uevent
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Format: mei:<mei device name>:<device uuid>:
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Format: mei:<mei device name>:<device uuid>:<protocol version>
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What: /sys/bus/mei/devices/.../name
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Date: May 2015
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@ -8,6 +8,7 @@ Device Mapper
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cache-policies
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cache
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delay
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dm-clone
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dm-crypt
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dm-flakey
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dm-init
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@ -22,6 +22,6 @@ Example:
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};
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ðernet_switch {
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resets = <&reset>;
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resets = <&reset 26>;
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reset-names = "switch";
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};
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@ -2,9 +2,11 @@ MT8183 with MT6358, TS3A227 and MAX98357 CODECS
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Required properties:
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- compatible : "mediatek,mt8183_mt6358_ts3a227_max98357"
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- mediatek,headset-codec: the phandles of ts3a227 codecs
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- mediatek,platform: the phandle of MT8183 ASoC platform
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Optional properties:
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- mediatek,headset-codec: the phandles of ts3a227 codecs
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Example:
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sound {
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@ -339,7 +339,7 @@ To claim an address following code example can be used:
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.pgn = J1939_PGN_ADDRESS_CLAIMED,
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.pgn_mask = J1939_PGN_PDU1_MAX,
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}, {
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.pgn = J1939_PGN_ADDRESS_REQUEST,
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.pgn = J1939_PGN_REQUEST,
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.pgn_mask = J1939_PGN_PDU1_MAX,
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}, {
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.pgn = J1939_PGN_ADDRESS_COMMANDED,
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@ -29,7 +29,7 @@ smartpqi specific entries in /sys
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smartpqi host attributes:
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-------------------------
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/sys/class/scsi_host/host*/rescan
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/sys/class/scsi_host/host*/version
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/sys/class/scsi_host/host*/driver_version
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The host rescan attribute is a write only attribute. Writing to this
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attribute will trigger the driver to scan for new, changed, or removed
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@ -6973,6 +6973,7 @@ L: linux-acpi@vger.kernel.org
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S: Maintained
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F: Documentation/firmware-guide/acpi/gpio-properties.rst
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F: drivers/gpio/gpiolib-acpi.c
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F: drivers/gpio/gpiolib-acpi.h
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GPIO IR Transmitter
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M: Sean Young <sean@mess.org>
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2
Makefile
2
Makefile
@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 4
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SUBLEVEL = 12
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SUBLEVEL = 13
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EXTRAVERSION =
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NAME = Kleptomaniac Octopus
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@ -240,6 +240,10 @@ int __cpu_disable(void)
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if (ret)
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return ret;
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#ifdef CONFIG_GENERIC_ARCH_TOPOLOGY
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remove_cpu_topology(cpu);
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#endif
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/*
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* Take this CPU offline. Once we clear this, we can't return,
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* and we must not schedule until we're ready to give up the cpu.
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@ -196,9 +196,8 @@ void store_cpu_topology(unsigned int cpuid)
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struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
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unsigned int mpidr;
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/* If the cpu topology has been already set, just return */
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if (cpuid_topo->core_id != -1)
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return;
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if (cpuid_topo->package_id != -1)
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goto topology_populated;
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mpidr = read_cpuid_mpidr();
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@ -231,14 +230,15 @@ void store_cpu_topology(unsigned int cpuid)
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cpuid_topo->package_id = -1;
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}
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update_siblings_masks(cpuid);
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update_cpu_capacity(cpuid);
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pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
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cpuid, cpu_topology[cpuid].thread_id,
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cpu_topology[cpuid].core_id,
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cpu_topology[cpuid].package_id, mpidr);
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topology_populated:
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update_siblings_masks(cpuid);
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}
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static inline int cpu_corepower_flags(void)
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@ -623,6 +623,8 @@
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l21 {
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regulator-min-microvolt = <2950000>;
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regulator-max-microvolt = <2950000>;
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regulator-allow-set-load;
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regulator-system-load = <200000>;
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};
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l22 {
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regulator-min-microvolt = <3300000>;
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@ -384,7 +384,7 @@ static int __xts_crypt(struct skcipher_request *req, bool encrypt,
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goto xts_tail;
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kernel_neon_end();
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skcipher_walk_done(&walk, nbytes);
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err = skcipher_walk_done(&walk, nbytes);
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}
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if (err || likely(!tail))
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@ -91,7 +91,7 @@ static inline void atomic_##op(int i, atomic_t *v) \
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"1: %0 = memw_locked(%1);\n" \
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" %0 = "#op "(%0,%2);\n" \
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" memw_locked(%1,P3)=%0;\n" \
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" if !P3 jump 1b;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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@ -107,7 +107,7 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
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"1: %0 = memw_locked(%1);\n" \
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" %0 = "#op "(%0,%2);\n" \
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" memw_locked(%1,P3)=%0;\n" \
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" if !P3 jump 1b;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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@ -124,7 +124,7 @@ static inline int atomic_fetch_##op(int i, atomic_t *v) \
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"1: %0 = memw_locked(%2);\n" \
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" %1 = "#op "(%0,%3);\n" \
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" memw_locked(%2,P3)=%1;\n" \
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" if !P3 jump 1b;\n" \
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" if (!P3) jump 1b;\n" \
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: "=&r" (output), "=&r" (val) \
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: "r" (&v->counter), "r" (i) \
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: "memory", "p3" \
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@ -173,7 +173,7 @@ static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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" }"
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" memw_locked(%2, p3) = %1;"
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" {"
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" if !p3 jump 1b;"
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" if (!p3) jump 1b;"
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" }"
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"2:"
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: "=&r" (__oldval), "=&r" (tmp)
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@ -38,7 +38,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr)
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"1: R12 = memw_locked(R10);\n"
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" { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n"
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" memw_locked(R10,P1) = R12;\n"
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" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
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" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (nr)
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: "r10", "r11", "r12", "p0", "p1", "memory"
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@ -62,7 +62,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr)
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"1: R12 = memw_locked(R10);\n"
|
||||
" { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n"
|
||||
" memw_locked(R10,P1) = R12;\n"
|
||||
" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
|
||||
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
|
||||
: "=&r" (oldval)
|
||||
: "r" (addr), "r" (nr)
|
||||
: "r10", "r11", "r12", "p0", "p1", "memory"
|
||||
@ -88,7 +88,7 @@ static inline int test_and_change_bit(int nr, volatile void *addr)
|
||||
"1: R12 = memw_locked(R10);\n"
|
||||
" { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n"
|
||||
" memw_locked(R10,P1) = R12;\n"
|
||||
" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
|
||||
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
|
||||
: "=&r" (oldval)
|
||||
: "r" (addr), "r" (nr)
|
||||
: "r10", "r11", "r12", "p0", "p1", "memory"
|
||||
@ -223,7 +223,7 @@ static inline int ffs(int x)
|
||||
int r;
|
||||
|
||||
asm("{ P0 = cmp.eq(%1,#0); %0 = ct0(%1);}\n"
|
||||
"{ if P0 %0 = #0; if !P0 %0 = add(%0,#1);}\n"
|
||||
"{ if (P0) %0 = #0; if (!P0) %0 = add(%0,#1);}\n"
|
||||
: "=&r" (r)
|
||||
: "r" (x)
|
||||
: "p0");
|
||||
|
||||
@ -30,7 +30,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
|
||||
__asm__ __volatile__ (
|
||||
"1: %0 = memw_locked(%1);\n" /* load into retval */
|
||||
" memw_locked(%1,P0) = %2;\n" /* store into memory */
|
||||
" if !P0 jump 1b;\n"
|
||||
" if (!P0) jump 1b;\n"
|
||||
: "=&r" (retval)
|
||||
: "r" (ptr), "r" (x)
|
||||
: "memory", "p0"
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
/* For example: %1 = %4 */ \
|
||||
insn \
|
||||
"2: memw_locked(%3,p2) = %1;\n" \
|
||||
" if !p2 jump 1b;\n" \
|
||||
" if (!p2) jump 1b;\n" \
|
||||
" %1 = #0;\n" \
|
||||
"3:\n" \
|
||||
".section .fixup,\"ax\"\n" \
|
||||
@ -84,10 +84,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval,
|
||||
"1: %1 = memw_locked(%3)\n"
|
||||
" {\n"
|
||||
" p2 = cmp.eq(%1,%4)\n"
|
||||
" if !p2.new jump:NT 3f\n"
|
||||
" if (!p2.new) jump:NT 3f\n"
|
||||
" }\n"
|
||||
"2: memw_locked(%3,p2) = %5\n"
|
||||
" if !p2 jump 1b\n"
|
||||
" if (!p2) jump 1b\n"
|
||||
"3:\n"
|
||||
".section .fixup,\"ax\"\n"
|
||||
"4: %0 = #%6\n"
|
||||
|
||||
@ -30,9 +30,9 @@ static inline void arch_read_lock(arch_rwlock_t *lock)
|
||||
__asm__ __volatile__(
|
||||
"1: R6 = memw_locked(%0);\n"
|
||||
" { P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
|
||||
" { if !P3 jump 1b; }\n"
|
||||
" { if (!P3) jump 1b; }\n"
|
||||
" memw_locked(%0,P3) = R6;\n"
|
||||
" { if !P3 jump 1b; }\n"
|
||||
" { if (!P3) jump 1b; }\n"
|
||||
:
|
||||
: "r" (&lock->lock)
|
||||
: "memory", "r6", "p3"
|
||||
@ -46,7 +46,7 @@ static inline void arch_read_unlock(arch_rwlock_t *lock)
|
||||
"1: R6 = memw_locked(%0);\n"
|
||||
" R6 = add(R6,#-1);\n"
|
||||
" memw_locked(%0,P3) = R6\n"
|
||||
" if !P3 jump 1b;\n"
|
||||
" if (!P3) jump 1b;\n"
|
||||
:
|
||||
: "r" (&lock->lock)
|
||||
: "memory", "r6", "p3"
|
||||
@ -61,7 +61,7 @@ static inline int arch_read_trylock(arch_rwlock_t *lock)
|
||||
__asm__ __volatile__(
|
||||
" R6 = memw_locked(%1);\n"
|
||||
" { %0 = #0; P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
|
||||
" { if !P3 jump 1f; }\n"
|
||||
" { if (!P3) jump 1f; }\n"
|
||||
" memw_locked(%1,P3) = R6;\n"
|
||||
" { %0 = P3 }\n"
|
||||
"1:\n"
|
||||
@ -78,9 +78,9 @@ static inline void arch_write_lock(arch_rwlock_t *lock)
|
||||
__asm__ __volatile__(
|
||||
"1: R6 = memw_locked(%0)\n"
|
||||
" { P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
|
||||
" { if !P3 jump 1b; }\n"
|
||||
" { if (!P3) jump 1b; }\n"
|
||||
" memw_locked(%0,P3) = R6;\n"
|
||||
" { if !P3 jump 1b; }\n"
|
||||
" { if (!P3) jump 1b; }\n"
|
||||
:
|
||||
: "r" (&lock->lock)
|
||||
: "memory", "r6", "p3"
|
||||
@ -94,7 +94,7 @@ static inline int arch_write_trylock(arch_rwlock_t *lock)
|
||||
__asm__ __volatile__(
|
||||
" R6 = memw_locked(%1)\n"
|
||||
" { %0 = #0; P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
|
||||
" { if !P3 jump 1f; }\n"
|
||||
" { if (!P3) jump 1f; }\n"
|
||||
" memw_locked(%1,P3) = R6;\n"
|
||||
" %0 = P3;\n"
|
||||
"1:\n"
|
||||
@ -117,9 +117,9 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
|
||||
__asm__ __volatile__(
|
||||
"1: R6 = memw_locked(%0);\n"
|
||||
" P3 = cmp.eq(R6,#0);\n"
|
||||
" { if !P3 jump 1b; R6 = #1; }\n"
|
||||
" { if (!P3) jump 1b; R6 = #1; }\n"
|
||||
" memw_locked(%0,P3) = R6;\n"
|
||||
" { if !P3 jump 1b; }\n"
|
||||
" { if (!P3) jump 1b; }\n"
|
||||
:
|
||||
: "r" (&lock->lock)
|
||||
: "memory", "r6", "p3"
|
||||
@ -139,7 +139,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
|
||||
__asm__ __volatile__(
|
||||
" R6 = memw_locked(%1);\n"
|
||||
" P3 = cmp.eq(R6,#0);\n"
|
||||
" { if !P3 jump 1f; R6 = #1; %0 = #0; }\n"
|
||||
" { if (!P3) jump 1f; R6 = #1; %0 = #0; }\n"
|
||||
" memw_locked(%1,P3) = R6;\n"
|
||||
" %0 = P3;\n"
|
||||
"1:\n"
|
||||
|
||||
@ -11,8 +11,6 @@
|
||||
#include <linux/thread_info.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
register unsigned long current_frame_pointer asm("r30");
|
||||
|
||||
struct stackframe {
|
||||
unsigned long fp;
|
||||
unsigned long rets;
|
||||
@ -30,7 +28,7 @@ void save_stack_trace(struct stack_trace *trace)
|
||||
|
||||
low = (unsigned long)task_stack_page(current);
|
||||
high = low + THREAD_SIZE;
|
||||
fp = current_frame_pointer;
|
||||
fp = (unsigned long)__builtin_frame_address(0);
|
||||
|
||||
while (fp >= low && fp <= (high - sizeof(*frame))) {
|
||||
frame = (struct stackframe *)fp;
|
||||
|
||||
@ -369,7 +369,7 @@ ret_from_fork:
|
||||
R26.L = #LO(do_work_pending);
|
||||
R0 = #VM_INT_DISABLE;
|
||||
}
|
||||
if P0 jump check_work_pending
|
||||
if (P0) jump check_work_pending
|
||||
{
|
||||
R0 = R25;
|
||||
callr R24
|
||||
|
||||
@ -29,6 +29,9 @@ KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
|
||||
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
|
||||
-DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
|
||||
|
||||
# Prevents link failures: __sanitizer_cov_trace_pc() is not linked in.
|
||||
KCOV_INSTRUMENT := n
|
||||
|
||||
# decompressor objects (linked with vmlinuz)
|
||||
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o
|
||||
|
||||
|
||||
@ -26,8 +26,6 @@
|
||||
|
||||
#define __VDSO_USE_SYSCALL ULLONG_MAX
|
||||
|
||||
#ifdef CONFIG_MIPS_CLOCK_VSYSCALL
|
||||
|
||||
static __always_inline long gettimeofday_fallback(
|
||||
struct __kernel_old_timeval *_tv,
|
||||
struct timezone *_tz)
|
||||
@ -48,17 +46,6 @@ static __always_inline long gettimeofday_fallback(
|
||||
return error ? -ret : ret;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static __always_inline long gettimeofday_fallback(
|
||||
struct __kernel_old_timeval *_tv,
|
||||
struct timezone *_tz)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static __always_inline long clock_gettime_fallback(
|
||||
clockid_t _clkid,
|
||||
struct __kernel_timespec *_ts)
|
||||
|
||||
@ -50,6 +50,25 @@ static int __init_cache_level(unsigned int cpu)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fill_cpumask_siblings(int cpu, cpumask_t *cpu_map)
|
||||
{
|
||||
int cpu1;
|
||||
|
||||
for_each_possible_cpu(cpu1)
|
||||
if (cpus_are_siblings(cpu, cpu1))
|
||||
cpumask_set_cpu(cpu1, cpu_map);
|
||||
}
|
||||
|
||||
static void fill_cpumask_cluster(int cpu, cpumask_t *cpu_map)
|
||||
{
|
||||
int cpu1;
|
||||
int cluster = cpu_cluster(&cpu_data[cpu]);
|
||||
|
||||
for_each_possible_cpu(cpu1)
|
||||
if (cpu_cluster(&cpu_data[cpu1]) == cluster)
|
||||
cpumask_set_cpu(cpu1, cpu_map);
|
||||
}
|
||||
|
||||
static int __populate_cache_leaves(unsigned int cpu)
|
||||
{
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
@ -57,14 +76,20 @@ static int __populate_cache_leaves(unsigned int cpu)
|
||||
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
|
||||
|
||||
if (c->icache.waysize) {
|
||||
/* L1 caches are per core */
|
||||
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
|
||||
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
|
||||
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
|
||||
populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
|
||||
} else {
|
||||
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
|
||||
}
|
||||
|
||||
if (c->scache.waysize)
|
||||
if (c->scache.waysize) {
|
||||
/* L2 cache is per cluster */
|
||||
fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
|
||||
populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
|
||||
}
|
||||
|
||||
if (c->tcache.waysize)
|
||||
populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
|
||||
|
||||
@ -279,16 +279,15 @@ static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
|
||||
struct bridge_irq_chip_data *data = d->chip_data;
|
||||
int bit = d->parent_data->hwirq;
|
||||
int pin = d->hwirq;
|
||||
nasid_t nasid;
|
||||
int ret, cpu;
|
||||
|
||||
ret = irq_chip_set_affinity_parent(d, mask, force);
|
||||
if (ret >= 0) {
|
||||
cpu = cpumask_first_and(mask, cpu_online_mask);
|
||||
nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
|
||||
data->nnasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
|
||||
bridge_write(data->bc, b_int_addr[pin].addr,
|
||||
(((data->bc->intr_addr >> 30) & 0x30000) |
|
||||
bit | (nasid << 8)));
|
||||
bit | (data->nasid << 8)));
|
||||
bridge_read(data->bc, b_wid_tflush);
|
||||
}
|
||||
return ret;
|
||||
|
||||
@ -73,6 +73,9 @@ static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask)
|
||||
int cpu;
|
||||
|
||||
cpu = cpumask_first_and(mask, cpu_online_mask);
|
||||
if (cpu >= nr_cpu_ids)
|
||||
cpu = cpumask_any(cpu_online_mask);
|
||||
|
||||
nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
|
||||
hd->cpu = cpu;
|
||||
if (!cputoslice(cpu)) {
|
||||
@ -139,6 +142,7 @@ static int hub_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
/* use CPU connected to nearest hub */
|
||||
hub = hub_data(NASID_TO_COMPACT_NODEID(info->nasid));
|
||||
setup_hub_mask(hd, &hub->h_cpus);
|
||||
info->nasid = cpu_to_node(hd->cpu);
|
||||
|
||||
/* Make sure it's not already pending when we connect it. */
|
||||
REMOTE_HUB_CLR_INTR(info->nasid, swlevel);
|
||||
|
||||
@ -17,12 +17,22 @@ int __vdso_clock_gettime(clockid_t clock,
|
||||
return __cvdso_clock_gettime32(clock, ts);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MIPS_CLOCK_VSYSCALL
|
||||
|
||||
/*
|
||||
* This is behind the ifdef so that we don't provide the symbol when there's no
|
||||
* possibility of there being a usable clocksource, because there's nothing we
|
||||
* can do without it. When libc fails the symbol lookup it should fall back on
|
||||
* the standard syscall path.
|
||||
*/
|
||||
int __vdso_gettimeofday(struct __kernel_old_timeval *tv,
|
||||
struct timezone *tz)
|
||||
{
|
||||
return __cvdso_gettimeofday(tv, tz);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MIPS_CLOCK_VSYSCALL */
|
||||
|
||||
int __vdso_clock_getres(clockid_t clock_id,
|
||||
struct old_timespec32 *res)
|
||||
{
|
||||
@ -43,12 +53,22 @@ int __vdso_clock_gettime(clockid_t clock,
|
||||
return __cvdso_clock_gettime(clock, ts);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MIPS_CLOCK_VSYSCALL
|
||||
|
||||
/*
|
||||
* This is behind the ifdef so that we don't provide the symbol when there's no
|
||||
* possibility of there being a usable clocksource, because there's nothing we
|
||||
* can do without it. When libc fails the symbol lookup it should fall back on
|
||||
* the standard syscall path.
|
||||
*/
|
||||
int __vdso_gettimeofday(struct __kernel_old_timeval *tv,
|
||||
struct timezone *tz)
|
||||
{
|
||||
return __cvdso_gettimeofday(tv, tz);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MIPS_CLOCK_VSYSCALL */
|
||||
|
||||
int __vdso_clock_getres(clockid_t clock_id,
|
||||
struct __kernel_timespec *res)
|
||||
{
|
||||
|
||||
@ -9,7 +9,11 @@
|
||||
#define PG_dcache_dirty PG_arch_1
|
||||
|
||||
void flush_icache_range(unsigned long start, unsigned long end);
|
||||
#define flush_icache_range flush_icache_range
|
||||
|
||||
void flush_icache_page(struct vm_area_struct *vma, struct page *page);
|
||||
#define flush_icache_page flush_icache_page
|
||||
|
||||
#ifdef CONFIG_CPU_CACHE_ALIASING
|
||||
void flush_cache_mm(struct mm_struct *mm);
|
||||
void flush_cache_dup_mm(struct mm_struct *mm);
|
||||
@ -40,12 +44,11 @@ void invalidate_kernel_vmap_range(void *addr, int size);
|
||||
#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&(mapping)->i_pages)
|
||||
|
||||
#else
|
||||
#include <asm-generic/cacheflush.h>
|
||||
#undef flush_icache_range
|
||||
#undef flush_icache_page
|
||||
#undef flush_icache_user_range
|
||||
void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long addr, int len);
|
||||
#define flush_icache_user_range flush_icache_user_range
|
||||
|
||||
#include <asm-generic/cacheflush.h>
|
||||
#endif
|
||||
|
||||
#endif /* __NDS32_CACHEFLUSH_H__ */
|
||||
|
||||
@ -945,6 +945,23 @@ void __init pnv_pci_init(void)
|
||||
if (!firmware_has_feature(FW_FEATURE_OPAL))
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_PCIEPORTBUS
|
||||
/*
|
||||
* On PowerNV PCIe devices are (currently) managed in cooperation
|
||||
* with firmware. This isn't *strictly* required, but there's enough
|
||||
* assumptions baked into both firmware and the platform code that
|
||||
* it's unwise to allow the portbus services to be used.
|
||||
*
|
||||
* We need to fix this eventually, but for now set this flag to disable
|
||||
* the portbus driver. The AER service isn't required since that AER
|
||||
* events are handled via EEH. The pciehp hotplug driver can't work
|
||||
* without kernel changes (and portbus binding breaks pnv_php). The
|
||||
* other services also require some thinking about how we're going
|
||||
* to integrate them.
|
||||
*/
|
||||
pcie_ports_disabled = true;
|
||||
#endif
|
||||
|
||||
/* Look for IODA IO-Hubs. */
|
||||
for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
|
||||
pnv_pci_init_ioda_hub(np);
|
||||
|
||||
@ -14,6 +14,7 @@ void flush_icache_all(void)
|
||||
{
|
||||
sbi_remote_fence_i(NULL);
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_all);
|
||||
|
||||
/*
|
||||
* Performs an icache flush for the given MM context. RISC-V has no direct
|
||||
|
||||
@ -10,13 +10,11 @@
|
||||
#ifdef CONFIG_IA32_EMULATION
|
||||
/* On X86_64, we use struct pt_regs * to pass parameters to syscalls */
|
||||
#define __SYSCALL_I386(nr, sym, qual) extern asmlinkage long sym(const struct pt_regs *);
|
||||
|
||||
/* this is a lie, but it does not hurt as sys_ni_syscall just returns -EINVAL */
|
||||
extern asmlinkage long sys_ni_syscall(const struct pt_regs *);
|
||||
|
||||
#define __sys_ni_syscall __ia32_sys_ni_syscall
|
||||
#else /* CONFIG_IA32_EMULATION */
|
||||
#define __SYSCALL_I386(nr, sym, qual) extern asmlinkage long sym(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
|
||||
extern asmlinkage long sys_ni_syscall(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
|
||||
#define __sys_ni_syscall sys_ni_syscall
|
||||
#endif /* CONFIG_IA32_EMULATION */
|
||||
|
||||
#include <asm/syscalls_32.h>
|
||||
@ -29,6 +27,6 @@ __visible const sys_call_ptr_t ia32_sys_call_table[__NR_syscall_compat_max+1] =
|
||||
* Smells like a compiler bug -- it doesn't work
|
||||
* when the & below is removed.
|
||||
*/
|
||||
[0 ... __NR_syscall_compat_max] = &sys_ni_syscall,
|
||||
[0 ... __NR_syscall_compat_max] = &__sys_ni_syscall,
|
||||
#include <asm/syscalls_32.h>
|
||||
};
|
||||
|
||||
@ -4,11 +4,17 @@
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/sys.h>
|
||||
#include <linux/cache.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/syscall.h>
|
||||
|
||||
/* this is a lie, but it does not hurt as sys_ni_syscall just returns -EINVAL */
|
||||
extern asmlinkage long sys_ni_syscall(const struct pt_regs *);
|
||||
extern asmlinkage long sys_ni_syscall(void);
|
||||
|
||||
SYSCALL_DEFINE0(ni_syscall)
|
||||
{
|
||||
return sys_ni_syscall();
|
||||
}
|
||||
|
||||
#define __SYSCALL_64(nr, sym, qual) extern asmlinkage long sym(const struct pt_regs *);
|
||||
#define __SYSCALL_X32(nr, sym, qual) __SYSCALL_64(nr, sym, qual)
|
||||
#include <asm/syscalls_64.h>
|
||||
@ -23,7 +29,7 @@ asmlinkage const sys_call_ptr_t sys_call_table[__NR_syscall_max+1] = {
|
||||
* Smells like a compiler bug -- it doesn't work
|
||||
* when the & below is removed.
|
||||
*/
|
||||
[0 ... __NR_syscall_max] = &sys_ni_syscall,
|
||||
[0 ... __NR_syscall_max] = &__x64_sys_ni_syscall,
|
||||
#include <asm/syscalls_64.h>
|
||||
};
|
||||
|
||||
@ -40,7 +46,7 @@ asmlinkage const sys_call_ptr_t x32_sys_call_table[__NR_syscall_x32_max+1] = {
|
||||
* Smells like a compiler bug -- it doesn't work
|
||||
* when the & below is removed.
|
||||
*/
|
||||
[0 ... __NR_syscall_x32_max] = &sys_ni_syscall,
|
||||
[0 ... __NR_syscall_x32_max] = &__x64_sys_ni_syscall,
|
||||
#include <asm/syscalls_64.h>
|
||||
};
|
||||
|
||||
|
||||
@ -124,13 +124,13 @@
|
||||
110 i386 iopl sys_iopl __ia32_sys_iopl
|
||||
111 i386 vhangup sys_vhangup __ia32_sys_vhangup
|
||||
112 i386 idle
|
||||
113 i386 vm86old sys_vm86old sys_ni_syscall
|
||||
113 i386 vm86old sys_vm86old __ia32_sys_ni_syscall
|
||||
114 i386 wait4 sys_wait4 __ia32_compat_sys_wait4
|
||||
115 i386 swapoff sys_swapoff __ia32_sys_swapoff
|
||||
116 i386 sysinfo sys_sysinfo __ia32_compat_sys_sysinfo
|
||||
117 i386 ipc sys_ipc __ia32_compat_sys_ipc
|
||||
118 i386 fsync sys_fsync __ia32_sys_fsync
|
||||
119 i386 sigreturn sys_sigreturn sys32_sigreturn
|
||||
119 i386 sigreturn sys_sigreturn __ia32_compat_sys_sigreturn
|
||||
120 i386 clone sys_clone __ia32_compat_sys_x86_clone
|
||||
121 i386 setdomainname sys_setdomainname __ia32_sys_setdomainname
|
||||
122 i386 uname sys_newuname __ia32_sys_newuname
|
||||
@ -177,14 +177,14 @@
|
||||
163 i386 mremap sys_mremap __ia32_sys_mremap
|
||||
164 i386 setresuid sys_setresuid16 __ia32_sys_setresuid16
|
||||
165 i386 getresuid sys_getresuid16 __ia32_sys_getresuid16
|
||||
166 i386 vm86 sys_vm86 sys_ni_syscall
|
||||
166 i386 vm86 sys_vm86 __ia32_sys_ni_syscall
|
||||
167 i386 query_module
|
||||
168 i386 poll sys_poll __ia32_sys_poll
|
||||
169 i386 nfsservctl
|
||||
170 i386 setresgid sys_setresgid16 __ia32_sys_setresgid16
|
||||
171 i386 getresgid sys_getresgid16 __ia32_sys_getresgid16
|
||||
172 i386 prctl sys_prctl __ia32_sys_prctl
|
||||
173 i386 rt_sigreturn sys_rt_sigreturn sys32_rt_sigreturn
|
||||
173 i386 rt_sigreturn sys_rt_sigreturn __ia32_compat_sys_rt_sigreturn
|
||||
174 i386 rt_sigaction sys_rt_sigaction __ia32_compat_sys_rt_sigaction
|
||||
175 i386 rt_sigprocmask sys_rt_sigprocmask __ia32_compat_sys_rt_sigprocmask
|
||||
176 i386 rt_sigpending sys_rt_sigpending __ia32_compat_sys_rt_sigpending
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
#include <linux/personality.h>
|
||||
#include <linux/compat.h>
|
||||
#include <linux/binfmts.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <asm/ucontext.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/fpu/internal.h>
|
||||
@ -118,7 +119,7 @@ static int ia32_restore_sigcontext(struct pt_regs *regs,
|
||||
return err;
|
||||
}
|
||||
|
||||
asmlinkage long sys32_sigreturn(void)
|
||||
COMPAT_SYSCALL_DEFINE0(sigreturn)
|
||||
{
|
||||
struct pt_regs *regs = current_pt_regs();
|
||||
struct sigframe_ia32 __user *frame = (struct sigframe_ia32 __user *)(regs->sp-8);
|
||||
@ -144,7 +145,7 @@ badframe:
|
||||
return 0;
|
||||
}
|
||||
|
||||
asmlinkage long sys32_rt_sigreturn(void)
|
||||
COMPAT_SYSCALL_DEFINE0(rt_sigreturn)
|
||||
{
|
||||
struct pt_regs *regs = current_pt_regs();
|
||||
struct rt_sigframe_ia32 __user *frame;
|
||||
|
||||
@ -6,6 +6,8 @@
|
||||
#ifndef _ASM_X86_SYSCALL_WRAPPER_H
|
||||
#define _ASM_X86_SYSCALL_WRAPPER_H
|
||||
|
||||
struct pt_regs;
|
||||
|
||||
/* Mapping of registers to parameters for syscalls on x86-64 and x32 */
|
||||
#define SC_X86_64_REGS_TO_ARGS(x, ...) \
|
||||
__MAP(x,__SC_ARGS \
|
||||
@ -28,13 +30,21 @@
|
||||
* kernel/sys_ni.c and SYS_NI in kernel/time/posix-stubs.c to cover this
|
||||
* case as well.
|
||||
*/
|
||||
#define __IA32_COMPAT_SYS_STUB0(x, name) \
|
||||
asmlinkage long __ia32_compat_sys_##name(const struct pt_regs *regs);\
|
||||
ALLOW_ERROR_INJECTION(__ia32_compat_sys_##name, ERRNO); \
|
||||
asmlinkage long __ia32_compat_sys_##name(const struct pt_regs *regs)\
|
||||
{ \
|
||||
return __se_compat_sys_##name(); \
|
||||
}
|
||||
|
||||
#define __IA32_COMPAT_SYS_STUBx(x, name, ...) \
|
||||
asmlinkage long __ia32_compat_sys##name(const struct pt_regs *regs);\
|
||||
ALLOW_ERROR_INJECTION(__ia32_compat_sys##name, ERRNO); \
|
||||
asmlinkage long __ia32_compat_sys##name(const struct pt_regs *regs)\
|
||||
{ \
|
||||
return __se_compat_sys##name(SC_IA32_REGS_TO_ARGS(x,__VA_ARGS__));\
|
||||
} \
|
||||
}
|
||||
|
||||
#define __IA32_SYS_STUBx(x, name, ...) \
|
||||
asmlinkage long __ia32_sys##name(const struct pt_regs *regs); \
|
||||
@ -57,8 +67,14 @@
|
||||
asmlinkage long __x64_sys_##sname(const struct pt_regs *__unused)
|
||||
|
||||
#define COND_SYSCALL(name) \
|
||||
cond_syscall(__x64_sys_##name); \
|
||||
cond_syscall(__ia32_sys_##name)
|
||||
asmlinkage __weak long __x64_sys_##name(const struct pt_regs *__unused) \
|
||||
{ \
|
||||
return sys_ni_syscall(); \
|
||||
} \
|
||||
asmlinkage __weak long __ia32_sys_##name(const struct pt_regs *__unused)\
|
||||
{ \
|
||||
return sys_ni_syscall(); \
|
||||
}
|
||||
|
||||
#define SYS_NI(name) \
|
||||
SYSCALL_ALIAS(__x64_sys_##name, sys_ni_posix_timers); \
|
||||
@ -76,15 +92,24 @@
|
||||
* of the x86-64-style parameter ordering of x32 syscalls. The syscalls common
|
||||
* with x86_64 obviously do not need such care.
|
||||
*/
|
||||
#define __X32_COMPAT_SYS_STUB0(x, name, ...) \
|
||||
asmlinkage long __x32_compat_sys_##name(const struct pt_regs *regs);\
|
||||
ALLOW_ERROR_INJECTION(__x32_compat_sys_##name, ERRNO); \
|
||||
asmlinkage long __x32_compat_sys_##name(const struct pt_regs *regs)\
|
||||
{ \
|
||||
return __se_compat_sys_##name();\
|
||||
}
|
||||
|
||||
#define __X32_COMPAT_SYS_STUBx(x, name, ...) \
|
||||
asmlinkage long __x32_compat_sys##name(const struct pt_regs *regs);\
|
||||
ALLOW_ERROR_INJECTION(__x32_compat_sys##name, ERRNO); \
|
||||
asmlinkage long __x32_compat_sys##name(const struct pt_regs *regs)\
|
||||
{ \
|
||||
return __se_compat_sys##name(SC_X86_64_REGS_TO_ARGS(x,__VA_ARGS__));\
|
||||
} \
|
||||
}
|
||||
|
||||
#else /* CONFIG_X86_X32 */
|
||||
#define __X32_COMPAT_SYS_STUB0(x, name)
|
||||
#define __X32_COMPAT_SYS_STUBx(x, name, ...)
|
||||
#endif /* CONFIG_X86_X32 */
|
||||
|
||||
@ -95,6 +120,17 @@
|
||||
* mapping of registers to parameters, we need to generate stubs for each
|
||||
* of them.
|
||||
*/
|
||||
#define COMPAT_SYSCALL_DEFINE0(name) \
|
||||
static long __se_compat_sys_##name(void); \
|
||||
static inline long __do_compat_sys_##name(void); \
|
||||
__IA32_COMPAT_SYS_STUB0(x, name) \
|
||||
__X32_COMPAT_SYS_STUB0(x, name) \
|
||||
static long __se_compat_sys_##name(void) \
|
||||
{ \
|
||||
return __do_compat_sys_##name(); \
|
||||
} \
|
||||
static inline long __do_compat_sys_##name(void)
|
||||
|
||||
#define COMPAT_SYSCALL_DEFINEx(x, name, ...) \
|
||||
static long __se_compat_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)); \
|
||||
static inline long __do_compat_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__));\
|
||||
@ -190,7 +226,11 @@
|
||||
#endif
|
||||
|
||||
#ifndef COND_SYSCALL
|
||||
#define COND_SYSCALL(name) cond_syscall(__x64_sys_##name)
|
||||
#define COND_SYSCALL(name) \
|
||||
asmlinkage __weak long __x64_sys_##name(const struct pt_regs *__unused) \
|
||||
{ \
|
||||
return sys_ni_syscall(); \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef SYS_NI
|
||||
@ -202,7 +242,6 @@
|
||||
* For VSYSCALLS, we need to declare these three syscalls with the new
|
||||
* pt_regs-based calling convention for in-kernel use.
|
||||
*/
|
||||
struct pt_regs;
|
||||
asmlinkage long __x64_sys_getcpu(const struct pt_regs *regs);
|
||||
asmlinkage long __x64_sys_gettimeofday(const struct pt_regs *regs);
|
||||
asmlinkage long __x64_sys_time(const struct pt_regs *regs);
|
||||
|
||||
12
block/bio.c
12
block/bio.c
@ -538,6 +538,16 @@ void zero_fill_bio_iter(struct bio *bio, struct bvec_iter start)
|
||||
}
|
||||
EXPORT_SYMBOL(zero_fill_bio_iter);
|
||||
|
||||
/**
|
||||
* bio_truncate - truncate the bio to small size of @new_size
|
||||
* @bio: the bio to be truncated
|
||||
* @new_size: new size for truncating the bio
|
||||
*
|
||||
* Description:
|
||||
* Truncate the bio to new size of @new_size. If bio_op(bio) is
|
||||
* REQ_OP_READ, zero the truncated part. This function should only
|
||||
* be used for handling corner cases, such as bio eod.
|
||||
*/
|
||||
void bio_truncate(struct bio *bio, unsigned new_size)
|
||||
{
|
||||
struct bio_vec bv;
|
||||
@ -548,7 +558,7 @@ void bio_truncate(struct bio *bio, unsigned new_size)
|
||||
if (new_size >= bio->bi_iter.bi_size)
|
||||
return;
|
||||
|
||||
if (bio_data_dir(bio) != READ)
|
||||
if (bio_op(bio) != REQ_OP_READ)
|
||||
goto exit;
|
||||
|
||||
bio_for_each_segment(bv, bio, iter) {
|
||||
|
||||
@ -56,7 +56,7 @@ static int _skcipher_recvmsg(struct socket *sock, struct msghdr *msg,
|
||||
struct alg_sock *pask = alg_sk(psk);
|
||||
struct af_alg_ctx *ctx = ask->private;
|
||||
struct crypto_skcipher *tfm = pask->private;
|
||||
unsigned int bs = crypto_skcipher_blocksize(tfm);
|
||||
unsigned int bs = crypto_skcipher_chunksize(tfm);
|
||||
struct af_alg_async_req *areq;
|
||||
int err = 0;
|
||||
size_t len = 0;
|
||||
|
||||
@ -3968,6 +3968,7 @@ void clk_unregister(struct clk *clk)
|
||||
__func__, clk->core->name);
|
||||
|
||||
kref_put(&clk->core->ref, __clk_release);
|
||||
free_clk(clk);
|
||||
unlock:
|
||||
clk_prepare_unlock();
|
||||
}
|
||||
|
||||
@ -112,43 +112,17 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
|
||||
return fvco;
|
||||
}
|
||||
|
||||
static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
|
||||
static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
|
||||
u32 pll_div)
|
||||
{
|
||||
u32 old_mdiv, old_pdiv;
|
||||
|
||||
old_mdiv = (pll_div >> MDIV_SHIFT) & MDIV_MASK;
|
||||
old_pdiv = (pll_div >> PDIV_SHIFT) & PDIV_MASK;
|
||||
old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
|
||||
old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
|
||||
|
||||
return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
|
||||
}
|
||||
|
||||
static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
|
||||
u32 pll_div_ctl0, u32 pll_div_ctl1)
|
||||
{
|
||||
u32 old_mdiv, old_pdiv, old_kdiv;
|
||||
|
||||
old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
|
||||
old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
|
||||
old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
|
||||
|
||||
return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
|
||||
rate->kdiv != old_kdiv;
|
||||
}
|
||||
|
||||
static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
|
||||
u32 pll_div_ctl0, u32 pll_div_ctl1)
|
||||
{
|
||||
u32 old_mdiv, old_pdiv, old_kdiv;
|
||||
|
||||
old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
|
||||
old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
|
||||
old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
|
||||
|
||||
return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
|
||||
rate->kdiv != old_kdiv;
|
||||
}
|
||||
|
||||
static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
|
||||
{
|
||||
u32 val;
|
||||
@ -174,7 +148,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
tmp = readl_relaxed(pll->base + 4);
|
||||
|
||||
if (!clk_pll1416x_mp_change(rate, tmp)) {
|
||||
if (!clk_pll14xx_mp_change(rate, tmp)) {
|
||||
tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
|
||||
tmp |= rate->sdiv << SDIV_SHIFT;
|
||||
writel_relaxed(tmp, pll->base + 4);
|
||||
@ -239,13 +213,15 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
}
|
||||
|
||||
tmp = readl_relaxed(pll->base + 4);
|
||||
div_val = readl_relaxed(pll->base + 8);
|
||||
|
||||
if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
|
||||
if (!clk_pll14xx_mp_change(rate, tmp)) {
|
||||
tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
|
||||
tmp |= rate->sdiv << SDIV_SHIFT;
|
||||
writel_relaxed(tmp, pll->base + 4);
|
||||
|
||||
tmp = rate->kdiv << KDIV_SHIFT;
|
||||
writel_relaxed(tmp, pll->base + 8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -1001,7 +1001,7 @@ static const struct regmap_config axg_audio_regmap_cfg = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = AUDIO_CLK_PDMIN_CTRL1,
|
||||
.max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
|
||||
};
|
||||
|
||||
struct audioclk_data {
|
||||
|
||||
@ -165,6 +165,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
|
||||
GATE_BUS_CPU,
|
||||
GATE_SCLK_CPU,
|
||||
CLKOUT_CMU_CPU,
|
||||
APLL_CON0,
|
||||
KPLL_CON0,
|
||||
CPLL_CON0,
|
||||
DPLL_CON0,
|
||||
EPLL_CON0,
|
||||
|
||||
@ -103,8 +103,7 @@ static void write_to_ucd_unit(struct nitrox_device *ndev, u32 ucode_size,
|
||||
offset = UCD_UCODE_LOAD_BLOCK_NUM;
|
||||
nitrox_write_csr(ndev, offset, block_num);
|
||||
|
||||
code_size = ucode_size;
|
||||
code_size = roundup(code_size, 8);
|
||||
code_size = roundup(ucode_size, 16);
|
||||
while (code_size) {
|
||||
data = ucode_data[i];
|
||||
/* write 8 bytes at a time */
|
||||
@ -220,11 +219,11 @@ static int nitrox_load_fw(struct nitrox_device *ndev)
|
||||
|
||||
/* write block number and firmware length
|
||||
* bit:<2:0> block number
|
||||
* bit:3 is set SE uses 32KB microcode
|
||||
* bit:3 is clear SE uses 64KB microcode
|
||||
* bit:3 is set AE uses 32KB microcode
|
||||
* bit:3 is clear AE uses 64KB microcode
|
||||
*/
|
||||
core_2_eid_val.value = 0ULL;
|
||||
core_2_eid_val.ucode_blk = 0;
|
||||
core_2_eid_val.ucode_blk = 2;
|
||||
if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
|
||||
core_2_eid_val.ucode_len = 1;
|
||||
else
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
#include <linux/spinlock.h>
|
||||
#include <crypto/algapi.h>
|
||||
#include <crypto/aes.h>
|
||||
#include <crypto/skcipher.h>
|
||||
#include <crypto/internal/skcipher.h>
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
@ -24,12 +24,12 @@ static spinlock_t lock;
|
||||
|
||||
/* Write a 128 bit field (either a writable key or IV) */
|
||||
static inline void
|
||||
_writefield(u32 offset, void *value)
|
||||
_writefield(u32 offset, const void *value)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
iowrite32(((u32 *) value)[i], _iobase + offset + (i * 4));
|
||||
iowrite32(((const u32 *) value)[i], _iobase + offset + (i * 4));
|
||||
}
|
||||
|
||||
/* Read a 128 bit field (either a writable key or IV) */
|
||||
@ -43,12 +43,12 @@ _readfield(u32 offset, void *value)
|
||||
}
|
||||
|
||||
static int
|
||||
do_crypt(void *src, void *dst, int len, u32 flags)
|
||||
do_crypt(const void *src, void *dst, u32 len, u32 flags)
|
||||
{
|
||||
u32 status;
|
||||
u32 counter = AES_OP_TIMEOUT;
|
||||
|
||||
iowrite32(virt_to_phys(src), _iobase + AES_SOURCEA_REG);
|
||||
iowrite32(virt_to_phys((void *)src), _iobase + AES_SOURCEA_REG);
|
||||
iowrite32(virt_to_phys(dst), _iobase + AES_DSTA_REG);
|
||||
iowrite32(len, _iobase + AES_LENA_REG);
|
||||
|
||||
@ -65,16 +65,14 @@ do_crypt(void *src, void *dst, int len, u32 flags)
|
||||
return counter ? 0 : 1;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
geode_aes_crypt(struct geode_aes_op *op)
|
||||
static void
|
||||
geode_aes_crypt(const struct geode_aes_tfm_ctx *tctx, const void *src,
|
||||
void *dst, u32 len, u8 *iv, int mode, int dir)
|
||||
{
|
||||
u32 flags = 0;
|
||||
unsigned long iflags;
|
||||
int ret;
|
||||
|
||||
if (op->len == 0)
|
||||
return 0;
|
||||
|
||||
/* If the source and destination is the same, then
|
||||
* we need to turn on the coherent flags, otherwise
|
||||
* we don't need to worry
|
||||
@ -82,32 +80,28 @@ geode_aes_crypt(struct geode_aes_op *op)
|
||||
|
||||
flags |= (AES_CTRL_DCA | AES_CTRL_SCA);
|
||||
|
||||
if (op->dir == AES_DIR_ENCRYPT)
|
||||
if (dir == AES_DIR_ENCRYPT)
|
||||
flags |= AES_CTRL_ENCRYPT;
|
||||
|
||||
/* Start the critical section */
|
||||
|
||||
spin_lock_irqsave(&lock, iflags);
|
||||
|
||||
if (op->mode == AES_MODE_CBC) {
|
||||
if (mode == AES_MODE_CBC) {
|
||||
flags |= AES_CTRL_CBC;
|
||||
_writefield(AES_WRITEIV0_REG, op->iv);
|
||||
_writefield(AES_WRITEIV0_REG, iv);
|
||||
}
|
||||
|
||||
if (!(op->flags & AES_FLAGS_HIDDENKEY)) {
|
||||
flags |= AES_CTRL_WRKEY;
|
||||
_writefield(AES_WRITEKEY0_REG, op->key);
|
||||
}
|
||||
_writefield(AES_WRITEKEY0_REG, tctx->key);
|
||||
|
||||
ret = do_crypt(op->src, op->dst, op->len, flags);
|
||||
ret = do_crypt(src, dst, len, flags);
|
||||
BUG_ON(ret);
|
||||
|
||||
if (op->mode == AES_MODE_CBC)
|
||||
_readfield(AES_WRITEIV0_REG, op->iv);
|
||||
if (mode == AES_MODE_CBC)
|
||||
_readfield(AES_WRITEIV0_REG, iv);
|
||||
|
||||
spin_unlock_irqrestore(&lock, iflags);
|
||||
|
||||
return op->len;
|
||||
}
|
||||
|
||||
/* CRYPTO-API Functions */
|
||||
@ -115,13 +109,13 @@ geode_aes_crypt(struct geode_aes_op *op)
|
||||
static int geode_setkey_cip(struct crypto_tfm *tfm, const u8 *key,
|
||||
unsigned int len)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
|
||||
unsigned int ret;
|
||||
|
||||
op->keylen = len;
|
||||
tctx->keylen = len;
|
||||
|
||||
if (len == AES_KEYSIZE_128) {
|
||||
memcpy(op->key, key, len);
|
||||
memcpy(tctx->key, key, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -134,132 +128,93 @@ static int geode_setkey_cip(struct crypto_tfm *tfm, const u8 *key,
|
||||
/*
|
||||
* The requested key size is not supported by HW, do a fallback
|
||||
*/
|
||||
op->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
|
||||
op->fallback.cip->base.crt_flags |= (tfm->crt_flags & CRYPTO_TFM_REQ_MASK);
|
||||
tctx->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
|
||||
tctx->fallback.cip->base.crt_flags |=
|
||||
(tfm->crt_flags & CRYPTO_TFM_REQ_MASK);
|
||||
|
||||
ret = crypto_cipher_setkey(op->fallback.cip, key, len);
|
||||
ret = crypto_cipher_setkey(tctx->fallback.cip, key, len);
|
||||
if (ret) {
|
||||
tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
|
||||
tfm->crt_flags |= (op->fallback.cip->base.crt_flags & CRYPTO_TFM_RES_MASK);
|
||||
tfm->crt_flags |= (tctx->fallback.cip->base.crt_flags &
|
||||
CRYPTO_TFM_RES_MASK);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int geode_setkey_blk(struct crypto_tfm *tfm, const u8 *key,
|
||||
static int geode_setkey_skcipher(struct crypto_skcipher *tfm, const u8 *key,
|
||||
unsigned int len)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
|
||||
unsigned int ret;
|
||||
|
||||
op->keylen = len;
|
||||
tctx->keylen = len;
|
||||
|
||||
if (len == AES_KEYSIZE_128) {
|
||||
memcpy(op->key, key, len);
|
||||
memcpy(tctx->key, key, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) {
|
||||
/* not supported at all */
|
||||
tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
|
||||
crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* The requested key size is not supported by HW, do a fallback
|
||||
*/
|
||||
crypto_sync_skcipher_clear_flags(op->fallback.blk, CRYPTO_TFM_REQ_MASK);
|
||||
crypto_sync_skcipher_set_flags(op->fallback.blk,
|
||||
tfm->crt_flags & CRYPTO_TFM_REQ_MASK);
|
||||
|
||||
ret = crypto_sync_skcipher_setkey(op->fallback.blk, key, len);
|
||||
if (ret) {
|
||||
tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
|
||||
tfm->crt_flags |= crypto_sync_skcipher_get_flags(op->fallback.blk) &
|
||||
CRYPTO_TFM_RES_MASK;
|
||||
}
|
||||
crypto_skcipher_clear_flags(tctx->fallback.skcipher,
|
||||
CRYPTO_TFM_REQ_MASK);
|
||||
crypto_skcipher_set_flags(tctx->fallback.skcipher,
|
||||
crypto_skcipher_get_flags(tfm) &
|
||||
CRYPTO_TFM_REQ_MASK);
|
||||
ret = crypto_skcipher_setkey(tctx->fallback.skcipher, key, len);
|
||||
crypto_skcipher_set_flags(tfm,
|
||||
crypto_skcipher_get_flags(tctx->fallback.skcipher) &
|
||||
CRYPTO_TFM_RES_MASK);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fallback_blk_dec(struct blkcipher_desc *desc,
|
||||
struct scatterlist *dst, struct scatterlist *src,
|
||||
unsigned int nbytes)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
|
||||
SYNC_SKCIPHER_REQUEST_ON_STACK(req, op->fallback.blk);
|
||||
|
||||
skcipher_request_set_sync_tfm(req, op->fallback.blk);
|
||||
skcipher_request_set_callback(req, 0, NULL, NULL);
|
||||
skcipher_request_set_crypt(req, src, dst, nbytes, desc->info);
|
||||
|
||||
return crypto_skcipher_decrypt(req);
|
||||
}
|
||||
|
||||
static int fallback_blk_enc(struct blkcipher_desc *desc,
|
||||
struct scatterlist *dst, struct scatterlist *src,
|
||||
unsigned int nbytes)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
|
||||
SYNC_SKCIPHER_REQUEST_ON_STACK(req, op->fallback.blk);
|
||||
|
||||
skcipher_request_set_sync_tfm(req, op->fallback.blk);
|
||||
skcipher_request_set_callback(req, 0, NULL, NULL);
|
||||
skcipher_request_set_crypt(req, src, dst, nbytes, desc->info);
|
||||
|
||||
return crypto_skcipher_encrypt(req);
|
||||
}
|
||||
|
||||
static void
|
||||
geode_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
const struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
if (unlikely(op->keylen != AES_KEYSIZE_128)) {
|
||||
crypto_cipher_encrypt_one(op->fallback.cip, out, in);
|
||||
if (unlikely(tctx->keylen != AES_KEYSIZE_128)) {
|
||||
crypto_cipher_encrypt_one(tctx->fallback.cip, out, in);
|
||||
return;
|
||||
}
|
||||
|
||||
op->src = (void *) in;
|
||||
op->dst = (void *) out;
|
||||
op->mode = AES_MODE_ECB;
|
||||
op->flags = 0;
|
||||
op->len = AES_BLOCK_SIZE;
|
||||
op->dir = AES_DIR_ENCRYPT;
|
||||
|
||||
geode_aes_crypt(op);
|
||||
geode_aes_crypt(tctx, in, out, AES_BLOCK_SIZE, NULL,
|
||||
AES_MODE_ECB, AES_DIR_ENCRYPT);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
geode_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
const struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
if (unlikely(op->keylen != AES_KEYSIZE_128)) {
|
||||
crypto_cipher_decrypt_one(op->fallback.cip, out, in);
|
||||
if (unlikely(tctx->keylen != AES_KEYSIZE_128)) {
|
||||
crypto_cipher_decrypt_one(tctx->fallback.cip, out, in);
|
||||
return;
|
||||
}
|
||||
|
||||
op->src = (void *) in;
|
||||
op->dst = (void *) out;
|
||||
op->mode = AES_MODE_ECB;
|
||||
op->flags = 0;
|
||||
op->len = AES_BLOCK_SIZE;
|
||||
op->dir = AES_DIR_DECRYPT;
|
||||
|
||||
geode_aes_crypt(op);
|
||||
geode_aes_crypt(tctx, in, out, AES_BLOCK_SIZE, NULL,
|
||||
AES_MODE_ECB, AES_DIR_DECRYPT);
|
||||
}
|
||||
|
||||
static int fallback_init_cip(struct crypto_tfm *tfm)
|
||||
{
|
||||
const char *name = crypto_tfm_alg_name(tfm);
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
op->fallback.cip = crypto_alloc_cipher(name, 0,
|
||||
tctx->fallback.cip = crypto_alloc_cipher(name, 0,
|
||||
CRYPTO_ALG_NEED_FALLBACK);
|
||||
|
||||
if (IS_ERR(op->fallback.cip)) {
|
||||
if (IS_ERR(tctx->fallback.cip)) {
|
||||
printk(KERN_ERR "Error allocating fallback algo %s\n", name);
|
||||
return PTR_ERR(op->fallback.cip);
|
||||
return PTR_ERR(tctx->fallback.cip);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -267,10 +222,9 @@ static int fallback_init_cip(struct crypto_tfm *tfm)
|
||||
|
||||
static void fallback_exit_cip(struct crypto_tfm *tfm)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
struct geode_aes_tfm_ctx *tctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
crypto_free_cipher(op->fallback.cip);
|
||||
op->fallback.cip = NULL;
|
||||
crypto_free_cipher(tctx->fallback.cip);
|
||||
}
|
||||
|
||||
static struct crypto_alg geode_alg = {
|
||||
@ -283,7 +237,7 @@ static struct crypto_alg geode_alg = {
|
||||
.cra_init = fallback_init_cip,
|
||||
.cra_exit = fallback_exit_cip,
|
||||
.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct geode_aes_op),
|
||||
.cra_ctxsize = sizeof(struct geode_aes_tfm_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_u = {
|
||||
.cipher = {
|
||||
@ -296,220 +250,126 @@ static struct crypto_alg geode_alg = {
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
geode_cbc_decrypt(struct blkcipher_desc *desc,
|
||||
struct scatterlist *dst, struct scatterlist *src,
|
||||
unsigned int nbytes)
|
||||
static int geode_init_skcipher(struct crypto_skcipher *tfm)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
|
||||
struct blkcipher_walk walk;
|
||||
int err, ret;
|
||||
const char *name = crypto_tfm_alg_name(&tfm->base);
|
||||
struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
|
||||
|
||||
if (nbytes % AES_BLOCK_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
if (unlikely(op->keylen != AES_KEYSIZE_128))
|
||||
return fallback_blk_dec(desc, dst, src, nbytes);
|
||||
|
||||
blkcipher_walk_init(&walk, dst, src, nbytes);
|
||||
err = blkcipher_walk_virt(desc, &walk);
|
||||
op->iv = walk.iv;
|
||||
|
||||
while ((nbytes = walk.nbytes)) {
|
||||
op->src = walk.src.virt.addr,
|
||||
op->dst = walk.dst.virt.addr;
|
||||
op->mode = AES_MODE_CBC;
|
||||
op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
|
||||
op->dir = AES_DIR_DECRYPT;
|
||||
|
||||
ret = geode_aes_crypt(op);
|
||||
|
||||
nbytes -= ret;
|
||||
err = blkcipher_walk_done(desc, &walk, nbytes);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
geode_cbc_encrypt(struct blkcipher_desc *desc,
|
||||
struct scatterlist *dst, struct scatterlist *src,
|
||||
unsigned int nbytes)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
|
||||
struct blkcipher_walk walk;
|
||||
int err, ret;
|
||||
|
||||
if (nbytes % AES_BLOCK_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
if (unlikely(op->keylen != AES_KEYSIZE_128))
|
||||
return fallback_blk_enc(desc, dst, src, nbytes);
|
||||
|
||||
blkcipher_walk_init(&walk, dst, src, nbytes);
|
||||
err = blkcipher_walk_virt(desc, &walk);
|
||||
op->iv = walk.iv;
|
||||
|
||||
while ((nbytes = walk.nbytes)) {
|
||||
op->src = walk.src.virt.addr,
|
||||
op->dst = walk.dst.virt.addr;
|
||||
op->mode = AES_MODE_CBC;
|
||||
op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
|
||||
op->dir = AES_DIR_ENCRYPT;
|
||||
|
||||
ret = geode_aes_crypt(op);
|
||||
nbytes -= ret;
|
||||
err = blkcipher_walk_done(desc, &walk, nbytes);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int fallback_init_blk(struct crypto_tfm *tfm)
|
||||
{
|
||||
const char *name = crypto_tfm_alg_name(tfm);
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
|
||||
op->fallback.blk = crypto_alloc_sync_skcipher(name, 0,
|
||||
CRYPTO_ALG_NEED_FALLBACK);
|
||||
if (IS_ERR(op->fallback.blk)) {
|
||||
tctx->fallback.skcipher =
|
||||
crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK |
|
||||
CRYPTO_ALG_ASYNC);
|
||||
if (IS_ERR(tctx->fallback.skcipher)) {
|
||||
printk(KERN_ERR "Error allocating fallback algo %s\n", name);
|
||||
return PTR_ERR(op->fallback.blk);
|
||||
return PTR_ERR(tctx->fallback.skcipher);
|
||||
}
|
||||
|
||||
crypto_skcipher_set_reqsize(tfm, sizeof(struct skcipher_request) +
|
||||
crypto_skcipher_reqsize(tctx->fallback.skcipher));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fallback_exit_blk(struct crypto_tfm *tfm)
|
||||
static void geode_exit_skcipher(struct crypto_skcipher *tfm)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_tfm_ctx(tfm);
|
||||
struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
|
||||
|
||||
crypto_free_sync_skcipher(op->fallback.blk);
|
||||
op->fallback.blk = NULL;
|
||||
crypto_free_skcipher(tctx->fallback.skcipher);
|
||||
}
|
||||
|
||||
static struct crypto_alg geode_cbc_alg = {
|
||||
.cra_name = "cbc(aes)",
|
||||
.cra_driver_name = "cbc-aes-geode",
|
||||
.cra_priority = 400,
|
||||
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
|
||||
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
||||
static int geode_skcipher_crypt(struct skcipher_request *req, int mode, int dir)
|
||||
{
|
||||
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
|
||||
const struct geode_aes_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
|
||||
struct skcipher_walk walk;
|
||||
unsigned int nbytes;
|
||||
int err;
|
||||
|
||||
if (unlikely(tctx->keylen != AES_KEYSIZE_128)) {
|
||||
struct skcipher_request *subreq = skcipher_request_ctx(req);
|
||||
|
||||
*subreq = *req;
|
||||
skcipher_request_set_tfm(subreq, tctx->fallback.skcipher);
|
||||
if (dir == AES_DIR_DECRYPT)
|
||||
return crypto_skcipher_decrypt(subreq);
|
||||
else
|
||||
return crypto_skcipher_encrypt(subreq);
|
||||
}
|
||||
|
||||
err = skcipher_walk_virt(&walk, req, false);
|
||||
|
||||
while ((nbytes = walk.nbytes) != 0) {
|
||||
geode_aes_crypt(tctx, walk.src.virt.addr, walk.dst.virt.addr,
|
||||
round_down(nbytes, AES_BLOCK_SIZE),
|
||||
walk.iv, mode, dir);
|
||||
err = skcipher_walk_done(&walk, nbytes % AES_BLOCK_SIZE);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int geode_cbc_encrypt(struct skcipher_request *req)
|
||||
{
|
||||
return geode_skcipher_crypt(req, AES_MODE_CBC, AES_DIR_ENCRYPT);
|
||||
}
|
||||
|
||||
static int geode_cbc_decrypt(struct skcipher_request *req)
|
||||
{
|
||||
return geode_skcipher_crypt(req, AES_MODE_CBC, AES_DIR_DECRYPT);
|
||||
}
|
||||
|
||||
static int geode_ecb_encrypt(struct skcipher_request *req)
|
||||
{
|
||||
return geode_skcipher_crypt(req, AES_MODE_ECB, AES_DIR_ENCRYPT);
|
||||
}
|
||||
|
||||
static int geode_ecb_decrypt(struct skcipher_request *req)
|
||||
{
|
||||
return geode_skcipher_crypt(req, AES_MODE_ECB, AES_DIR_DECRYPT);
|
||||
}
|
||||
|
||||
static struct skcipher_alg geode_skcipher_algs[] = {
|
||||
{
|
||||
.base.cra_name = "cbc(aes)",
|
||||
.base.cra_driver_name = "cbc-aes-geode",
|
||||
.base.cra_priority = 400,
|
||||
.base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
|
||||
CRYPTO_ALG_NEED_FALLBACK,
|
||||
.cra_init = fallback_init_blk,
|
||||
.cra_exit = fallback_exit_blk,
|
||||
.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct geode_aes_op),
|
||||
.cra_alignmask = 15,
|
||||
.cra_type = &crypto_blkcipher_type,
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_u = {
|
||||
.blkcipher = {
|
||||
.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.max_keysize = AES_MAX_KEY_SIZE,
|
||||
.setkey = geode_setkey_blk,
|
||||
.base.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.base.cra_ctxsize = sizeof(struct geode_aes_tfm_ctx),
|
||||
.base.cra_alignmask = 15,
|
||||
.base.cra_module = THIS_MODULE,
|
||||
.init = geode_init_skcipher,
|
||||
.exit = geode_exit_skcipher,
|
||||
.setkey = geode_setkey_skcipher,
|
||||
.encrypt = geode_cbc_encrypt,
|
||||
.decrypt = geode_cbc_decrypt,
|
||||
.ivsize = AES_BLOCK_SIZE,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
geode_ecb_decrypt(struct blkcipher_desc *desc,
|
||||
struct scatterlist *dst, struct scatterlist *src,
|
||||
unsigned int nbytes)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
|
||||
struct blkcipher_walk walk;
|
||||
int err, ret;
|
||||
|
||||
if (nbytes % AES_BLOCK_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
if (unlikely(op->keylen != AES_KEYSIZE_128))
|
||||
return fallback_blk_dec(desc, dst, src, nbytes);
|
||||
|
||||
blkcipher_walk_init(&walk, dst, src, nbytes);
|
||||
err = blkcipher_walk_virt(desc, &walk);
|
||||
|
||||
while ((nbytes = walk.nbytes)) {
|
||||
op->src = walk.src.virt.addr,
|
||||
op->dst = walk.dst.virt.addr;
|
||||
op->mode = AES_MODE_ECB;
|
||||
op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
|
||||
op->dir = AES_DIR_DECRYPT;
|
||||
|
||||
ret = geode_aes_crypt(op);
|
||||
nbytes -= ret;
|
||||
err = blkcipher_walk_done(desc, &walk, nbytes);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
geode_ecb_encrypt(struct blkcipher_desc *desc,
|
||||
struct scatterlist *dst, struct scatterlist *src,
|
||||
unsigned int nbytes)
|
||||
{
|
||||
struct geode_aes_op *op = crypto_blkcipher_ctx(desc->tfm);
|
||||
struct blkcipher_walk walk;
|
||||
int err, ret;
|
||||
|
||||
if (nbytes % AES_BLOCK_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
if (unlikely(op->keylen != AES_KEYSIZE_128))
|
||||
return fallback_blk_enc(desc, dst, src, nbytes);
|
||||
|
||||
blkcipher_walk_init(&walk, dst, src, nbytes);
|
||||
err = blkcipher_walk_virt(desc, &walk);
|
||||
|
||||
while ((nbytes = walk.nbytes)) {
|
||||
op->src = walk.src.virt.addr,
|
||||
op->dst = walk.dst.virt.addr;
|
||||
op->mode = AES_MODE_ECB;
|
||||
op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
|
||||
op->dir = AES_DIR_ENCRYPT;
|
||||
|
||||
ret = geode_aes_crypt(op);
|
||||
nbytes -= ret;
|
||||
ret = blkcipher_walk_done(desc, &walk, nbytes);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct crypto_alg geode_ecb_alg = {
|
||||
.cra_name = "ecb(aes)",
|
||||
.cra_driver_name = "ecb-aes-geode",
|
||||
.cra_priority = 400,
|
||||
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
|
||||
CRYPTO_ALG_KERN_DRIVER_ONLY |
|
||||
CRYPTO_ALG_NEED_FALLBACK,
|
||||
.cra_init = fallback_init_blk,
|
||||
.cra_exit = fallback_exit_blk,
|
||||
.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct geode_aes_op),
|
||||
.cra_alignmask = 15,
|
||||
.cra_type = &crypto_blkcipher_type,
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_u = {
|
||||
.blkcipher = {
|
||||
.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.max_keysize = AES_MAX_KEY_SIZE,
|
||||
.setkey = geode_setkey_blk,
|
||||
.ivsize = AES_BLOCK_SIZE,
|
||||
}, {
|
||||
.base.cra_name = "ecb(aes)",
|
||||
.base.cra_driver_name = "ecb-aes-geode",
|
||||
.base.cra_priority = 400,
|
||||
.base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
|
||||
CRYPTO_ALG_NEED_FALLBACK,
|
||||
.base.cra_blocksize = AES_BLOCK_SIZE,
|
||||
.base.cra_ctxsize = sizeof(struct geode_aes_tfm_ctx),
|
||||
.base.cra_alignmask = 15,
|
||||
.base.cra_module = THIS_MODULE,
|
||||
.init = geode_init_skcipher,
|
||||
.exit = geode_exit_skcipher,
|
||||
.setkey = geode_setkey_skcipher,
|
||||
.encrypt = geode_ecb_encrypt,
|
||||
.decrypt = geode_ecb_decrypt,
|
||||
}
|
||||
}
|
||||
.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.max_keysize = AES_MAX_KEY_SIZE,
|
||||
},
|
||||
};
|
||||
|
||||
static void geode_aes_remove(struct pci_dev *dev)
|
||||
{
|
||||
crypto_unregister_alg(&geode_alg);
|
||||
crypto_unregister_alg(&geode_ecb_alg);
|
||||
crypto_unregister_alg(&geode_cbc_alg);
|
||||
crypto_unregister_skciphers(geode_skcipher_algs,
|
||||
ARRAY_SIZE(geode_skcipher_algs));
|
||||
|
||||
pci_iounmap(dev, _iobase);
|
||||
_iobase = NULL;
|
||||
@ -547,20 +407,14 @@ static int geode_aes_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
if (ret)
|
||||
goto eiomap;
|
||||
|
||||
ret = crypto_register_alg(&geode_ecb_alg);
|
||||
ret = crypto_register_skciphers(geode_skcipher_algs,
|
||||
ARRAY_SIZE(geode_skcipher_algs));
|
||||
if (ret)
|
||||
goto ealg;
|
||||
|
||||
ret = crypto_register_alg(&geode_cbc_alg);
|
||||
if (ret)
|
||||
goto eecb;
|
||||
|
||||
dev_notice(&dev->dev, "GEODE AES engine enabled.\n");
|
||||
return 0;
|
||||
|
||||
eecb:
|
||||
crypto_unregister_alg(&geode_ecb_alg);
|
||||
|
||||
ealg:
|
||||
crypto_unregister_alg(&geode_alg);
|
||||
|
||||
|
||||
@ -46,21 +46,10 @@
|
||||
|
||||
#define AES_OP_TIMEOUT 0x50000
|
||||
|
||||
struct geode_aes_op {
|
||||
|
||||
void *src;
|
||||
void *dst;
|
||||
|
||||
u32 mode;
|
||||
u32 dir;
|
||||
u32 flags;
|
||||
int len;
|
||||
|
||||
struct geode_aes_tfm_ctx {
|
||||
u8 key[AES_KEYSIZE_128];
|
||||
u8 *iv;
|
||||
|
||||
union {
|
||||
struct crypto_sync_skcipher *blk;
|
||||
struct crypto_skcipher *skcipher;
|
||||
struct crypto_cipher *cip;
|
||||
} fallback;
|
||||
u32 keylen;
|
||||
|
||||
@ -17,6 +17,7 @@ config CRYPTO_DEV_HISI_SEC
|
||||
config CRYPTO_DEV_HISI_QM
|
||||
tristate
|
||||
depends on ARM64 && PCI && PCI_MSI
|
||||
select NEED_SG_DMA_LENGTH
|
||||
help
|
||||
HiSilicon accelerator engines use a common queue management
|
||||
interface. Specific engine driver may use this module.
|
||||
|
||||
@ -435,6 +435,11 @@ __virtio_crypto_ablkcipher_do_req(struct virtio_crypto_sym_request *vc_sym_req,
|
||||
goto free;
|
||||
}
|
||||
memcpy(iv, req->info, ivsize);
|
||||
if (!vc_sym_req->encrypt)
|
||||
scatterwalk_map_and_copy(req->info, req->src,
|
||||
req->nbytes - AES_BLOCK_SIZE,
|
||||
AES_BLOCK_SIZE, 0);
|
||||
|
||||
sg_init_one(&iv_sg, iv, ivsize);
|
||||
sgs[num_out++] = &iv_sg;
|
||||
vc_sym_req->iv = iv;
|
||||
@ -571,6 +576,10 @@ static void virtio_crypto_ablkcipher_finalize_req(
|
||||
struct ablkcipher_request *req,
|
||||
int err)
|
||||
{
|
||||
if (vc_sym_req->encrypt)
|
||||
scatterwalk_map_and_copy(req->info, req->dst,
|
||||
req->nbytes - AES_BLOCK_SIZE,
|
||||
AES_BLOCK_SIZE, 0);
|
||||
crypto_finalize_ablkcipher_request(vc_sym_req->base.dataq->engine,
|
||||
req, err);
|
||||
kzfree(vc_sym_req->iv);
|
||||
|
||||
@ -99,6 +99,7 @@ config ARM_TEGRA_DEVFREQ
|
||||
ARCH_TEGRA_210_SOC || \
|
||||
COMPILE_TEST
|
||||
select PM_OPP
|
||||
depends on COMMON_CLK
|
||||
help
|
||||
This adds the DEVFREQ driver for the Tegra family of SoCs.
|
||||
It reads ACTMON counters of memory controllers and adjusts the
|
||||
|
||||
@ -66,7 +66,7 @@ static int dw_probe(struct platform_device *pdev)
|
||||
|
||||
data->chip = chip;
|
||||
|
||||
chip->clk = devm_clk_get(chip->dev, "hclk");
|
||||
chip->clk = devm_clk_get_optional(chip->dev, "hclk");
|
||||
if (IS_ERR(chip->clk))
|
||||
return PTR_ERR(chip->clk);
|
||||
err = clk_prepare_enable(chip->clk);
|
||||
|
||||
@ -377,10 +377,11 @@ ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
|
||||
|
||||
descs->virt = dma_alloc_coherent(to_dev(ioat_chan),
|
||||
SZ_2M, &descs->hw, flags);
|
||||
if (!descs->virt && (i > 0)) {
|
||||
if (!descs->virt) {
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < i; idx++) {
|
||||
descs = &ioat_chan->descs[idx];
|
||||
dma_free_coherent(to_dev(ioat_chan), SZ_2M,
|
||||
descs->virt, descs->hw);
|
||||
descs->virt = NULL;
|
||||
|
||||
@ -346,6 +346,7 @@ static int mpc8xxx_probe(struct platform_device *pdev)
|
||||
return -ENOMEM;
|
||||
|
||||
gc = &mpc8xxx_gc->gc;
|
||||
gc->parent = &pdev->dev;
|
||||
|
||||
if (of_property_read_bool(np, "little-endian")) {
|
||||
ret = bgpio_init(gc, &pdev->dev, 4,
|
||||
|
||||
@ -681,6 +681,8 @@ static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
|
||||
unsigned int bank_num;
|
||||
|
||||
for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
|
||||
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
|
||||
ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
|
||||
writel_relaxed(gpio->context.datalsw[bank_num],
|
||||
gpio->base_addr +
|
||||
ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
|
||||
@ -690,9 +692,6 @@ static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
|
||||
writel_relaxed(gpio->context.dirm[bank_num],
|
||||
gpio->base_addr +
|
||||
ZYNQ_GPIO_DIRM_OFFSET(bank_num));
|
||||
writel_relaxed(gpio->context.int_en[bank_num],
|
||||
gpio->base_addr +
|
||||
ZYNQ_GPIO_INTEN_OFFSET(bank_num));
|
||||
writel_relaxed(gpio->context.int_type[bank_num],
|
||||
gpio->base_addr +
|
||||
ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
|
||||
@ -702,6 +701,9 @@ static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
|
||||
writel_relaxed(gpio->context.int_any[bank_num],
|
||||
gpio->base_addr +
|
||||
ZYNQ_GPIO_INTANY_OFFSET(bank_num));
|
||||
writel_relaxed(~(gpio->context.int_en[bank_num]),
|
||||
gpio->base_addr +
|
||||
ZYNQ_GPIO_INTEN_OFFSET(bank_num));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -4328,8 +4328,9 @@ static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
|
||||
|
||||
if (chip->ngpio <= p->chip_hwnum) {
|
||||
dev_err(dev,
|
||||
"requested GPIO %d is out of range [0..%d] for chip %s\n",
|
||||
idx, chip->ngpio, chip->label);
|
||||
"requested GPIO %u (%u) is out of range [0..%u] for chip %s\n",
|
||||
idx, p->chip_hwnum, chip->ngpio - 1,
|
||||
chip->label);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
|
||||
@ -813,6 +813,7 @@ struct amdgpu_device {
|
||||
uint8_t *bios;
|
||||
uint32_t bios_size;
|
||||
struct amdgpu_bo *stolen_vga_memory;
|
||||
struct amdgpu_bo *discovery_memory;
|
||||
uint32_t bios_scratch_reg_offset;
|
||||
uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
|
||||
|
||||
|
||||
@ -136,7 +136,7 @@ static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *bin
|
||||
{
|
||||
uint32_t *p = (uint32_t *)binary;
|
||||
uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
|
||||
uint64_t pos = vram_size - BINARY_MAX_SIZE;
|
||||
uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
|
||||
unsigned long flags;
|
||||
|
||||
while (pos < vram_size) {
|
||||
@ -179,7 +179,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev)
|
||||
uint16_t checksum;
|
||||
int r;
|
||||
|
||||
adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
|
||||
adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL);
|
||||
if (!adev->discovery)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
@ -24,6 +24,8 @@
|
||||
#ifndef __AMDGPU_DISCOVERY__
|
||||
#define __AMDGPU_DISCOVERY__
|
||||
|
||||
#define DISCOVERY_TMR_SIZE (64 << 10)
|
||||
|
||||
int amdgpu_discovery_init(struct amdgpu_device *adev);
|
||||
void amdgpu_discovery_fini(struct amdgpu_device *adev);
|
||||
int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
|
||||
|
||||
@ -342,6 +342,67 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
|
||||
*
|
||||
* @adev: amdgpu device object
|
||||
* @offset: offset of the BO
|
||||
* @size: size of the BO
|
||||
* @domain: where to place it
|
||||
* @bo_ptr: used to initialize BOs in structures
|
||||
* @cpu_addr: optional CPU address mapping
|
||||
*
|
||||
* Creates a kernel BO at a specific offset in the address space of the domain.
|
||||
*
|
||||
* Returns:
|
||||
* 0 on success, negative error code otherwise.
|
||||
*/
|
||||
int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
|
||||
uint64_t offset, uint64_t size, uint32_t domain,
|
||||
struct amdgpu_bo **bo_ptr, void **cpu_addr)
|
||||
{
|
||||
struct ttm_operation_ctx ctx = { false, false };
|
||||
unsigned int i;
|
||||
int r;
|
||||
|
||||
offset &= PAGE_MASK;
|
||||
size = ALIGN(size, PAGE_SIZE);
|
||||
|
||||
r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
|
||||
NULL, NULL);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/*
|
||||
* Remove the original mem node and create a new one at the request
|
||||
* position.
|
||||
*/
|
||||
for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
|
||||
(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
|
||||
(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
|
||||
}
|
||||
|
||||
ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
|
||||
r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
|
||||
&(*bo_ptr)->tbo.mem, &ctx);
|
||||
if (r)
|
||||
goto error;
|
||||
|
||||
if (cpu_addr) {
|
||||
r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
|
||||
if (r)
|
||||
goto error;
|
||||
}
|
||||
|
||||
amdgpu_bo_unreserve(*bo_ptr);
|
||||
return 0;
|
||||
|
||||
error:
|
||||
amdgpu_bo_unreserve(*bo_ptr);
|
||||
amdgpu_bo_unref(bo_ptr);
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_bo_free_kernel - free BO for kernel use
|
||||
*
|
||||
|
||||
@ -237,6 +237,9 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
|
||||
unsigned long size, int align,
|
||||
u32 domain, struct amdgpu_bo **bo_ptr,
|
||||
u64 *gpu_addr, void **cpu_addr);
|
||||
int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
|
||||
uint64_t offset, uint64_t size, uint32_t domain,
|
||||
struct amdgpu_bo **bo_ptr, void **cpu_addr);
|
||||
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
|
||||
void **cpu_addr);
|
||||
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
|
||||
|
||||
@ -65,12 +65,6 @@ const char *ras_block_string[] = {
|
||||
/* inject address is 52 bits */
|
||||
#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
|
||||
|
||||
static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
|
||||
uint64_t offset, uint64_t size,
|
||||
struct amdgpu_bo **bo_ptr);
|
||||
static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
|
||||
struct amdgpu_bo **bo_ptr);
|
||||
|
||||
static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
|
||||
size_t size, loff_t *pos)
|
||||
{
|
||||
@ -1214,75 +1208,6 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
|
||||
atomic_set(&ras->in_recovery, 0);
|
||||
}
|
||||
|
||||
static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
|
||||
struct amdgpu_bo **bo_ptr)
|
||||
{
|
||||
/* no need to free it actually. */
|
||||
amdgpu_bo_free_kernel(bo_ptr, NULL, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* reserve vram with size@offset */
|
||||
static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
|
||||
uint64_t offset, uint64_t size,
|
||||
struct amdgpu_bo **bo_ptr)
|
||||
{
|
||||
struct ttm_operation_ctx ctx = { false, false };
|
||||
struct amdgpu_bo_param bp;
|
||||
int r = 0;
|
||||
int i;
|
||||
struct amdgpu_bo *bo;
|
||||
|
||||
if (bo_ptr)
|
||||
*bo_ptr = NULL;
|
||||
memset(&bp, 0, sizeof(bp));
|
||||
bp.size = size;
|
||||
bp.byte_align = PAGE_SIZE;
|
||||
bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
|
||||
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
|
||||
AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
|
||||
bp.type = ttm_bo_type_kernel;
|
||||
bp.resv = NULL;
|
||||
|
||||
r = amdgpu_bo_create(adev, &bp, &bo);
|
||||
if (r)
|
||||
return -EINVAL;
|
||||
|
||||
r = amdgpu_bo_reserve(bo, false);
|
||||
if (r)
|
||||
goto error_reserve;
|
||||
|
||||
offset = ALIGN(offset, PAGE_SIZE);
|
||||
for (i = 0; i < bo->placement.num_placement; ++i) {
|
||||
bo->placements[i].fpfn = offset >> PAGE_SHIFT;
|
||||
bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
|
||||
}
|
||||
|
||||
ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
|
||||
r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx);
|
||||
if (r)
|
||||
goto error_pin;
|
||||
|
||||
r = amdgpu_bo_pin_restricted(bo,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
offset,
|
||||
offset + size);
|
||||
if (r)
|
||||
goto error_pin;
|
||||
|
||||
if (bo_ptr)
|
||||
*bo_ptr = bo;
|
||||
|
||||
amdgpu_bo_unreserve(bo);
|
||||
return r;
|
||||
|
||||
error_pin:
|
||||
amdgpu_bo_unreserve(bo);
|
||||
error_reserve:
|
||||
amdgpu_bo_unref(&bo);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* alloc/realloc bps array */
|
||||
static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
|
||||
struct ras_err_handler_data *data, int pages)
|
||||
@ -1345,7 +1270,7 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
|
||||
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
|
||||
struct ras_err_handler_data *data;
|
||||
uint64_t bp;
|
||||
struct amdgpu_bo *bo;
|
||||
struct amdgpu_bo *bo = NULL;
|
||||
int i;
|
||||
|
||||
if (!con || !con->eh_data)
|
||||
@ -1359,12 +1284,14 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
|
||||
for (i = data->last_reserved; i < data->count; i++) {
|
||||
bp = data->bps[i].bp;
|
||||
|
||||
if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
|
||||
PAGE_SIZE, &bo))
|
||||
if (amdgpu_bo_create_kernel_at(adev, bp << PAGE_SHIFT, PAGE_SIZE,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&bo, NULL))
|
||||
DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
|
||||
|
||||
data->bps[i].bo = bo;
|
||||
data->last_reserved = i + 1;
|
||||
bo = NULL;
|
||||
}
|
||||
out:
|
||||
mutex_unlock(&con->recovery_lock);
|
||||
@ -1390,7 +1317,7 @@ static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
|
||||
for (i = data->last_reserved - 1; i >= 0; i--) {
|
||||
bo = data->bps[i].bo;
|
||||
|
||||
amdgpu_ras_release_vram(adev, &bo);
|
||||
amdgpu_bo_free_kernel(&bo, NULL, NULL);
|
||||
|
||||
data->bps[i].bo = bo;
|
||||
data->last_reserved = i;
|
||||
|
||||
@ -1639,81 +1639,25 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
|
||||
*/
|
||||
static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct ttm_operation_ctx ctx = { false, false };
|
||||
struct amdgpu_bo_param bp;
|
||||
int r = 0;
|
||||
int i;
|
||||
u64 vram_size = adev->gmc.visible_vram_size;
|
||||
u64 offset = adev->fw_vram_usage.start_offset;
|
||||
u64 size = adev->fw_vram_usage.size;
|
||||
struct amdgpu_bo *bo;
|
||||
uint64_t vram_size = adev->gmc.visible_vram_size;
|
||||
int r;
|
||||
|
||||
memset(&bp, 0, sizeof(bp));
|
||||
bp.size = adev->fw_vram_usage.size;
|
||||
bp.byte_align = PAGE_SIZE;
|
||||
bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
|
||||
bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
|
||||
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
|
||||
bp.type = ttm_bo_type_kernel;
|
||||
bp.resv = NULL;
|
||||
adev->fw_vram_usage.va = NULL;
|
||||
adev->fw_vram_usage.reserved_bo = NULL;
|
||||
|
||||
if (adev->fw_vram_usage.size > 0 &&
|
||||
adev->fw_vram_usage.size <= vram_size) {
|
||||
if (adev->fw_vram_usage.size == 0 ||
|
||||
adev->fw_vram_usage.size > vram_size)
|
||||
return 0;
|
||||
|
||||
r = amdgpu_bo_create(adev, &bp,
|
||||
&adev->fw_vram_usage.reserved_bo);
|
||||
if (r)
|
||||
goto error_create;
|
||||
|
||||
r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
|
||||
if (r)
|
||||
goto error_reserve;
|
||||
|
||||
/* remove the original mem node and create a new one at the
|
||||
* request position
|
||||
*/
|
||||
bo = adev->fw_vram_usage.reserved_bo;
|
||||
offset = ALIGN(offset, PAGE_SIZE);
|
||||
for (i = 0; i < bo->placement.num_placement; ++i) {
|
||||
bo->placements[i].fpfn = offset >> PAGE_SHIFT;
|
||||
bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
|
||||
}
|
||||
|
||||
ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
|
||||
r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
|
||||
&bo->tbo.mem, &ctx);
|
||||
if (r)
|
||||
goto error_pin;
|
||||
|
||||
r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
return amdgpu_bo_create_kernel_at(adev,
|
||||
adev->fw_vram_usage.start_offset,
|
||||
(adev->fw_vram_usage.start_offset +
|
||||
adev->fw_vram_usage.size));
|
||||
if (r)
|
||||
goto error_pin;
|
||||
r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
|
||||
adev->fw_vram_usage.size,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&adev->fw_vram_usage.reserved_bo,
|
||||
&adev->fw_vram_usage.va);
|
||||
if (r)
|
||||
goto error_kmap;
|
||||
|
||||
amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
|
||||
}
|
||||
return r;
|
||||
|
||||
error_kmap:
|
||||
amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
|
||||
error_pin:
|
||||
amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
|
||||
error_reserve:
|
||||
amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
|
||||
error_create:
|
||||
adev->fw_vram_usage.va = NULL;
|
||||
adev->fw_vram_usage.reserved_bo = NULL;
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_ttm_init - Init the memory management (ttm) as well as various
|
||||
* gtt/vram related fields.
|
||||
@ -1786,6 +1730,20 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
|
||||
NULL, &stolen_vga_buf);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/*
|
||||
* reserve one TMR (64K) memory at the top of VRAM which holds
|
||||
* IP Discovery data and is protected by PSP.
|
||||
*/
|
||||
r = amdgpu_bo_create_kernel_at(adev,
|
||||
adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
|
||||
DISCOVERY_TMR_SIZE,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&adev->discovery_memory,
|
||||
NULL);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
|
||||
(unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
|
||||
|
||||
@ -1850,6 +1808,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
|
||||
void *stolen_vga_buf;
|
||||
/* return the VGA stolen memory (if any) back to VRAM */
|
||||
amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
|
||||
|
||||
/* return the IP Discovery TMR memory back to VRAM */
|
||||
amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -1038,17 +1038,10 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
|
||||
case CHIP_VEGA20:
|
||||
break;
|
||||
case CHIP_RAVEN:
|
||||
/* Disable GFXOFF on original raven. There are combinations
|
||||
* of sbios and platforms that are not stable.
|
||||
*/
|
||||
if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))
|
||||
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
|
||||
else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
|
||||
&&((adev->gfx.rlc_fw_version != 106 &&
|
||||
adev->gfx.rlc_fw_version < 531) ||
|
||||
(adev->gfx.rlc_fw_version == 53815) ||
|
||||
(adev->gfx.rlc_feature_version < 1) ||
|
||||
!adev->gfx.rlc.is_rlc_v2_1))
|
||||
if (!(adev->rev_id >= 0x8 ||
|
||||
adev->pdev->device == 0x15d8) &&
|
||||
(adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */
|
||||
!adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */
|
||||
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
|
||||
|
||||
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
|
||||
|
||||
@ -25,7 +25,6 @@
|
||||
#define _DISCOVERY_H_
|
||||
|
||||
#define PSP_HEADER_SIZE 256
|
||||
#define BINARY_MAX_SIZE (64 << 10)
|
||||
#define BINARY_SIGNATURE 0x28211407
|
||||
#define DISCOVERY_TABLE_SIGNATURE 0x53445049
|
||||
|
||||
|
||||
@ -56,7 +56,7 @@ malidp_mw_connector_mode_valid(struct drm_connector *connector,
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
|
||||
static const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
|
||||
.get_modes = malidp_mw_connector_get_modes,
|
||||
.mode_valid = malidp_mw_connector_mode_valid,
|
||||
};
|
||||
|
||||
@ -201,19 +201,19 @@ hub:
|
||||
if (tegra->hub)
|
||||
tegra_display_hub_cleanup(tegra->hub);
|
||||
device:
|
||||
host1x_device_exit(device);
|
||||
fbdev:
|
||||
drm_kms_helper_poll_fini(drm);
|
||||
tegra_drm_fb_free(drm);
|
||||
config:
|
||||
drm_mode_config_cleanup(drm);
|
||||
|
||||
if (tegra->domain) {
|
||||
mutex_destroy(&tegra->mm_lock);
|
||||
drm_mm_takedown(&tegra->mm);
|
||||
put_iova_domain(&tegra->carveout.domain);
|
||||
iova_cache_put();
|
||||
}
|
||||
|
||||
host1x_device_exit(device);
|
||||
fbdev:
|
||||
drm_kms_helper_poll_fini(drm);
|
||||
tegra_drm_fb_free(drm);
|
||||
config:
|
||||
drm_mode_config_cleanup(drm);
|
||||
domain:
|
||||
if (tegra->domain)
|
||||
iommu_domain_free(tegra->domain);
|
||||
|
||||
@ -249,13 +249,14 @@ out:
|
||||
static __poll_t hidraw_poll(struct file *file, poll_table *wait)
|
||||
{
|
||||
struct hidraw_list *list = file->private_data;
|
||||
__poll_t mask = EPOLLOUT | EPOLLWRNORM; /* hidraw is always writable */
|
||||
|
||||
poll_wait(file, &list->hidraw->wait, wait);
|
||||
if (list->head != list->tail)
|
||||
return EPOLLIN | EPOLLRDNORM;
|
||||
mask |= EPOLLIN | EPOLLRDNORM;
|
||||
if (!list->hidraw->exist)
|
||||
return EPOLLERR | EPOLLHUP;
|
||||
return EPOLLOUT | EPOLLWRNORM;
|
||||
mask |= EPOLLERR | EPOLLHUP;
|
||||
return mask;
|
||||
}
|
||||
|
||||
static int hidraw_open(struct inode *inode, struct file *file)
|
||||
|
||||
@ -766,13 +766,14 @@ unlock:
|
||||
static __poll_t uhid_char_poll(struct file *file, poll_table *wait)
|
||||
{
|
||||
struct uhid_device *uhid = file->private_data;
|
||||
__poll_t mask = EPOLLOUT | EPOLLWRNORM; /* uhid is always writable */
|
||||
|
||||
poll_wait(file, &uhid->waitq, wait);
|
||||
|
||||
if (uhid->head != uhid->tail)
|
||||
return EPOLLIN | EPOLLRDNORM;
|
||||
mask |= EPOLLIN | EPOLLRDNORM;
|
||||
|
||||
return EPOLLOUT | EPOLLWRNORM;
|
||||
return mask;
|
||||
}
|
||||
|
||||
static const struct file_operations uhid_fops = {
|
||||
|
||||
@ -58,6 +58,7 @@ struct bcm2835_i2c_dev {
|
||||
struct i2c_adapter adapter;
|
||||
struct completion completion;
|
||||
struct i2c_msg *curr_msg;
|
||||
struct clk *bus_clk;
|
||||
int num_msgs;
|
||||
u32 msg_err;
|
||||
u8 *msg_buf;
|
||||
@ -404,7 +405,6 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
|
||||
struct resource *mem, *irq;
|
||||
int ret;
|
||||
struct i2c_adapter *adap;
|
||||
struct clk *bus_clk;
|
||||
struct clk *mclk;
|
||||
u32 bus_clk_rate;
|
||||
|
||||
@ -427,11 +427,11 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(mclk);
|
||||
}
|
||||
|
||||
bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
|
||||
i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
|
||||
|
||||
if (IS_ERR(bus_clk)) {
|
||||
if (IS_ERR(i2c_dev->bus_clk)) {
|
||||
dev_err(&pdev->dev, "Could not register clock\n");
|
||||
return PTR_ERR(bus_clk);
|
||||
return PTR_ERR(i2c_dev->bus_clk);
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
|
||||
@ -442,13 +442,13 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
|
||||
bus_clk_rate = 100000;
|
||||
}
|
||||
|
||||
ret = clk_set_rate_exclusive(bus_clk, bus_clk_rate);
|
||||
ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Could not set clock frequency\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(bus_clk);
|
||||
ret = clk_prepare_enable(i2c_dev->bus_clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Couldn't prepare clock");
|
||||
return ret;
|
||||
@ -491,10 +491,9 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
|
||||
static int bcm2835_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
|
||||
struct clk *bus_clk = devm_clk_get(i2c_dev->dev, "div");
|
||||
|
||||
clk_rate_exclusive_put(bus_clk);
|
||||
clk_disable_unprepare(bus_clk);
|
||||
clk_rate_exclusive_put(i2c_dev->bus_clk);
|
||||
clk_disable_unprepare(i2c_dev->bus_clk);
|
||||
|
||||
free_irq(i2c_dev->irq, i2c_dev);
|
||||
i2c_del_adapter(&i2c_dev->adapter);
|
||||
|
||||
@ -454,11 +454,13 @@ static int adis16480_get_calibbias(struct iio_dev *indio_dev,
|
||||
case IIO_MAGN:
|
||||
case IIO_PRESSURE:
|
||||
ret = adis_read_reg_16(&st->adis, reg, &val16);
|
||||
if (ret == 0)
|
||||
*bias = sign_extend32(val16, 15);
|
||||
break;
|
||||
case IIO_ANGL_VEL:
|
||||
case IIO_ACCEL:
|
||||
ret = adis_read_reg_32(&st->adis, reg, &val32);
|
||||
if (ret == 0)
|
||||
*bias = sign_extend32(val32, 31);
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -152,9 +152,10 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
|
||||
.addr = 0x10,
|
||||
.mask = GENMASK(4, 3),
|
||||
},
|
||||
.fs_avl[0] = { IIO_DEGREE_TO_RAD(245), 0x0 },
|
||||
.fs_avl[1] = { IIO_DEGREE_TO_RAD(500), 0x1 },
|
||||
.fs_avl[2] = { IIO_DEGREE_TO_RAD(2000), 0x3 },
|
||||
|
||||
.fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
|
||||
.fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
|
||||
.fs_avl[2] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
|
||||
.fs_len = 3,
|
||||
},
|
||||
},
|
||||
|
||||
@ -466,10 +466,15 @@ static struct rdma_counter *rdma_get_counter_by_id(struct ib_device *dev,
|
||||
int rdma_counter_bind_qpn(struct ib_device *dev, u8 port,
|
||||
u32 qp_num, u32 counter_id)
|
||||
{
|
||||
struct rdma_port_counter *port_counter;
|
||||
struct rdma_counter *counter;
|
||||
struct ib_qp *qp;
|
||||
int ret;
|
||||
|
||||
port_counter = &dev->port_data[port].port_counter;
|
||||
if (port_counter->mode.mode == RDMA_COUNTER_MODE_AUTO)
|
||||
return -EINVAL;
|
||||
|
||||
qp = rdma_counter_get_qp(dev, qp_num);
|
||||
if (!qp)
|
||||
return -ENOENT;
|
||||
@ -506,6 +511,7 @@ err:
|
||||
int rdma_counter_bind_qpn_alloc(struct ib_device *dev, u8 port,
|
||||
u32 qp_num, u32 *counter_id)
|
||||
{
|
||||
struct rdma_port_counter *port_counter;
|
||||
struct rdma_counter *counter;
|
||||
struct ib_qp *qp;
|
||||
int ret;
|
||||
@ -513,9 +519,13 @@ int rdma_counter_bind_qpn_alloc(struct ib_device *dev, u8 port,
|
||||
if (!rdma_is_port_valid(dev, port))
|
||||
return -EINVAL;
|
||||
|
||||
if (!dev->port_data[port].port_counter.hstats)
|
||||
port_counter = &dev->port_data[port].port_counter;
|
||||
if (!port_counter->hstats)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (port_counter->mode.mode == RDMA_COUNTER_MODE_AUTO)
|
||||
return -EINVAL;
|
||||
|
||||
qp = rdma_counter_get_qp(dev, qp_num);
|
||||
if (!qp)
|
||||
return -ENOENT;
|
||||
|
||||
@ -3323,8 +3323,10 @@ int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
|
||||
int rc;
|
||||
|
||||
rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
|
||||
if (rc)
|
||||
if (rc) {
|
||||
dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
if (mr->pages) {
|
||||
rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
|
||||
|
||||
@ -2283,13 +2283,13 @@ static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq,
|
||||
/* Add qp to flush list of the CQ */
|
||||
bnxt_qplib_add_flush_qp(qp);
|
||||
} else {
|
||||
if (swq->flags & SQ_SEND_FLAGS_SIGNAL_COMP) {
|
||||
/* Before we complete, do WA 9060 */
|
||||
if (do_wa9060(qp, cq, cq_cons, sw_sq_cons,
|
||||
cqe_sq_cons)) {
|
||||
*lib_qp = qp;
|
||||
goto out;
|
||||
}
|
||||
if (swq->flags & SQ_SEND_FLAGS_SIGNAL_COMP) {
|
||||
cqe->status = CQ_REQ_STATUS_OK;
|
||||
cqe++;
|
||||
(*budget)--;
|
||||
|
||||
@ -81,6 +81,8 @@ void iowait_init(struct iowait *wait, u32 tx_limit,
|
||||
void iowait_cancel_work(struct iowait *w)
|
||||
{
|
||||
cancel_work_sync(&iowait_get_ib_work(w)->iowork);
|
||||
/* Make sure that the iowork for TID RDMA is used */
|
||||
if (iowait_get_tid_work(w)->iowork.func)
|
||||
cancel_work_sync(&iowait_get_tid_work(w)->iowork);
|
||||
}
|
||||
|
||||
|
||||
@ -1,23 +1,34 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
config INFINIBAND_HNS
|
||||
bool "HNS RoCE Driver"
|
||||
tristate "HNS RoCE Driver"
|
||||
depends on NET_VENDOR_HISILICON
|
||||
depends on ARM64 || (COMPILE_TEST && 64BIT)
|
||||
depends on (HNS_DSAF && HNS_ENET) || HNS3
|
||||
---help---
|
||||
This is a RoCE/RDMA driver for the Hisilicon RoCE engine. The engine
|
||||
is used in Hisilicon Hip06 and more further ICT SoC based on
|
||||
platform device.
|
||||
|
||||
To compile HIP06 or HIP08 driver as module, choose M here.
|
||||
|
||||
config INFINIBAND_HNS_HIP06
|
||||
tristate "Hisilicon Hip06 Family RoCE support"
|
||||
bool "Hisilicon Hip06 Family RoCE support"
|
||||
depends on INFINIBAND_HNS && HNS && HNS_DSAF && HNS_ENET
|
||||
depends on INFINIBAND_HNS=m || (HNS_DSAF=y && HNS_ENET=y)
|
||||
---help---
|
||||
RoCE driver support for Hisilicon RoCE engine in Hisilicon Hip06 and
|
||||
Hip07 SoC. These RoCE engines are platform devices.
|
||||
|
||||
To compile this driver, choose Y here: if INFINIBAND_HNS is m, this
|
||||
module will be called hns-roce-hw-v1
|
||||
|
||||
config INFINIBAND_HNS_HIP08
|
||||
tristate "Hisilicon Hip08 Family RoCE support"
|
||||
bool "Hisilicon Hip08 Family RoCE support"
|
||||
depends on INFINIBAND_HNS && PCI && HNS3
|
||||
depends on INFINIBAND_HNS=m || HNS3=y
|
||||
---help---
|
||||
RoCE driver support for Hisilicon RoCE engine in Hisilicon Hip08 SoC.
|
||||
The RoCE engine is a PCI device.
|
||||
|
||||
To compile this driver, choose Y here: if INFINIBAND_HNS is m, this
|
||||
module will be called hns-roce-hw-v2.
|
||||
|
||||
@ -9,8 +9,12 @@ hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_pd.o \
|
||||
hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \
|
||||
hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o hns_roce_srq.o hns_roce_restrack.o
|
||||
|
||||
ifdef CONFIG_INFINIBAND_HNS_HIP06
|
||||
hns-roce-hw-v1-objs := hns_roce_hw_v1.o $(hns-roce-objs)
|
||||
obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o
|
||||
obj-$(CONFIG_INFINIBAND_HNS) += hns-roce-hw-v1.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_INFINIBAND_HNS_HIP08
|
||||
hns-roce-hw-v2-objs := hns_roce_hw_v2.o hns_roce_hw_v2_dfx.o $(hns-roce-objs)
|
||||
obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns-roce-hw-v2.o
|
||||
obj-$(CONFIG_INFINIBAND_HNS) += hns-roce-hw-v2.o
|
||||
endif
|
||||
|
||||
@ -389,7 +389,7 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
|
||||
roce_set_field(ud_sq_wqe->byte_36,
|
||||
V2_UD_SEND_WQE_BYTE_36_VLAN_M,
|
||||
V2_UD_SEND_WQE_BYTE_36_VLAN_S,
|
||||
le16_to_cpu(ah->av.vlan));
|
||||
ah->av.vlan);
|
||||
roce_set_field(ud_sq_wqe->byte_36,
|
||||
V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
|
||||
V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
|
||||
@ -4650,16 +4650,14 @@ static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
|
||||
{
|
||||
struct hns_roce_cq *send_cq, *recv_cq;
|
||||
struct ib_device *ibdev = &hr_dev->ib_dev;
|
||||
int ret;
|
||||
int ret = 0;
|
||||
|
||||
if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
|
||||
/* Modify qp to reset before destroying qp */
|
||||
ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
|
||||
hr_qp->state, IB_QPS_RESET);
|
||||
if (ret) {
|
||||
if (ret)
|
||||
ibdev_err(ibdev, "modify QP to Reset failed.\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
|
||||
@ -4715,7 +4713,7 @@ static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
|
||||
kfree(hr_qp->rq_inl_buf.wqe_list);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
|
||||
@ -4725,11 +4723,9 @@ static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
|
||||
int ret;
|
||||
|
||||
ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
|
||||
if (ret) {
|
||||
if (ret)
|
||||
ibdev_err(&hr_dev->ib_dev, "Destroy qp 0x%06lx failed(%d)\n",
|
||||
hr_qp->qpn, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
|
||||
kfree(hr_to_hr_sqp(hr_qp));
|
||||
@ -6092,11 +6088,11 @@ static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
|
||||
roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
|
||||
SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
|
||||
SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
|
||||
hr_dev->caps.idx_ba_pg_sz);
|
||||
hr_dev->caps.idx_ba_pg_sz + PG_SHIFT_OFFSET);
|
||||
roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
|
||||
SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
|
||||
SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
|
||||
hr_dev->caps.idx_buf_pg_sz);
|
||||
hr_dev->caps.idx_buf_pg_sz + PG_SHIFT_OFFSET);
|
||||
|
||||
srq_context->idx_nxt_blk_addr =
|
||||
cpu_to_le32(mtts_idx[1] >> PAGE_ADDR_SHIFT);
|
||||
|
||||
@ -87,8 +87,8 @@
|
||||
#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
|
||||
#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
|
||||
#define HNS_ROCE_V2_SCCC_ENTRY_SZ 32
|
||||
#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ 4096
|
||||
#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ 4096
|
||||
#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE
|
||||
#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
|
||||
#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
|
||||
#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
|
||||
#define HNS_ROCE_INVALID_LKEY 0x100
|
||||
|
||||
@ -332,8 +332,7 @@ static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev,
|
||||
u8 max_sq_stride = ilog2(roundup_sq_stride);
|
||||
|
||||
/* Sanity check SQ size before proceeding */
|
||||
if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes ||
|
||||
ucmd->log_sq_stride > max_sq_stride ||
|
||||
if (ucmd->log_sq_stride > max_sq_stride ||
|
||||
ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
|
||||
ibdev_err(&hr_dev->ib_dev, "check SQ size error!\n");
|
||||
return -EINVAL;
|
||||
@ -358,13 +357,16 @@ static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
|
||||
u32 max_cnt;
|
||||
int ret;
|
||||
|
||||
if (check_shl_overflow(1, ucmd->log_sq_bb_count, &hr_qp->sq.wqe_cnt) ||
|
||||
hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes)
|
||||
return -EINVAL;
|
||||
|
||||
ret = check_sq_size_with_integrity(hr_dev, cap, ucmd);
|
||||
if (ret) {
|
||||
ibdev_err(&hr_dev->ib_dev, "Sanity check sq size failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
|
||||
hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
|
||||
|
||||
max_cnt = max(1U, cap->max_send_sge);
|
||||
|
||||
@ -95,7 +95,7 @@ static int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
|
||||
|
||||
ret = hr_dev->dfx->query_cqc_info(hr_dev, hr_cq->cqn, (int *)context);
|
||||
if (ret)
|
||||
goto err;
|
||||
return -EINVAL;
|
||||
|
||||
table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER);
|
||||
if (!table_attr) {
|
||||
|
||||
@ -428,7 +428,7 @@ struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry)
|
||||
|
||||
if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) {
|
||||
mlx5_ib_err(dev, "cache entry %d is out of range\n", entry);
|
||||
return NULL;
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
ent = &cache->ent[entry];
|
||||
|
||||
@ -1867,14 +1867,7 @@ static int siw_listen_address(struct iw_cm_id *id, int backlog,
|
||||
list_add_tail(&cep->listenq, (struct list_head *)id->provider_data);
|
||||
cep->state = SIW_EPSTATE_LISTENING;
|
||||
|
||||
if (addr_family == AF_INET)
|
||||
siw_dbg(id->device, "Listen at laddr %pI4 %u\n",
|
||||
&(((struct sockaddr_in *)laddr)->sin_addr),
|
||||
((struct sockaddr_in *)laddr)->sin_port);
|
||||
else
|
||||
siw_dbg(id->device, "Listen at laddr %pI6 %u\n",
|
||||
&(((struct sockaddr_in6 *)laddr)->sin6_addr),
|
||||
((struct sockaddr_in6 *)laddr)->sin6_port);
|
||||
siw_dbg(id->device, "Listen at laddr %pISp\n", laddr);
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@ -1364,9 +1364,11 @@ static int srpt_build_cmd_rsp(struct srpt_rdma_ch *ch,
|
||||
struct srpt_send_ioctx *ioctx, u64 tag,
|
||||
int status)
|
||||
{
|
||||
struct se_cmd *cmd = &ioctx->cmd;
|
||||
struct srp_rsp *srp_rsp;
|
||||
const u8 *sense_data;
|
||||
int sense_data_len, max_sense_len;
|
||||
u32 resid = cmd->residual_count;
|
||||
|
||||
/*
|
||||
* The lowest bit of all SAM-3 status codes is zero (see also
|
||||
@ -1388,6 +1390,28 @@ static int srpt_build_cmd_rsp(struct srpt_rdma_ch *ch,
|
||||
srp_rsp->tag = tag;
|
||||
srp_rsp->status = status;
|
||||
|
||||
if (cmd->se_cmd_flags & SCF_UNDERFLOW_BIT) {
|
||||
if (cmd->data_direction == DMA_TO_DEVICE) {
|
||||
/* residual data from an underflow write */
|
||||
srp_rsp->flags = SRP_RSP_FLAG_DOUNDER;
|
||||
srp_rsp->data_out_res_cnt = cpu_to_be32(resid);
|
||||
} else if (cmd->data_direction == DMA_FROM_DEVICE) {
|
||||
/* residual data from an underflow read */
|
||||
srp_rsp->flags = SRP_RSP_FLAG_DIUNDER;
|
||||
srp_rsp->data_in_res_cnt = cpu_to_be32(resid);
|
||||
}
|
||||
} else if (cmd->se_cmd_flags & SCF_OVERFLOW_BIT) {
|
||||
if (cmd->data_direction == DMA_TO_DEVICE) {
|
||||
/* residual data from an overflow write */
|
||||
srp_rsp->flags = SRP_RSP_FLAG_DOOVER;
|
||||
srp_rsp->data_out_res_cnt = cpu_to_be32(resid);
|
||||
} else if (cmd->data_direction == DMA_FROM_DEVICE) {
|
||||
/* residual data from an overflow read */
|
||||
srp_rsp->flags = SRP_RSP_FLAG_DIOVER;
|
||||
srp_rsp->data_in_res_cnt = cpu_to_be32(resid);
|
||||
}
|
||||
}
|
||||
|
||||
if (sense_data_len) {
|
||||
BUILD_BUG_ON(MIN_MAX_RSP_SIZE <= sizeof(*srp_rsp));
|
||||
max_sense_len = ch->max_ti_iu_len - sizeof(*srp_rsp);
|
||||
|
||||
@ -5593,8 +5593,10 @@ static int intel_iommu_add_device(struct device *dev)
|
||||
|
||||
group = iommu_group_get_for_dev(dev);
|
||||
|
||||
if (IS_ERR(group))
|
||||
return PTR_ERR(group);
|
||||
if (IS_ERR(group)) {
|
||||
ret = PTR_ERR(group);
|
||||
goto unlink;
|
||||
}
|
||||
|
||||
iommu_group_put(group);
|
||||
|
||||
@ -5620,7 +5622,8 @@ static int intel_iommu_add_device(struct device *dev)
|
||||
if (!get_private_domain_for_dev(dev)) {
|
||||
dev_warn(dev,
|
||||
"Failed to get a private domain.\n");
|
||||
return -ENOMEM;
|
||||
ret = -ENOMEM;
|
||||
goto unlink;
|
||||
}
|
||||
|
||||
dev_info(dev,
|
||||
@ -5635,6 +5638,10 @@ static int intel_iommu_add_device(struct device *dev)
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
unlink:
|
||||
iommu_device_unlink(&iommu->iommu, dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void intel_iommu_remove_device(struct device *dev)
|
||||
|
||||
@ -768,6 +768,7 @@ err_put_group:
|
||||
mutex_unlock(&group->mutex);
|
||||
dev->iommu_group = NULL;
|
||||
kobject_put(group->devices_kobj);
|
||||
sysfs_remove_link(group->devices_kobj, device->name);
|
||||
err_free_name:
|
||||
kfree(device->name);
|
||||
err_remove_link:
|
||||
|
||||
@ -219,22 +219,37 @@ static void mtk_iommu_tlb_sync(void *cookie)
|
||||
static void mtk_iommu_tlb_flush_walk(unsigned long iova, size_t size,
|
||||
size_t granule, void *cookie)
|
||||
{
|
||||
struct mtk_iommu_data *data = cookie;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&data->tlb_lock, flags);
|
||||
mtk_iommu_tlb_add_flush_nosync(iova, size, granule, false, cookie);
|
||||
mtk_iommu_tlb_sync(cookie);
|
||||
spin_unlock_irqrestore(&data->tlb_lock, flags);
|
||||
}
|
||||
|
||||
static void mtk_iommu_tlb_flush_leaf(unsigned long iova, size_t size,
|
||||
size_t granule, void *cookie)
|
||||
{
|
||||
struct mtk_iommu_data *data = cookie;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&data->tlb_lock, flags);
|
||||
mtk_iommu_tlb_add_flush_nosync(iova, size, granule, true, cookie);
|
||||
mtk_iommu_tlb_sync(cookie);
|
||||
spin_unlock_irqrestore(&data->tlb_lock, flags);
|
||||
}
|
||||
|
||||
static void mtk_iommu_tlb_flush_page_nosync(struct iommu_iotlb_gather *gather,
|
||||
unsigned long iova, size_t granule,
|
||||
void *cookie)
|
||||
{
|
||||
struct mtk_iommu_data *data = cookie;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&data->tlb_lock, flags);
|
||||
mtk_iommu_tlb_add_flush_nosync(iova, granule, granule, true, cookie);
|
||||
spin_unlock_irqrestore(&data->tlb_lock, flags);
|
||||
}
|
||||
|
||||
static const struct iommu_flush_ops mtk_iommu_flush_ops = {
|
||||
@ -447,13 +462,18 @@ static size_t mtk_iommu_unmap(struct iommu_domain *domain,
|
||||
|
||||
static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
|
||||
{
|
||||
mtk_iommu_tlb_sync(mtk_iommu_get_m4u_data());
|
||||
mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data());
|
||||
}
|
||||
|
||||
static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
|
||||
struct iommu_iotlb_gather *gather)
|
||||
{
|
||||
mtk_iommu_tlb_sync(mtk_iommu_get_m4u_data());
|
||||
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&data->tlb_lock, flags);
|
||||
mtk_iommu_tlb_sync(data);
|
||||
spin_unlock_irqrestore(&data->tlb_lock, flags);
|
||||
}
|
||||
|
||||
static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
@ -733,6 +753,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
spin_lock_init(&data->tlb_lock);
|
||||
list_add_tail(&data->list, &m4ulist);
|
||||
|
||||
if (!iommu_present(&platform_bus_type))
|
||||
|
||||
@ -58,6 +58,7 @@ struct mtk_iommu_data {
|
||||
struct iommu_group *m4u_group;
|
||||
bool enable_4GB;
|
||||
bool tlb_flush_active;
|
||||
spinlock_t tlb_lock; /* lock for tlb range flush */
|
||||
|
||||
struct iommu_device iommu;
|
||||
const struct mtk_iommu_plat_data *plat_data;
|
||||
|
||||
@ -201,7 +201,6 @@ struct ov6650 {
|
||||
unsigned long pclk_max; /* from resolution and format */
|
||||
struct v4l2_fract tpf; /* as requested with s_frame_interval */
|
||||
u32 code;
|
||||
enum v4l2_colorspace colorspace;
|
||||
};
|
||||
|
||||
|
||||
@ -214,6 +213,17 @@ static u32 ov6650_codes[] = {
|
||||
MEDIA_BUS_FMT_Y8_1X8,
|
||||
};
|
||||
|
||||
static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
|
||||
.width = W_CIF,
|
||||
.height = H_CIF,
|
||||
.code = MEDIA_BUS_FMT_SBGGR8_1X8,
|
||||
.colorspace = V4L2_COLORSPACE_SRGB,
|
||||
.field = V4L2_FIELD_NONE,
|
||||
.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
|
||||
.quantization = V4L2_QUANTIZATION_DEFAULT,
|
||||
.xfer_func = V4L2_XFER_FUNC_DEFAULT,
|
||||
};
|
||||
|
||||
/* read a register */
|
||||
static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
|
||||
{
|
||||
@ -514,12 +524,20 @@ static int ov6650_get_fmt(struct v4l2_subdev *sd,
|
||||
if (format->pad)
|
||||
return -EINVAL;
|
||||
|
||||
/* initialize response with default media bus frame format */
|
||||
*mf = ov6650_def_fmt;
|
||||
|
||||
/* update media bus format code and frame size */
|
||||
if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
|
||||
mf->width = cfg->try_fmt.width;
|
||||
mf->height = cfg->try_fmt.height;
|
||||
mf->code = cfg->try_fmt.code;
|
||||
|
||||
} else {
|
||||
mf->width = priv->rect.width >> priv->half_scale;
|
||||
mf->height = priv->rect.height >> priv->half_scale;
|
||||
mf->code = priv->code;
|
||||
mf->colorspace = priv->colorspace;
|
||||
mf->field = V4L2_FIELD_NONE;
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -624,11 +642,6 @@ static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
|
||||
priv->pclk_max = 8000000;
|
||||
}
|
||||
|
||||
if (code == MEDIA_BUS_FMT_SBGGR8_1X8)
|
||||
priv->colorspace = V4L2_COLORSPACE_SRGB;
|
||||
else if (code != 0)
|
||||
priv->colorspace = V4L2_COLORSPACE_JPEG;
|
||||
|
||||
if (half_scale) {
|
||||
dev_dbg(&client->dev, "max resolution: QCIF\n");
|
||||
coma_set |= COMA_QCIF;
|
||||
@ -662,11 +675,6 @@ static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
|
||||
if (!ret)
|
||||
priv->code = code;
|
||||
|
||||
if (!ret) {
|
||||
mf->colorspace = priv->colorspace;
|
||||
mf->width = priv->rect.width >> half_scale;
|
||||
mf->height = priv->rect.height >> half_scale;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -685,8 +693,6 @@ static int ov6650_set_fmt(struct v4l2_subdev *sd,
|
||||
v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
|
||||
&mf->height, 2, H_CIF, 1, 0);
|
||||
|
||||
mf->field = V4L2_FIELD_NONE;
|
||||
|
||||
switch (mf->code) {
|
||||
case MEDIA_BUS_FMT_Y10_1X10:
|
||||
mf->code = MEDIA_BUS_FMT_Y8_1X8;
|
||||
@ -696,20 +702,39 @@ static int ov6650_set_fmt(struct v4l2_subdev *sd,
|
||||
case MEDIA_BUS_FMT_YUYV8_2X8:
|
||||
case MEDIA_BUS_FMT_VYUY8_2X8:
|
||||
case MEDIA_BUS_FMT_UYVY8_2X8:
|
||||
mf->colorspace = V4L2_COLORSPACE_JPEG;
|
||||
break;
|
||||
default:
|
||||
mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
|
||||
/* fall through */
|
||||
case MEDIA_BUS_FMT_SBGGR8_1X8:
|
||||
mf->colorspace = V4L2_COLORSPACE_SRGB;
|
||||
break;
|
||||
}
|
||||
|
||||
if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
|
||||
return ov6650_s_fmt(sd, mf);
|
||||
cfg->try_fmt = *mf;
|
||||
if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
|
||||
/* store media bus format code and frame size in pad config */
|
||||
cfg->try_fmt.width = mf->width;
|
||||
cfg->try_fmt.height = mf->height;
|
||||
cfg->try_fmt.code = mf->code;
|
||||
|
||||
/* return default mbus frame format updated with pad config */
|
||||
*mf = ov6650_def_fmt;
|
||||
mf->width = cfg->try_fmt.width;
|
||||
mf->height = cfg->try_fmt.height;
|
||||
mf->code = cfg->try_fmt.code;
|
||||
|
||||
} else {
|
||||
/* apply new media bus format code and frame size */
|
||||
int ret = ov6650_s_fmt(sd, mf);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* return default format updated with active size and code */
|
||||
*mf = ov6650_def_fmt;
|
||||
mf->width = priv->rect.width >> priv->half_scale;
|
||||
mf->height = priv->rect.height >> priv->half_scale;
|
||||
mf->code = priv->code;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -852,6 +877,11 @@ static int ov6650_video_probe(struct v4l2_subdev *sd)
|
||||
ret = ov6650_reset(client);
|
||||
if (!ret)
|
||||
ret = ov6650_prog_dflt(client);
|
||||
if (!ret) {
|
||||
struct v4l2_mbus_framefmt mf = ov6650_def_fmt;
|
||||
|
||||
ret = ov6650_s_fmt(sd, &mf);
|
||||
}
|
||||
if (!ret)
|
||||
ret = v4l2_ctrl_handler_setup(&priv->hdl);
|
||||
|
||||
@ -1006,9 +1036,6 @@ static int ov6650_probe(struct i2c_client *client,
|
||||
priv->rect.top = DEF_VSTRT << 1;
|
||||
priv->rect.width = W_CIF;
|
||||
priv->rect.height = H_CIF;
|
||||
priv->half_scale = false;
|
||||
priv->code = MEDIA_BUS_FMT_YUYV8_2X8;
|
||||
priv->colorspace = V4L2_COLORSPACE_JPEG;
|
||||
|
||||
/* Hardware default frame interval */
|
||||
priv->tpf.numerator = GET_CLKRC_DIV(DEF_CLKRC);
|
||||
|
||||
@ -1658,7 +1658,8 @@ static int aspeed_video_probe(struct platform_device *pdev)
|
||||
{
|
||||
int rc;
|
||||
struct resource *res;
|
||||
struct aspeed_video *video = kzalloc(sizeof(*video), GFP_KERNEL);
|
||||
struct aspeed_video *video =
|
||||
devm_kzalloc(&pdev->dev, sizeof(*video), GFP_KERNEL);
|
||||
|
||||
if (!video)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -129,7 +129,7 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
|
||||
*/
|
||||
for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) {
|
||||
unsigned int idx = find_first_zero_bit(&lanes_used,
|
||||
sizeof(lanes_used));
|
||||
csi2rx->max_lanes);
|
||||
set_bit(idx, &lanes_used);
|
||||
reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1);
|
||||
}
|
||||
|
||||
@ -1084,16 +1084,16 @@ static int coda_decoder_cmd(struct file *file, void *fh,
|
||||
|
||||
switch (dc->cmd) {
|
||||
case V4L2_DEC_CMD_START:
|
||||
mutex_lock(&ctx->bitstream_mutex);
|
||||
mutex_lock(&dev->coda_mutex);
|
||||
mutex_lock(&ctx->bitstream_mutex);
|
||||
coda_bitstream_flush(ctx);
|
||||
mutex_unlock(&dev->coda_mutex);
|
||||
dst_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
|
||||
V4L2_BUF_TYPE_VIDEO_CAPTURE);
|
||||
vb2_clear_last_buffer_dequeued(dst_vq);
|
||||
ctx->bit_stream_param &= ~CODA_BIT_STREAM_END_FLAG;
|
||||
coda_fill_bitstream(ctx, NULL);
|
||||
mutex_unlock(&ctx->bitstream_mutex);
|
||||
mutex_unlock(&dev->coda_mutex);
|
||||
break;
|
||||
case V4L2_DEC_CMD_STOP:
|
||||
stream_end = false;
|
||||
|
||||
@ -313,7 +313,7 @@ static int isp_video_release(struct file *file)
|
||||
ivc->streaming = 0;
|
||||
}
|
||||
|
||||
vb2_fop_release(file);
|
||||
_vb2_fop_release(file, NULL);
|
||||
|
||||
if (v4l2_fh_is_singular_file(file)) {
|
||||
fimc_pipeline_call(&ivc->ve, close);
|
||||
|
||||
@ -208,6 +208,7 @@ static int rvin_try_format(struct rvin_dev *vin, u32 which,
|
||||
ret = v4l2_subdev_call(sd, pad, set_fmt, pad_cfg, &format);
|
||||
if (ret < 0 && ret != -ENOIOCTLCMD)
|
||||
goto done;
|
||||
ret = 0;
|
||||
|
||||
v4l2_fill_pix_format(pix, &format.format);
|
||||
|
||||
@ -242,7 +243,7 @@ static int rvin_try_format(struct rvin_dev *vin, u32 which,
|
||||
done:
|
||||
v4l2_subdev_free_pad_config(pad_cfg);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rvin_querycap(struct file *file, void *priv,
|
||||
|
||||
@ -366,6 +366,8 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
|
||||
|
||||
static const struct dev_pm_ops smi_larb_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver mtk_smi_larb_driver = {
|
||||
@ -507,6 +509,8 @@ static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
|
||||
|
||||
static const struct dev_pm_ops smi_common_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver mtk_smi_common_driver = {
|
||||
|
||||
@ -406,10 +406,9 @@ int enclosure_remove_device(struct enclosure_device *edev, struct device *dev)
|
||||
cdev = &edev->component[i];
|
||||
if (cdev->dev == dev) {
|
||||
enclosure_remove_links(cdev);
|
||||
device_del(&cdev->cdev);
|
||||
put_device(dev);
|
||||
cdev->dev = NULL;
|
||||
return device_add(&cdev->cdev);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return -ENODEV;
|
||||
|
||||
@ -328,7 +328,8 @@ static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
|
||||
struct dma_async_tx_descriptor *tx;
|
||||
dma_cookie_t cookie;
|
||||
|
||||
tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
|
||||
tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count,
|
||||
DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
|
||||
if (!tx) {
|
||||
dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
|
||||
return -EIO;
|
||||
|
||||
@ -37,6 +37,7 @@
|
||||
/* Max ECC buffer length */
|
||||
#define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
|
||||
|
||||
#define FMC2_TIMEOUT_US 1000
|
||||
#define FMC2_TIMEOUT_MS 1000
|
||||
|
||||
/* Timings */
|
||||
@ -53,6 +54,8 @@
|
||||
#define FMC2_PMEM 0x88
|
||||
#define FMC2_PATT 0x8c
|
||||
#define FMC2_HECCR 0x94
|
||||
#define FMC2_ISR 0x184
|
||||
#define FMC2_ICR 0x188
|
||||
#define FMC2_CSQCR 0x200
|
||||
#define FMC2_CSQCFGR1 0x204
|
||||
#define FMC2_CSQCFGR2 0x208
|
||||
@ -118,6 +121,12 @@
|
||||
#define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24)
|
||||
#define FMC2_PATT_DEFAULT 0x0a0a0a0a
|
||||
|
||||
/* Register: FMC2_ISR */
|
||||
#define FMC2_ISR_IHLF BIT(1)
|
||||
|
||||
/* Register: FMC2_ICR */
|
||||
#define FMC2_ICR_CIHLF BIT(1)
|
||||
|
||||
/* Register: FMC2_CSQCR */
|
||||
#define FMC2_CSQCR_CSQSTART BIT(0)
|
||||
|
||||
@ -1322,6 +1331,31 @@ static void stm32_fmc2_write_data(struct nand_chip *chip, const void *buf,
|
||||
stm32_fmc2_set_buswidth_16(fmc2, true);
|
||||
}
|
||||
|
||||
static int stm32_fmc2_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
|
||||
{
|
||||
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
|
||||
const struct nand_sdr_timings *timings;
|
||||
u32 isr, sr;
|
||||
|
||||
/* Check if there is no pending requests to the NAND flash */
|
||||
if (readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_SR, sr,
|
||||
sr & FMC2_SR_NWRF, 1,
|
||||
FMC2_TIMEOUT_US))
|
||||
dev_warn(fmc2->dev, "Waitrdy timeout\n");
|
||||
|
||||
/* Wait tWB before R/B# signal is low */
|
||||
timings = nand_get_sdr_timings(&chip->data_interface);
|
||||
ndelay(PSEC_TO_NSEC(timings->tWB_max));
|
||||
|
||||
/* R/B# signal is low, clear high level flag */
|
||||
writel_relaxed(FMC2_ICR_CIHLF, fmc2->io_base + FMC2_ICR);
|
||||
|
||||
/* Wait R/B# signal is high */
|
||||
return readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_ISR,
|
||||
isr, isr & FMC2_ISR_IHLF,
|
||||
5, 1000 * timeout_ms);
|
||||
}
|
||||
|
||||
static int stm32_fmc2_exec_op(struct nand_chip *chip,
|
||||
const struct nand_operation *op,
|
||||
bool check_only)
|
||||
@ -1366,7 +1400,7 @@ static int stm32_fmc2_exec_op(struct nand_chip *chip,
|
||||
break;
|
||||
|
||||
case NAND_OP_WAITRDY_INSTR:
|
||||
ret = nand_soft_waitrdy(chip,
|
||||
ret = stm32_fmc2_waitrdy(chip,
|
||||
instr->ctx.waitrdy.timeout_ms);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -2544,7 +2544,7 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
|
||||
size_t *retlen, u_char *buf)
|
||||
{
|
||||
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
||||
int ret;
|
||||
ssize_t ret;
|
||||
|
||||
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
|
||||
|
||||
@ -2865,7 +2865,7 @@ static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
|
||||
*/
|
||||
static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
|
||||
{
|
||||
int ret;
|
||||
ssize_t ret;
|
||||
|
||||
while (len) {
|
||||
ret = spi_nor_read_data(nor, addr, len, buf);
|
||||
|
||||
@ -84,7 +84,7 @@ static int ath9k_pci_fixup(struct pci_dev *pdev, const u16 *cal_data,
|
||||
val = swahb32(val);
|
||||
}
|
||||
|
||||
__raw_writel(val, mem + reg);
|
||||
iowrite32(val, mem + reg);
|
||||
usleep_range(100, 120);
|
||||
}
|
||||
|
||||
|
||||
@ -514,6 +514,18 @@ static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
|
||||
struct iwl_phy_cfg_cmd phy_cfg_cmd;
|
||||
enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
|
||||
|
||||
if (iwl_mvm_has_unified_ucode(mvm) &&
|
||||
!mvm->trans->cfg->tx_with_siso_diversity) {
|
||||
return 0;
|
||||
} else if (mvm->trans->cfg->tx_with_siso_diversity) {
|
||||
/*
|
||||
* TODO: currently we don't set the antenna but letting the NIC
|
||||
* to decide which antenna to use. This should come from BIOS.
|
||||
*/
|
||||
phy_cfg_cmd.phy_cfg =
|
||||
cpu_to_le32(FW_PHY_CFG_CHAIN_SAD_ENABLED);
|
||||
}
|
||||
|
||||
/* Set parameters */
|
||||
phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
|
||||
|
||||
@ -1344,11 +1356,11 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
|
||||
ret = iwl_send_phy_db_data(mvm->phy_db);
|
||||
if (ret)
|
||||
goto error;
|
||||
}
|
||||
|
||||
ret = iwl_send_phy_cfg_cmd(mvm);
|
||||
if (ret)
|
||||
goto error;
|
||||
}
|
||||
|
||||
ret = iwl_mvm_send_bt_init_conf(mvm);
|
||||
if (ret)
|
||||
|
||||
@ -350,7 +350,13 @@ void iwl_mvm_tlc_update_notif(struct iwl_mvm *mvm,
|
||||
u16 size = le32_to_cpu(notif->amsdu_size);
|
||||
int i;
|
||||
|
||||
if (WARN_ON(sta->max_amsdu_len < size))
|
||||
/*
|
||||
* In debug sta->max_amsdu_len < size
|
||||
* so also check with orig_amsdu_len which holds the original
|
||||
* data before debugfs changed the value
|
||||
*/
|
||||
if (WARN_ON(sta->max_amsdu_len < size &&
|
||||
mvmsta->orig_amsdu_len < size))
|
||||
goto out;
|
||||
|
||||
mvmsta->amsdu_enabled = le32_to_cpu(notif->amsdu_enabled);
|
||||
|
||||
@ -935,7 +935,12 @@ static int iwl_mvm_tx_tso(struct iwl_mvm *mvm, struct sk_buff *skb,
|
||||
!(mvmsta->amsdu_enabled & BIT(tid)))
|
||||
return iwl_mvm_tx_tso_segment(skb, 1, netdev_flags, mpdus_skb);
|
||||
|
||||
max_amsdu_len = iwl_mvm_max_amsdu_size(mvm, sta, tid);
|
||||
/*
|
||||
* Take the min of ieee80211 station and mvm station
|
||||
*/
|
||||
max_amsdu_len =
|
||||
min_t(unsigned int, sta->max_amsdu_len,
|
||||
iwl_mvm_max_amsdu_size(mvm, sta, tid));
|
||||
|
||||
/*
|
||||
* Limit A-MSDU in A-MPDU to 4095 bytes when VHT is not
|
||||
|
||||
@ -386,7 +386,7 @@ int rtl_regd_init(struct ieee80211_hw *hw,
|
||||
struct wiphy *wiphy = hw->wiphy;
|
||||
struct country_code_to_enum_rd *country = NULL;
|
||||
|
||||
if (wiphy == NULL || &rtlpriv->regd == NULL)
|
||||
if (!wiphy)
|
||||
return -EINVAL;
|
||||
|
||||
/* init country_code from efuse channel plan */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user