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drm/vc4: dsi: Correct DSI divider calculations

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[ Upstream commit 3b45eee87da171caa28f61240ddb5c21170cda53 ]

The divider calculations tried to find the divider just faster than the
clock requested. However if it required a divider of 7 then the for loop
aborted without handling the "error" case, and could end up with a clock
lower than requested.

The integer divider from parent PLL to DSI clock is also capable of
going up to /255, not just /7 that the driver was trying.  This allows
for slower link frequencies on the DSI bus where the resolution permits.

Correct the loop so that we always have a clock greater than requested,
and covering the whole range of dividers.

Fixes: 86c1b9eff3 ("drm/vc4: Adjust modes in DSI to work around the integer PLL divider.")
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20220613144800.326124-13-maxime@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dave Stevenson 2022-06-13 16:47:39 +02:00 committed by Greg Kroah-Hartman
parent 120161c127
commit b53cbaf9b3
1 changed files with 2 additions and 4 deletions
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6
drivers/gpu/drm/vc4/vc4_dsi.c
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@ -791,11 +791,9 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
/* Find what divider gets us a faster clock than the requested
* pixel clock.
*/
for (divider = 1; divider < 8; divider++) {
if (parent_rate / divider < pll_clock) {
divider--;
for (divider = 1; divider < 255; divider++) {
if (parent_rate / (divider + 1) < pll_clock)
break;
}
}
/* Now that we've picked a PLL divider, calculate back to its