qcom-llcc-pmu: Update the LLCC PMU configurations for kona
Kona has new LLCC PMU version. This brought in changes in the monitor enable, disable and configuration registers and hence made code changes accordingly to read cache misses for multiple CPUs. Change-Id: I4d25487966a31f12143e2f99264a25d8c38f0188 Signed-off-by: Rama Aparna Mallavarapu <aparnam@codeaurora.org> [avajid@codeaurora.org: updated version enum, fixed disable/clear masks and made minor styling changes] Signed-off-by: Amir Vajid <avajid@codeaurora.org>
This commit is contained in:
Rama Aparna Mallavarapu
Amir Vajid
parent
e43263bdea
commit
b6d80a179b
@ -4,6 +4,7 @@
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*/
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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@ -14,11 +15,17 @@
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#include <linux/spinlock.h>
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#include <linux/ktime.h>
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enum llcc_pmu_version {
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LLCC_PMU_VER1 = 1,
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LLCC_PMU_VER2,
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};
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struct llcc_pmu {
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struct pmu pmu;
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struct hlist_node node;
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void __iomem *lagg_base;
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struct perf_event event;
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enum llcc_pmu_version ver;
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};
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#define MON_CFG(m) ((m)->lagg_base + 0x200)
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@ -26,9 +33,10 @@ struct llcc_pmu {
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#define to_llcc_pmu(ptr) (container_of(ptr, struct llcc_pmu, pmu))
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#define LLCC_RD_EV 0x1000
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#define ENABLE 0x01
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#define ENABLE 0x1
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#define CLEAR 0x10
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#define DISABLE 0x00
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#define CLEAR_POS 16
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#define DISABLE 0x0
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#define SCALING_FACTOR 0x3
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#define NUM_COUNTERS NR_CPUS
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#define VALUE_MASK 0xFFFFFF
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@ -38,6 +46,93 @@ static unsigned int users;
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static raw_spinlock_t counter_lock;
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static raw_spinlock_t users_lock;
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static ktime_t last_read;
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static DEFINE_PER_CPU(unsigned int, users_alive);
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static void mon_disable(struct llcc_pmu *llccpmu, int cpu)
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{
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u32 reg;
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if (!llccpmu->ver) {
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pr_err("LLCCPMU version not correct\n");
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return;
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}
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switch (llccpmu->ver) {
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case LLCC_PMU_VER1:
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writel_relaxed(DISABLE, MON_CFG(llccpmu));
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break;
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case LLCC_PMU_VER2:
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reg = readl_relaxed(MON_CFG(llccpmu));
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reg &= ~(ENABLE << cpu);
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writel_relaxed(reg, MON_CFG(llccpmu));
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break;
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}
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}
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static void mon_clear(struct llcc_pmu *llccpmu, int cpu)
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{
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int clear_bit = CLEAR_POS + cpu;
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u32 reg;
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if (!llccpmu->ver) {
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pr_err("LLCCPMU version not correct\n");
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return;
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}
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switch (llccpmu->ver) {
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case LLCC_PMU_VER1:
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writel_relaxed(CLEAR, MON_CFG(llccpmu));
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break;
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case LLCC_PMU_VER2:
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reg = readl_relaxed(MON_CFG(llccpmu));
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reg |= (ENABLE << clear_bit);
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writel_relaxed(reg, MON_CFG(llccpmu));
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reg &= ~(ENABLE << clear_bit);
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writel_relaxed(reg, MON_CFG(llccpmu));
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break;
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}
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}
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static void mon_enable(struct llcc_pmu *llccpmu, int cpu)
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{
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u32 reg;
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if (!llccpmu->ver) {
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pr_err("LLCCPMU version not correct\n");
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return;
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}
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switch (llccpmu->ver) {
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case LLCC_PMU_VER1:
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writel_relaxed(ENABLE, MON_CFG(llccpmu));
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break;
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case LLCC_PMU_VER2:
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reg = readl_relaxed(MON_CFG(llccpmu));
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reg |= (ENABLE << cpu);
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writel_relaxed(reg, MON_CFG(llccpmu));
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break;
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}
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}
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static unsigned long read_cnt(struct llcc_pmu *llccpmu, int cpu)
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{
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unsigned long value;
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if (!llccpmu->ver) {
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pr_err("LLCCPMU version not correct\n");
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return -EINVAL;
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}
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switch (llccpmu->ver) {
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case LLCC_PMU_VER1:
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value = readl_relaxed(MON_CNT(llccpmu, cpu));
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break;
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case LLCC_PMU_VER2:
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value = readl_relaxed(MON_CNT(llccpmu, cpu));
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break;
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}
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return value;
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}
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static int qcom_llcc_event_init(struct perf_event *event)
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{
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@ -58,17 +153,26 @@ static void qcom_llcc_event_read(struct perf_event *event)
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ktime_t cur;
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raw_spin_lock_irqsave(&counter_lock, irq_flags);
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cur = ktime_get();
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if (ktime_ms_delta(cur, last_read) > 1) {
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writel_relaxed(DISABLE, MON_CFG(llccpmu));
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for (i = 0; i < NUM_COUNTERS; i++) {
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raw = readl_relaxed(MON_CNT(llccpmu, i));
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raw &= VALUE_MASK;
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llcc_stats[i] += (u64) raw << SCALING_FACTOR;
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if (llccpmu->ver == LLCC_PMU_VER1) {
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cur = ktime_get();
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if (ktime_ms_delta(cur, last_read) > 1) {
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mon_disable(llccpmu, cpu);
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for (i = 0; i < NUM_COUNTERS; i++) {
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raw = read_cnt(llccpmu, i);
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raw &= VALUE_MASK;
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llcc_stats[i] += (u64) raw << SCALING_FACTOR;
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}
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last_read = cur;
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mon_clear(llccpmu, cpu);
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mon_enable(llccpmu, cpu);
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}
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last_read = cur;
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writel_relaxed(CLEAR, MON_CFG(llccpmu));
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writel_relaxed(ENABLE, MON_CFG(llccpmu));
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} else {
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mon_disable(llccpmu, cpu);
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raw = read_cnt(llccpmu, cpu);
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raw &= VALUE_MASK;
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llcc_stats[cpu] += (u64) raw << SCALING_FACTOR;
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mon_clear(llccpmu, cpu);
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mon_enable(llccpmu, cpu);
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}
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if (!(event->hw.state & PERF_HES_STOPPED))
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@ -92,11 +196,22 @@ static void qcom_llcc_event_stop(struct perf_event *event, int flags)
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static int qcom_llcc_event_add(struct perf_event *event, int flags)
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{
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struct llcc_pmu *llccpmu = to_llcc_pmu(event->pmu);
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unsigned int cpu_users;
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raw_spin_lock(&users_lock);
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if (!users)
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writel_relaxed(ENABLE, MON_CFG(llccpmu));
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users++;
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if (llccpmu->ver == LLCC_PMU_VER1) {
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if (!users)
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mon_enable(llccpmu, event->cpu);
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users++;
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} else {
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cpu_users = per_cpu(users_alive, event->cpu);
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if (!cpu_users)
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mon_enable(llccpmu, event->cpu);
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cpu_users++;
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per_cpu(users_alive, event->cpu) = cpu_users;
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}
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raw_spin_unlock(&users_lock);
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event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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@ -110,11 +225,22 @@ static int qcom_llcc_event_add(struct perf_event *event, int flags)
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static void qcom_llcc_event_del(struct perf_event *event, int flags)
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{
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struct llcc_pmu *llccpmu = to_llcc_pmu(event->pmu);
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unsigned int cpu_users;
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raw_spin_lock(&users_lock);
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users--;
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if (!users)
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writel_relaxed(DISABLE, MON_CFG(llccpmu));
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if (llccpmu->ver == LLCC_PMU_VER1) {
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users--;
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if (!users)
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mon_disable(llccpmu, event->cpu);
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} else {
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cpu_users = per_cpu(users_alive, event->cpu);
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cpu_users--;
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if (!cpu_users)
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mon_disable(llccpmu, event->cpu);
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per_cpu(users_alive, event->cpu) = cpu_users;
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}
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raw_spin_unlock(&users_lock);
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}
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@ -128,6 +254,13 @@ static int qcom_llcc_pmu_probe(struct platform_device *pdev)
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if (!llccpmu)
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return -ENOMEM;
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llccpmu->ver = (enum llcc_pmu_version)
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of_device_get_match_data(&pdev->dev);
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if (!llccpmu->ver) {
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pr_err("Unknown device type!\n");
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return -ENODEV;
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}
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llccpmu->pmu = (struct pmu) {
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.task_ctx_nr = perf_invalid_context,
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@ -161,7 +294,8 @@ static int qcom_llcc_pmu_probe(struct platform_device *pdev)
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}
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static const struct of_device_id qcom_llcc_pmu_match_table[] = {
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{ .compatible = "qcom,qcom-llcc-pmu" },
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{ .compatible = "qcom,llcc-pmu-ver1", .data = (void *) LLCC_PMU_VER1 },
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{ .compatible = "qcom,llcc-pmu-ver2", .data = (void *) LLCC_PMU_VER2 },
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{}
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};
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