Merge "disp: msm: sde: Fix 32-bit compilation issues"
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commit
c096bfcf2a
@ -847,8 +847,8 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
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bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
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} else if (config->panel_mode == DSI_OP_CMD_MODE) {
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/* Calculate the bit rate needed to match dsi transfer time */
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bit_rate = mult_frac(min_dsi_clk_hz, frame_time_us,
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dsi_transfer_time_us);
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bit_rate = min_dsi_clk_hz * frame_time_us;
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do_div(bit_rate, dsi_transfer_time_us);
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bit_rate = bit_rate * num_of_lanes;
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} else {
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h_period = DSI_H_TOTAL_DSC(timing);
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@ -2492,6 +2492,7 @@ static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode,
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u32 len, i;
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int rc = 0;
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struct dsi_display_mode_priv_info *priv_info;
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u64 pixel_clk_khz;
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if (!mode || !mode->priv_info)
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return -EINVAL;
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@ -2520,9 +2521,11 @@ static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode,
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* function dsi_panel_calc_dsi_transfer_time( )
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* as we set it based on dsi clock or mdp transfer time.
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*/
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mode->pixel_clk_khz = (DSI_H_TOTAL_DSC(&mode->timing) *
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pixel_clk_khz = (DSI_H_TOTAL_DSC(&mode->timing) *
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DSI_V_TOTAL(&mode->timing) *
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mode->timing.refresh_rate) / 1000;
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mode->timing.refresh_rate);
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do_div(pixel_clk_khz, 1000);
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mode->pixel_clk_khz = pixel_clk_khz;
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}
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return rc;
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@ -3571,7 +3574,8 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config,
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struct dsi_display_mode *mode, u32 frame_threshold_us)
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{
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u32 frame_time_us,nslices;
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u64 min_bitclk_hz, total_active_pixels, bits_per_line, pclk_rate_hz;
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u64 min_bitclk_hz, total_active_pixels, bits_per_line, pclk_rate_hz,
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dsi_transfer_time_us, pixel_clk_khz;
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struct msm_display_dsc_info *dsc = mode->timing.dsc;
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struct dsi_mode_info *timing = &mode->timing;
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struct dsi_display_mode *display_mode;
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@ -3606,15 +3610,18 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config,
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* timing->v_active));
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/* calculate the actual bitclk needed to transfer the frame */
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min_bitclk_hz = (total_active_pixels * (timing->refresh_rate) *
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(config->bpp)) / (config->num_data_lanes);
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(config->bpp));
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do_div(min_bitclk_hz, config->num_data_lanes);
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}
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timing->min_dsi_clk_hz = min_bitclk_hz;
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if (timing->clk_rate_hz) {
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/* adjust the transfer time proportionately for bit clk*/
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timing->dsi_transfer_time_us = mult_frac(frame_time_us,
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min_bitclk_hz, timing->clk_rate_hz);
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dsi_transfer_time_us = frame_time_us * min_bitclk_hz;
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do_div(dsi_transfer_time_us, timing->clk_rate_hz);
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timing->dsi_transfer_time_us = dsi_transfer_time_us;
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} else if (mode->priv_info->mdp_transfer_time_us) {
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timing->dsi_transfer_time_us =
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mode->priv_info->mdp_transfer_time_us;
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@ -3656,13 +3663,14 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config,
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}
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/* Calculate pclk_khz to update modeinfo */
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pclk_rate_hz = mult_frac(min_bitclk_hz, frame_time_us,
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timing->dsi_transfer_time_us);
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pclk_rate_hz = min_bitclk_hz * frame_time_us;
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do_div(pclk_rate_hz, timing->dsi_transfer_time_us);
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display_mode->pixel_clk_khz = mult_frac(pclk_rate_hz,
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config->num_data_lanes, config->bpp);
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pixel_clk_khz = pclk_rate_hz * config->num_data_lanes;
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do_div(pixel_clk_khz, config->bpp);
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display_mode->pixel_clk_khz = pixel_clk_khz;
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do_div(display_mode->pixel_clk_khz, 1000);
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display_mode->pixel_clk_khz = display_mode->pixel_clk_khz / 1000;
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}
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@ -26,7 +26,7 @@ int32_t dsi_phy_hw_v4_0_calc_clk_zero(s64 rec_temp1, s64 mult)
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s64 rec_temp2, rec_temp3;
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rec_temp2 = rec_temp1;
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rec_temp3 = roundup(div_s64(rec_temp2, 8), mult);
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rec_temp3 = roundup64(div_s64(rec_temp2, 8), mult);
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return (div_s64(rec_temp3, mult) - 1);
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}
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@ -37,7 +37,7 @@ int32_t dsi_phy_hw_v4_0_calc_clk_trail_rec_min(s64 temp_mul,
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rec_temp1 = temp_mul;
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rec_temp2 = div_s64(rec_temp1, 8);
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rec_temp3 = roundup(rec_temp2, mult);
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rec_temp3 = roundup64(rec_temp2, mult);
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return (div_s64(rec_temp3, mult) - 1);
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}
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@ -53,7 +53,7 @@ int32_t dsi_phy_hw_v4_0_calc_hs_zero(s64 temp1, s64 mult)
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{
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s64 rec_temp2, rec_min;
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rec_temp2 = roundup((temp1 / 8), mult);
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rec_temp2 = roundup64((temp1 / 8), mult);
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rec_min = rec_temp2 - (1 * mult);
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return div_s64(rec_min, mult);
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}
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@ -451,7 +451,7 @@ static int msm_smmu_probe(struct platform_device *pdev)
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client->dev->dma_parms = devm_kzalloc(client->dev,
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sizeof(*client->dev->dma_parms), GFP_KERNEL);
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dma_set_max_seg_size(client->dev, DMA_BIT_MASK(32));
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dma_set_seg_boundary(client->dev, DMA_BIT_MASK(64));
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dma_set_seg_boundary(client->dev, (unsigned long)DMA_BIT_MASK(64));
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iommu_set_fault_handler(client->domain,
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msm_smmu_fault_handler, (void *)client);
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@ -276,7 +276,7 @@ static ssize_t measured_fps_show(struct device *device,
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{
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struct drm_crtc *crtc;
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struct sde_crtc *sde_crtc;
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unsigned int fps_int, fps_decimal;
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uint64_t fps_int, fps_decimal;
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u64 fps = 0, frame_count = 0;
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ktime_t current_time;
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int i = 0, current_time_index;
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@ -353,7 +353,7 @@ static ssize_t measured_fps_show(struct device *device,
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}
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}
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fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
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fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
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fps_decimal = do_div(fps_int, 10);
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return scnprintf(buf, PAGE_SIZE,
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"fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal,
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@ -14,8 +14,8 @@
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#define SDE_POWER_HANDLE_ENABLE_NRT_BUS_IB_QUOTA 0
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#define SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0
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#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA 3000000000
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#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA 3000000000
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#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA 3000000000ULL
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#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA 3000000000ULL
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#include <linux/sde_io_util.h>
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#include <soc/qcom/cx_ipeak.h>
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@ -23,8 +23,8 @@ struct lpfr_cfg {
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struct dsi_pll_vco_clk {
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struct clk_hw hw;
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unsigned long ref_clk_rate;
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unsigned long min_rate;
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unsigned long max_rate;
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u64 min_rate;
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u64 max_rate;
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u32 pll_en_seq_cnt;
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struct lpfr_cfg *lpfr_lut;
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u32 lpfr_lut_size;
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@ -1062,10 +1062,11 @@ long pll_vco_round_rate_14nm(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long rrate = rate;
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u32 div;
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u64 div;
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struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
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div = vco->min_rate / rate;
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div = vco->min_rate;
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do_div(div, rate);
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if (div > 15) {
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/* rate < 86.67 Mhz */
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pr_err("rate=%lu NOT supportted\n", rate);
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@ -576,11 +576,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll,
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break;
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case MDSS_DSI_PLL_7NM_V4_1:
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default:
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if (pll_freq <= 1000000000)
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if (pll_freq <= 1000000000ULL)
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regs->pll_clock_inverters = 0xA0;
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else if (pll_freq <= 2500000000)
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else if (pll_freq <= 2500000000ULL)
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regs->pll_clock_inverters = 0x20;
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else if (pll_freq <= 3020000000)
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else if (pll_freq <= 3020000000ULL)
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regs->pll_clock_inverters = 0x00;
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else
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regs->pll_clock_inverters = 0x40;
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@ -680,16 +680,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll,
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break;
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case MDSS_DSI_PLL_7NM_V4_1:
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default:
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if (vco_rate < 3100000000)
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if (vco_rate < 3100000000ULL)
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MDSS_PLL_REG_W(pll_base,
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PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
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else
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MDSS_PLL_REG_W(pll_base,
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PLL_ANALOG_CONTROLS_FIVE_1, 0x03);
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if (vco_rate < 1520000000)
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if (vco_rate < 1520000000ULL)
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MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08);
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else if (vco_rate < 2990000000)
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else if (vco_rate < 2990000000ULL)
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MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01);
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else
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MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);
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@ -617,7 +617,7 @@ int sde_smmu_probe(struct platform_device *pdev)
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sizeof(*dev->dma_parms), GFP_KERNEL);
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dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
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dma_set_seg_boundary(dev, DMA_BIT_MASK(64));
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dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64));
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iommu_set_fault_handler(sde_smmu->rot_domain,
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sde_smmu_fault_handler, (void *)sde_smmu);
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