asoc: afe: Add afe dyn mclk kcontrol
Add afe dyn mclk kcontrol to support change external clk. Change-Id: I90f0a4a6a350ec261f216aa53bfa2f7306987bc1 Signed-off-by: Jing Wang <quic_jingwa@quicinc.com>
This commit is contained in:
Jing Wang
parent
3f10f8fe5f
commit
c11441a914
@ -481,6 +481,8 @@ static bool afe_port_logging_item[IDX_TDM_MAX];
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static int afe_port_loggging_control_added;
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static int afe_dyn_mclk_control_added;
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static DEFINE_MUTEX(tdm_mutex);
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static atomic_t tdm_group_ref[IDX_GROUP_TDM_MAX];
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@ -522,6 +524,51 @@ static struct afe_clk_set tdm_clk_set = {
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0,
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};
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static int clk_id_index;
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static int clk_root_index;
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static int clk_attri_index;
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static int global_dyn_mclk_cfg_portid;
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struct afe_param_id_clock_set_v2_t global_dyn_mclk_cfg = {
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.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION,
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.clk_id = Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT,
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.clk_freq_in_hz = 12288000,
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.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
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.clk_root = Q6AFE_LPASS_MCLK_IN0,
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.divider_2x = AFE_CLOCK_DEFAULT_INTEGER_DIVIDER,
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.m = AFE_CLOCK_DEFAULT_M_VALUE,
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.n = AFE_CLOCK_DEFAULT_N_VALUE,
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.d = AFE_CLOCK_DEFAULT_D_VALUE,
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.enable = 0,
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};
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static int afe_dyn_clk_root_enum[] = {
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Q6AFE_LPASS_MCLK_IN0,
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Q6AFE_LPASS_MCLK_IN1,
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};
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static int afe_dyn_clk_attri_enum[] = {
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Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
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Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND,
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Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR,
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};
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static int afe_dyn_clk_id_enum[] = {
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Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
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Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
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Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
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Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT, Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
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Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT, Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT,
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Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR,
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Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT, Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT,
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Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT, Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT,
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Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT, Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT,
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Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT, Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT,
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Q6AFE_LPASS_CLK_ID_MCLK_1, Q6AFE_LPASS_CLK_ID_MCLK_2,
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Q6AFE_LPASS_CLK_ID_MCLK_3, Q6AFE_LPASS_CLK_ID_MCLK_4,
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Q6AFE_LPASS_CLK_ID_MCLK_5, Q6AFE_LPASS_CLK_ID_AHB_HDMI_INPUT,
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Q6AFE_LPASS_CLK_ID_SPDIF_CORE
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};
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static int msm_dai_q6_get_tdm_clk_ref(u16 id)
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{
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switch (id) {
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@ -10371,14 +10418,168 @@ static int msm_pcm_add_afe_port_logging_control(struct snd_soc_dai *dai)
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return rc;
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}
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static int get_global_clk_root(int value)
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{
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if ((value < 0) || (value > ARRAY_SIZE(afe_dyn_clk_root_enum) - 1)) {
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pr_err("%s, %d set clk_root range failed\n", __func__, __LINE__);
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return global_dyn_mclk_cfg.clk_root;
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}
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clk_root_index = value;
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return afe_dyn_clk_root_enum[clk_root_index];
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}
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static int get_global_clk_attri(int value)
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{
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if ((value < 0) || (value > ARRAY_SIZE(afe_dyn_clk_attri_enum) - 1)) {
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pr_err("%s, %d set clk_attri range failed\n", __func__, __LINE__);
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return global_dyn_mclk_cfg.clk_attri;
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}
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clk_attri_index = value;
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return afe_dyn_clk_attri_enum[clk_attri_index];
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}
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static int get_global_clk_id(int value)
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{
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if ((value < 0) || (value > ARRAY_SIZE(afe_dyn_clk_id_enum) - 1)) {
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pr_err("%s, %d set clk_id range failed\n", __func__, __LINE__);
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return global_dyn_mclk_cfg.clk_id;
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}
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clk_id_index = value;
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return afe_dyn_clk_id_enum[clk_id_index];
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}
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static int msm_pcm_afe_dyn_mclk_ctl_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *ucontrol)
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{
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ucontrol->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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/* 11 int values:clk_set_minor_version, clk_id, clk_freq_in_hz, clk_attri,
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* clk_root, enable, divider_2x, m, n, d
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*/
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ucontrol->count = 11;
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ucontrol->value.integer.min = 0;
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ucontrol->value.integer.max = INT_MAX;
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/* Valid range is all positive values to support above controls */
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pr_debug("%s,%d\n", __func__, __LINE__);
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return 0;
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}
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static int msm_pcm_afe_dyn_mclk_ctl_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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ucontrol->value.integer.value[0] = global_dyn_mclk_cfg_portid;
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ucontrol->value.integer.value[1] = clk_id_index;
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ucontrol->value.integer.value[2] = global_dyn_mclk_cfg.clk_freq_in_hz;
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ucontrol->value.integer.value[3] = clk_attri_index;
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ucontrol->value.integer.value[4] = clk_root_index;
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ucontrol->value.integer.value[5] = global_dyn_mclk_cfg.enable;
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ucontrol->value.integer.value[6] = global_dyn_mclk_cfg.divider_2x;
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ucontrol->value.integer.value[7] = global_dyn_mclk_cfg.m;
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ucontrol->value.integer.value[8] = global_dyn_mclk_cfg.n;
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ucontrol->value.integer.value[9] = global_dyn_mclk_cfg.d;
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ucontrol->value.integer.value[10] = global_dyn_mclk_cfg.clk_set_minor_version;
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pr_debug("%s:%d.... portid:%d, clk_id:%d, clk_freq_in_hz:%d, clk_attri:%d, clk_root:%d, enable:%d, divider_2x:%d, m:%d, n:%d, d:%d, version:%d\n",
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__func__, __LINE__, global_dyn_mclk_cfg_portid, global_dyn_mclk_cfg.clk_id,
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global_dyn_mclk_cfg.clk_freq_in_hz, global_dyn_mclk_cfg.clk_attri,
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global_dyn_mclk_cfg.clk_root, global_dyn_mclk_cfg.enable,
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global_dyn_mclk_cfg.divider_2x, global_dyn_mclk_cfg.m, global_dyn_mclk_cfg.n,
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global_dyn_mclk_cfg.d, global_dyn_mclk_cfg.clk_set_minor_version);
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return 0;
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}
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static int msm_pcm_afe_dyn_mclk_ctl_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int ret = -EINVAL;
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pr_debug("%s: enter\n", __func__);
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global_dyn_mclk_cfg_portid = ucontrol->value.integer.value[0];
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global_dyn_mclk_cfg.clk_id = get_global_clk_id(ucontrol->value.integer.value[1]);
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if (ucontrol->value.integer.value[2] >= 0)
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global_dyn_mclk_cfg.clk_freq_in_hz = ucontrol->value.integer.value[2];
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global_dyn_mclk_cfg.clk_attri = get_global_clk_attri(ucontrol->value.integer.value[3]);
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global_dyn_mclk_cfg.clk_root = get_global_clk_root(ucontrol->value.integer.value[4]);
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if ((ucontrol->value.integer.value[5] <= 1) && (ucontrol->value.integer.value[5] >= 0))
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global_dyn_mclk_cfg.enable = ucontrol->value.integer.value[5];
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global_dyn_mclk_cfg.divider_2x = ucontrol->value.integer.value[6];
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global_dyn_mclk_cfg.m = ucontrol->value.integer.value[7];
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global_dyn_mclk_cfg.n = ucontrol->value.integer.value[8];
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global_dyn_mclk_cfg.d = ucontrol->value.integer.value[9];
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pr_debug("%s:%d.... portid:%d, clk_id_index:%d, clk_freq_in_hz:%d, clk_attri_index:%d, clk_root_index:%d, enable:%d, divider_2x:%d, m:%d, n:%d, d:%d, version:%d\n",
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__func__, __LINE__, ucontrol->value.integer.value[0],
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ucontrol->value.integer.value[1],
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ucontrol->value.integer.value[2], ucontrol->value.integer.value[3],
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ucontrol->value.integer.value[4], ucontrol->value.integer.value[5],
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ucontrol->value.integer.value[6], ucontrol->value.integer.value[7],
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ucontrol->value.integer.value[8], ucontrol->value.integer.value[9]);
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ret = afe_set_lpass_clk_cfg_ext_mclk_v2(global_dyn_mclk_cfg_portid,
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&global_dyn_mclk_cfg, 0);
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if (ret)
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pr_err("%s: AFE port logging setting for port 0x%x failed %d\n",
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__func__, global_dyn_mclk_cfg_portid, ret);
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return ret;
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}
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static int msm_pcm_add_afe_dyn_mclk_control(struct snd_soc_dai *dai)
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{
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int rc = 0;
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struct snd_kcontrol_new *knew = NULL;
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struct snd_kcontrol *kctl = NULL;
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const char *afe_dyn_mclk_ctl_name = "AFE_dyn_switch_mclk_source";
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/* Add AFE port logging controls */
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knew = kzalloc(sizeof(struct snd_kcontrol_new), GFP_KERNEL);
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if (!knew)
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return -ENOMEM;
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knew->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
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knew->info = msm_pcm_afe_dyn_mclk_ctl_info;
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knew->get = msm_pcm_afe_dyn_mclk_ctl_get;
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knew->put = msm_pcm_afe_dyn_mclk_ctl_put;
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knew->name = afe_dyn_mclk_ctl_name;
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knew->private_value = dai->id;
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kctl = snd_ctl_new1(knew, knew);
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if (!kctl) {
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kfree(knew);
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return -ENOMEM;
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}
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rc = snd_ctl_add(dai->component->card->snd_card, kctl);
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if (rc < 0)
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pr_err("%s: err add AFE dyn mclk control, DAI = %s\n",
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__func__, dai->name);
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return rc;
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}
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int jitter_cleaner_afe_enable_mclk_and_get_info_cb_func(void *private_data,
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uint32_t enable, uint32_t mclk_freq,
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struct afe_param_id_clock_set_v2_t *dyn_mclk_cfg)
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{
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pr_debug("%s,%d\n", __func__, __LINE__);
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return 0;
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}
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static int msm_dai_q6_dai_tdm_probe(struct snd_soc_dai *dai)
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{
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int rc = 0;
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int port_idx = 0;
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struct msm_dai_q6_tdm_dai_data *tdm_dai_data = NULL;
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struct snd_kcontrol *data_format_kcontrol = NULL;
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struct snd_kcontrol *header_type_kcontrol = NULL;
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struct snd_kcontrol *header_kcontrol = NULL;
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int port_idx = 0;
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const struct snd_kcontrol_new *data_format_ctrl = NULL;
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const struct snd_kcontrol_new *header_type_ctrl = NULL;
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const struct snd_kcontrol_new *header_ctrl = NULL;
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@ -10459,6 +10660,26 @@ static int msm_dai_q6_dai_tdm_probe(struct snd_soc_dai *dai)
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afe_port_loggging_control_added = 1;
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}
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/* add AFE dyn mclk controls */
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if (!afe_dyn_mclk_control_added) {
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rc = msm_pcm_add_afe_dyn_mclk_control(dai);
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if (rc < 0) {
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dev_err(dai->dev, "%s: add AFE dyn mclk control failed DAI: %s\n",
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__func__, dai->name);
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goto rtn;
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}
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afe_dyn_mclk_control_added = 1;
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rc = afe_register_ext_mclk_cb(jitter_cleaner_afe_enable_mclk_and_get_info_cb_func,
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(void *)&global_dyn_mclk_cfg);
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if (rc < 0) {
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dev_err(dai->dev, "%s: add AFE afe_register_ext_mclk_cb failed : %s\n",
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__func__, dai->name);
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goto rtn;
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}
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}
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if (tdm_dai_data->is_island_dai)
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rc = msm_dai_q6_add_island_mx_ctls(
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dai->component->card->snd_card,
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79
dsp/q6afe.c
79
dsp/q6afe.c
@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/slab.h>
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#include <linux/debugfs.h>
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@ -9792,7 +9793,6 @@ static int afe_set_lpass_clk_cfg_ext_mclk(int index, struct afe_clk_set *cfg,
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dyn_mclk_cfg.clk_id = cfg->clk_id;
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dyn_mclk_cfg.clk_attri = cfg->clk_attri;
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dyn_mclk_cfg.enable = cfg->enable;
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pr_debug("%s: Minor version =0x%x clk id = %d\n", __func__,
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dyn_mclk_cfg.clk_set_minor_version, dyn_mclk_cfg.clk_id);
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pr_debug("%s: clk freq (Hz) = %d, clk attri = 0x%x\n", __func__,
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@ -9831,6 +9831,83 @@ stop_mclk:
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return ret;
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}
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int afe_set_lpass_clk_cfg_ext_mclk_v2(int index, struct afe_param_id_clock_set_v2_t *dyn_mclk_cfg,
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uint32_t mclk_freq)
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{
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struct param_hdr_v3 param_hdr;
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int ret = 0;
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if (!dyn_mclk_cfg) {
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pr_err("%s: clock cfg is NULL\n", __func__);
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ret = -EINVAL;
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return ret;
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}
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if (index < 0 || index >= AFE_MAX_PORTS) {
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pr_err("%s: index[%d] invalid!\n", __func__, index);
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return -EINVAL;
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}
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memset(¶m_hdr, 0, sizeof(param_hdr));
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param_hdr.module_id = AFE_MODULE_CLOCK_SET;
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param_hdr.instance_id = INSTANCE_ID_0;
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param_hdr.param_id = AFE_PARAM_ID_CLOCK_SET_V2;
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param_hdr.param_size = sizeof(struct afe_param_id_clock_set_v2_t);
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if (afe_ext_mclk.ext_mclk_cb) {
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ret = afe_ext_mclk.ext_mclk_cb(afe_ext_mclk.private_data,
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dyn_mclk_cfg->enable, mclk_freq, dyn_mclk_cfg);
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if (ret) {
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pr_err_ratelimited("%s: get mclk cfg failed %d\n",
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__func__, ret);
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return ret;
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}
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} else {
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pr_err_ratelimited("%s: mclk callback not registered\n", __func__);
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return -EINVAL;
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}
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dyn_mclk_cfg->clk_set_minor_version = 1;
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pr_debug("%s: Minor version =0x%x clk id = %d\n", __func__,
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dyn_mclk_cfg->clk_set_minor_version, dyn_mclk_cfg->clk_id);
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pr_debug("%s: clk freq (Hz) = %d, clk attri = 0x%x\n", __func__,
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dyn_mclk_cfg->clk_freq_in_hz, dyn_mclk_cfg->clk_attri);
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pr_debug("%s: clk root = 0x%x clk enable = 0x%x\n", __func__,
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dyn_mclk_cfg->clk_root, dyn_mclk_cfg->enable);
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pr_debug("%s: divider_2x =%d m = %d n = %d, d =%d\n", __func__,
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dyn_mclk_cfg->divider_2x, dyn_mclk_cfg->m, dyn_mclk_cfg->n,
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dyn_mclk_cfg->d);
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ret = afe_q6_interface_prepare();
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if (ret != 0) {
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pr_err_ratelimited("%s: Q6 interface prepare failed %d\n",
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__func__, ret);
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goto stop_mclk;
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}
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mutex_lock(&this_afe.afe_cmd_lock);
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ret = q6afe_svc_pack_and_set_param_in_band(index, param_hdr,
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(u8 *) dyn_mclk_cfg);
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if (ret < 0)
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pr_err_ratelimited("%s: ext MCLK clk cfg failed with ret %d\n",
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__func__, ret);
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mutex_unlock(&this_afe.afe_cmd_lock);
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if (ret >= 0)
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return ret;
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stop_mclk:
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if (afe_ext_mclk.ext_mclk_cb && dyn_mclk_cfg->enable) {
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afe_ext_mclk.ext_mclk_cb(afe_ext_mclk.private_data,
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dyn_mclk_cfg->enable, mclk_freq, dyn_mclk_cfg);
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}
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return ret;
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}
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EXPORT_SYMBOL(afe_set_lpass_clk_cfg_ext_mclk_v2);
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/**
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* afe_set_lpass_clk_cfg - Set AFE clk config
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*
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
|
||||
@ -12209,6 +12210,9 @@ struct afe_param_id_clip_bank_sel {
|
||||
/* Supported LPASS CLK root*/
|
||||
#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
|
||||
|
||||
#define Q6AFE_LPASS_MCLK_IN0 1
|
||||
#define Q6AFE_LPASS_MCLK_IN1 2
|
||||
|
||||
enum afe_lpass_clk_mode {
|
||||
Q6AFE_LPASS_MODE_BOTH_INVALID,
|
||||
Q6AFE_LPASS_MODE_CLK1_VALID,
|
||||
@ -12362,6 +12366,8 @@ enum afe_lpass_clk_mode {
|
||||
/* Clock ID for AHB HDMI input */
|
||||
#define Q6AFE_LPASS_CLK_ID_AHB_HDMI_INPUT 0x400
|
||||
|
||||
#define Q6AFE_LPASS_CLK_ID_SPDIF_CORE 0x000
|
||||
|
||||
/* Clock ID for the primary SPDIF output core. */
|
||||
#define AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE 0x500
|
||||
/* Clock ID for the secondary SPDIF output core. */
|
||||
@ -12448,6 +12454,12 @@ struct afe_clk_set {
|
||||
|
||||
#define AFE_PARAM_ID_CLOCK_SET_V2 0x000102E6
|
||||
|
||||
#define AFE_CLOCK_SET_CLOCK_ROOT_DEFAULT 0x2
|
||||
#define AFE_CLOCK_DEFAULT_INTEGER_DIVIDER 0x0
|
||||
#define AFE_CLOCK_DEFAULT_M_VALUE 0x1
|
||||
#define AFE_CLOCK_DEFAULT_N_VALUE 0x2
|
||||
#define AFE_CLOCK_DEFAULT_D_VALUE 0x1
|
||||
|
||||
#define AFE_API_VERSION_CLOCK_SET_V2 0x1
|
||||
|
||||
struct afe_param_id_clock_set_v2_t {
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __Q6AFE_V2_H__
|
||||
#define __Q6AFE_V2_H__
|
||||
@ -592,6 +593,8 @@ int afe_port_send_logging_cfg(u16 port_id,
|
||||
struct afe_param_id_port_data_log_disable_t *log_disable);
|
||||
int afe_get_av_dev_drift(struct afe_param_id_dev_timing_stats *timing_stats,
|
||||
u16 port);
|
||||
int afe_set_lpass_clk_cfg_ext_mclk_v2(int index,
|
||||
struct afe_param_id_clock_set_v2_t *dyn_mclk_cfg, uint32_t mclk_freq);
|
||||
int afe_get_sp_rx_tmax_xmax_logging_data(
|
||||
struct afe_sp_rx_tmax_xmax_logging_param *xt_logging,
|
||||
u16 port_id);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user