msm: kgsl: Make coresight optional
Make coresight support conditional on a new Kconfig option. Support this by moving the code around a bit and out of the generic headers to make possible to omit the coresight code when the support isn't available. This allows us to omit coresight when CONFIG_CORESIGHT isn't enabled and optionally to remove it at the KGSL level too. Change-Id: Ic0dedbad2a55df4acf1b8c6e15e5b1b39f08a832 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This commit is contained in:
parent
7a6368ee0b
commit
c1cc28e662
@ -13,3 +13,11 @@ config QCOM_ADRENO_DEFAULT_GOVERNOR
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string "devfreq governor for the adreno core"
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default "simple_ondemand"
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depends on QCOM_KGSL
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config QCOM_KGSL_CORESIGHT
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bool "Enable coresight support for the Adreno GPU"
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depends on QCOM_KGSL && CORESIGHT
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help
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When enabled, the Adreno GPU is available as a source for Coresight
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data. On a6xx targets there are two sources available for the GX and
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CX domains respectively. Debug kernels should say 'Y' here.
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@ -37,7 +37,6 @@ msm_kgsl-y += \
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adreno_a6xx_preempt.o \
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adreno_a6xx_rgmu.o \
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adreno_a6xx_snapshot.o \
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adreno_coresight.o \
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adreno_cp_parser.o \
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adreno_dispatch.o \
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adreno_drawctxt.o \
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@ -49,5 +48,6 @@ msm_kgsl-y += \
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adreno_trace.o
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msm_kgsl-$(CONFIG_COMPAT) += adreno_compat.o
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msm_kgsl-$(CONFIG_QCOM_KGSL_CORESIGHT) += adreno_coresight.o
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msm_kgsl-$(CONFIG_DEBUG_FS) += adreno_debugfs.o adreno_profile.o
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msm_kgsl-$(CONFIG_ARM_SMMU) += adreno_iommu.o
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@ -5,6 +5,7 @@
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#ifndef __ADRENO_H
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#define __ADRENO_H
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#include "adreno_coresight.h"
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#include "adreno_dispatch.h"
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#include "adreno_drawctxt.h"
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#include "adreno_perfcounter.h"
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@ -364,12 +365,6 @@ struct adreno_gpu_core {
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u32 bus_width;
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};
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enum gpu_coresight_sources {
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GPU_CORESIGHT_GX = 0,
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GPU_CORESIGHT_CX = 1,
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GPU_CORESIGHT_MAX,
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};
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/**
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* struct adreno_device - The mothership structure for all adreno related info
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* @dev: Reference to struct kgsl_device
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@ -520,7 +515,7 @@ struct adreno_device {
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unsigned int highest_bank_bit;
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unsigned int quirks;
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struct coresight_device *csdev[GPU_CORESIGHT_MAX];
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struct coresight_device *csdev[2];
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uint32_t gpmu_throttle_counters[ADRENO_GPMU_THROTTLE_COUNTERS];
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struct work_struct irq_storm_work;
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@ -733,53 +728,6 @@ struct adreno_vbif_snapshot_registers {
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const int count;
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};
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/**
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* struct adreno_coresight_register - Definition for a coresight (tracebus)
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* debug register
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* @offset: Offset of the debug register in the KGSL mmio region
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* @initial: Default value to write when coresight is enabled
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* @value: Current shadow value of the register (to be reprogrammed after power
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* collapse)
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*/
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struct adreno_coresight_register {
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unsigned int offset;
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unsigned int initial;
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unsigned int value;
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};
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struct adreno_coresight_attr {
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struct device_attribute attr;
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struct adreno_coresight_register *reg;
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};
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ssize_t adreno_coresight_show_register(struct device *device,
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struct device_attribute *attr, char *buf);
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ssize_t adreno_coresight_store_register(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t size);
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#define ADRENO_CORESIGHT_ATTR(_attrname, _reg) \
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struct adreno_coresight_attr coresight_attr_##_attrname = { \
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__ATTR(_attrname, 0644, \
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adreno_coresight_show_register, \
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adreno_coresight_store_register), \
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(_reg), }
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/**
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* struct adreno_coresight - GPU specific coresight definition
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* @registers - Array of GPU specific registers to configure trace bus output
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* @count - Number of registers in the array
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* @groups - Pointer to an attribute list of control files
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* @atid - The unique ATID value of the coresight device
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*/
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struct adreno_coresight {
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struct adreno_coresight_register *registers;
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unsigned int count;
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const struct attribute_group **groups;
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unsigned int atid;
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};
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struct adreno_irq_funcs {
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void (*func)(struct adreno_device *adreno_dev, int mask);
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};
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@ -819,7 +767,7 @@ struct adreno_gpudev {
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struct adreno_perfcounters *perfcounters;
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struct adreno_coresight *coresight[GPU_CORESIGHT_MAX];
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struct adreno_coresight *coresight[2];
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struct adreno_irq *irq;
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int num_prio_levels;
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@ -988,13 +936,6 @@ void adreno_fault_skipcmd_detached(struct adreno_device *adreno_dev,
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struct adreno_context *drawctxt,
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struct kgsl_drawobj *drawobj);
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void adreno_coresight_init(struct adreno_device *adreno_dev);
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void adreno_coresight_start(struct adreno_device *adreno_dev);
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void adreno_coresight_stop(struct adreno_device *adreno_dev);
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void adreno_coresight_remove(struct adreno_device *adreno_dev);
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bool adreno_hw_isidle(struct adreno_device *adreno_dev);
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void adreno_fault_detect_start(struct adreno_device *adreno_dev);
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@ -1142,6 +1142,7 @@ static void a3xx_start(struct adreno_device *adreno_dev)
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}
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#ifdef CONFIG_QCOM_KGSL_CORESIGHT
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static struct adreno_coresight_register a3xx_coresight_registers[] = {
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{ A3XX_RBBM_DEBUG_BUS_CTL, 0x0001093F },
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{ A3XX_RBBM_EXT_TRACE_STOP_CNT, 0x00017fff },
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@ -1191,6 +1192,7 @@ static struct adreno_coresight a3xx_coresight = {
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.count = ARRAY_SIZE(a3xx_coresight_registers),
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.groups = a3xx_coresight_groups,
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};
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#endif
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static unsigned int a3xx_int_bits[ADRENO_INT_BITS_MAX] = {
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ADRENO_INT_DEFINE(ADRENO_INT_RBBM_AHB_ERROR, A3XX_INT_RBBM_AHB_ERROR),
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@ -1445,6 +1447,8 @@ struct adreno_gpudev adreno_a3xx_gpudev = {
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.microcode_read = a3xx_microcode_read,
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.start = a3xx_start,
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.snapshot = a3xx_snapshot,
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#ifdef CONFIG_QCOM_KGSL_CORESIGHT
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.coresight = {&a3xx_coresight},
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#endif
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.clk_set_options = a3xx_clk_set_options,
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};
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@ -2857,6 +2857,7 @@ static struct adreno_irq a5xx_irq = {
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.mask = A5XX_INT_MASK,
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};
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#ifdef CONFIG_QCOM_KGSL_CORESIGHT
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static struct adreno_coresight_register a5xx_coresight_registers[] = {
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{ A5XX_RBBM_CFG_DBGBUS_SEL_A },
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{ A5XX_RBBM_CFG_DBGBUS_SEL_B },
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@ -3049,13 +3050,16 @@ static struct adreno_coresight a5xx_coresight = {
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.count = ARRAY_SIZE(a5xx_coresight_registers),
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.groups = a5xx_coresight_groups,
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};
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#endif
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struct adreno_gpudev adreno_a5xx_gpudev = {
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.reg_offsets = a5xx_register_offsets,
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.int_bits = a5xx_int_bits,
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.ft_perf_counters = a5xx_ft_perf_counters,
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.ft_perf_counters_count = ARRAY_SIZE(a5xx_ft_perf_counters),
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#ifdef CONFIG_QCOM_KGSL_CORESIGHT
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.coresight = {&a5xx_coresight},
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#endif
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.start = a5xx_start,
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.snapshot = a5xx_snapshot,
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.irq = &a5xx_irq,
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@ -1428,6 +1428,7 @@ static struct adreno_irq a6xx_irq = {
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.mask = A6XX_INT_MASK,
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};
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#ifdef CONFIG_QCOM_KGSL_CORESIGHT
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static struct adreno_coresight_register a6xx_coresight_regs[] = {
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{ A6XX_DBGC_CFG_DBGBUS_SEL_A },
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{ A6XX_DBGC_CFG_DBGBUS_SEL_B },
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@ -1841,6 +1842,7 @@ static struct adreno_coresight a6xx_coresight_cx = {
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.count = ARRAY_SIZE(a6xx_coresight_regs_cx),
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.groups = a6xx_coresight_groups_cx,
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};
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#endif
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static struct adreno_perfcount_register a6xx_perfcounters_cp[] = {
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{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_0_LO,
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@ -2614,6 +2616,8 @@ struct adreno_gpudev adreno_a6xx_gpudev = {
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.sptprac_is_on = a6xx_sptprac_is_on,
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.ccu_invalidate = a6xx_ccu_invalidate,
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.perfcounter_update = a6xx_perfcounter_update,
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#ifdef CONFIG_QCOM_KGSL_CORESIGHT
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.coresight = {&a6xx_coresight, &a6xx_coresight_cx},
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#endif
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.clk_set_options = a6xx_clk_set_options,
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};
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@ -9,6 +9,11 @@
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#include "adreno.h"
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enum gpu_coresight_sources {
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GPU_CORESIGHT_GX = 0,
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GPU_CORESIGHT_CX = 1,
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};
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#define TO_ADRENO_CORESIGHT_ATTR(_attr) \
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container_of(_attr, struct adreno_coresight_attr, attr)
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@ -129,18 +134,10 @@ out:
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return size;
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}
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/**
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* adreno_coresight_disable() - Generic function to disable coresight debugging
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* @csdev: Pointer to coresight's device struct
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*
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* This is a generic function to disable coresight debug bus on adreno
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* devices. This should be used in all cases of disabling
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* coresight debug bus for adreno devices. This function in turn calls
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* the adreno device specific function through the gpudev hook.
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* This function is registered as the coresight disable function
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* with coresight driver. It should only be called through coresight driver
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* as that would ensure that the necessary setup required to be done on
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* coresight driver's part is also done.
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/*
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* This is a generic function to disable coresight debug bus on Adreno
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* devices. This function in turn calls the device specific function
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* through the gpudev hook.
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*/
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static void adreno_coresight_disable(struct coresight_device *csdev,
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struct perf_event *event)
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@ -190,12 +187,6 @@ static void adreno_coresight_disable(struct coresight_device *csdev,
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mutex_unlock(&device->mutex);
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}
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/**
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* _adreno_coresight_get_and_clear(): Save the current value of coresight
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* registers and clear the registers subsequently. Clearing registers
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* has the effect of disabling coresight.
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* @adreno_dev: Pointer to adreno device struct
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*/
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static int _adreno_coresight_get_and_clear(struct adreno_device *adreno_dev,
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int cs_id)
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{
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@ -254,17 +245,7 @@ static int _adreno_coresight_set(struct adreno_device *adreno_dev, int cs_id)
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}
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return 0;
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}
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/**
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* adreno_coresight_enable() - Generic function to enable coresight debugging
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* @csdev: Pointer to coresight's device struct
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*
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* This is a generic function to enable coresight debug bus on adreno
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* devices. This should be used in all cases of enabling
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* coresight debug bus for adreno devices. This function is registered as the
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* coresight enable function with coresight driver. It should only be called
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* through coresight driver as that would ensure that the necessary setup
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* required to be done on coresight driver's part is also done.
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*/
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/* Generic function to enable coresight debug bus on adreno devices */
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static int adreno_coresight_enable(struct coresight_device *csdev,
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struct perf_event *event, u32 mode)
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{
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@ -321,51 +302,22 @@ static int adreno_coresight_enable(struct coresight_device *csdev,
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return ret;
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}
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/**
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* adreno_coresight_stop() - Reprogram coresight registers after power collapse
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* @adreno_dev: Pointer to the adreno device structure
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*
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* Cache the current coresight register values so they can be restored after
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* power collapse
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*/
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void adreno_coresight_stop(struct adreno_device *adreno_dev)
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{
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int i, adreno_dev_flag = -EINVAL;
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if (test_bit(ADRENO_DEVICE_CORESIGHT, &adreno_dev->priv))
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_adreno_coresight_get_and_clear(adreno_dev, GPU_CORESIGHT_GX);
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for (i = 0; i < GPU_CORESIGHT_MAX; ++i) {
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if (i == GPU_CORESIGHT_GX)
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adreno_dev_flag = ADRENO_DEVICE_CORESIGHT;
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else if (i == GPU_CORESIGHT_CX)
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adreno_dev_flag = ADRENO_DEVICE_CORESIGHT_CX;
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else
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return;
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if (test_bit(adreno_dev_flag, &adreno_dev->priv))
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_adreno_coresight_get_and_clear(adreno_dev, i);
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}
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if (test_bit(ADRENO_DEVICE_CORESIGHT_CX, &adreno_dev->priv))
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_adreno_coresight_get_and_clear(adreno_dev, GPU_CORESIGHT_CX);
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}
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/**
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* adreno_coresight_start() - Reprogram coresight registers after power collapse
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* @adreno_dev: Pointer to the adreno device structure
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*
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* Reprogram the cached values to the coresight registers on power up
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*/
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void adreno_coresight_start(struct adreno_device *adreno_dev)
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{
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int i, adreno_dev_flag = -EINVAL;
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if (test_bit(ADRENO_DEVICE_CORESIGHT, &adreno_dev->priv))
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_adreno_coresight_set(adreno_dev, GPU_CORESIGHT_GX);
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for (i = 0; i < GPU_CORESIGHT_MAX; ++i) {
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if (i == GPU_CORESIGHT_GX)
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adreno_dev_flag = ADRENO_DEVICE_CORESIGHT;
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else if (i == GPU_CORESIGHT_CX)
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adreno_dev_flag = ADRENO_DEVICE_CORESIGHT_CX;
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else
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return;
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if (test_bit(adreno_dev_flag, &adreno_dev->priv))
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_adreno_coresight_set(adreno_dev, i);
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}
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if (test_bit(ADRENO_DEVICE_CORESIGHT_CX, &adreno_dev->priv))
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_adreno_coresight_set(adreno_dev, GPU_CORESIGHT_CX);
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}
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static int adreno_coresight_trace_id(struct coresight_device *csdev)
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@ -396,12 +348,9 @@ void adreno_coresight_remove(struct adreno_device *adreno_dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(adreno_dev->csdev); i++) {
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if (!IS_ERR_OR_NULL(adreno_dev->csdev[i])) {
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for (i = 0; i < ARRAY_SIZE(adreno_dev->csdev); i++)
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if (!IS_ERR_OR_NULL(adreno_dev->csdev[i]))
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coresight_unregister(adreno_dev->csdev[i]);
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adreno_dev->csdev[i] = NULL;
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}
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}
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}
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static struct coresight_device *
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@ -437,7 +386,6 @@ adreno_coresight_dev_probe(struct kgsl_device *device,
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void adreno_coresight_init(struct adreno_device *adreno_dev)
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{
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int ret = 0;
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struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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int i = 0;
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@ -456,5 +404,4 @@ void adreno_coresight_init(struct adreno_device *adreno_dev)
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}
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of_node_put(node);
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return ret;
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}
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132
drivers/gpu/msm/adreno_coresight.h
Normal file
132
drivers/gpu/msm/adreno_coresight.h
Normal file
@ -0,0 +1,132 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ADRENO_CORESIGHT_H_
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#define _ADRENO_CORESIGHT_H_
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#include <linux/device.h>
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struct adreno_device;
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/**
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* struct adreno_coresight_register - Definition for a coresight (tracebus)
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* debug register
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*/
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struct adreno_coresight_register {
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/** @offset: Offset of the debug register in the KGSL register space */
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unsigned int offset;
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/** @initial: Default value to write when coresight is enabled */
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unsigned int initial;
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/**
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* @value: Current shadow value of the register (to be reprogrammed
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* after power collapse)
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*/
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unsigned int value;
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};
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/**
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* struct adreno_coresight_attr - Local attribute struct for coresight sysfs
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*
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* files
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*/
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struct adreno_coresight_attr {
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/** @attr: Base device attribute */
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struct device_attribute attr;
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/**
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* @reg: Pointer to the &struct adreno_coresight_register definition
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* for this register
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*/
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struct adreno_coresight_register *reg;
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};
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/**
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* adreno_coresight_show_register - Callback function for sysfs show
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* @device: Pointer to a device handle
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* @attr: Pointer to the device attribute
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* @buf: Contains the output buffer for sysfs
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*
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* Callback function to write the value of the register into the sysfs node.
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* Return: The size of the data written to the buffer or negative on error.
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*/
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ssize_t adreno_coresight_show_register(struct device *device,
|
||||
struct device_attribute *attr, char *buf);
|
||||
|
||||
/**
|
||||
* adreno_coresight_show_register - Callback function for sysfs store
|
||||
* @device: Pointer to a device handle
|
||||
* @attr: Pointer to the device attribute
|
||||
* @buf: Contains the input buffer for sysfs
|
||||
* @size: Size of the data stored in buf
|
||||
*
|
||||
* Callback function to read the value of a register from a sysfs node.
|
||||
* Return: The size of the data consumed or negative on error.
|
||||
*/
|
||||
ssize_t adreno_coresight_store_register(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t size);
|
||||
|
||||
#define ADRENO_CORESIGHT_ATTR(_attrname, _reg) \
|
||||
struct adreno_coresight_attr coresight_attr_##_attrname = { \
|
||||
__ATTR(_attrname, 0644, \
|
||||
adreno_coresight_show_register, \
|
||||
adreno_coresight_store_register), \
|
||||
(_reg), }
|
||||
|
||||
/**
|
||||
* struct adreno_coresight - GPU specific coresight definition
|
||||
*/
|
||||
struct adreno_coresight {
|
||||
/**
|
||||
* @registers: Array of GPU specific registers to configure trace
|
||||
* bus output
|
||||
*/
|
||||
struct adreno_coresight_register *registers;
|
||||
/** @count: Number of registers in the array */
|
||||
unsigned int count;
|
||||
/** @groups: Pointer to an attribute list of control files */
|
||||
const struct attribute_group **groups;
|
||||
/** @atid: The unique ATID value of the coresight device */
|
||||
unsigned int atid;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_QCOM_KGSL_CORESIGHT
|
||||
/**
|
||||
* adreno_coresight_init - Initialize coresight for the GPU device
|
||||
* @adreno_dev: An Adreno GPU device handle
|
||||
*
|
||||
* Initialize devices for the GPU target.
|
||||
*/
|
||||
void adreno_coresight_init(struct adreno_device *adreno_dev);
|
||||
|
||||
/**
|
||||
* adreno_coresight_start - Reprogram coresight registers after power collapse
|
||||
* @adreno_dev: An Adreno GPU device handle
|
||||
*
|
||||
* Reprogram the cached values to the coresight registers on power up.
|
||||
*/
|
||||
void adreno_coresight_start(struct adreno_device *adreno_dev);
|
||||
|
||||
/**
|
||||
* adreno_coresight_stop - Reprogram coresight registers after power collapse
|
||||
* @adreno_dev: An Adreno GPU device handle
|
||||
*
|
||||
* Cache the current coresight register values so they can be restored after
|
||||
* power collapse.
|
||||
*/
|
||||
void adreno_coresight_stop(struct adreno_device *adreno_dev);
|
||||
|
||||
/**
|
||||
* adreno_coresight_remove - Destroy active coresight devices
|
||||
* @adreno_dev: An Adreno GPU device handle
|
||||
*
|
||||
* Destroy any active coresight devices.
|
||||
*/
|
||||
void adreno_coresight_remove(struct adreno_device *adreno_dev);
|
||||
#else
|
||||
static inline void adreno_coresight_init(struct adreno_device *adreno_dev) { }
|
||||
static inline void adreno_coresight_start(struct adreno_device *adreno_dev) { }
|
||||
static inline void adreno_coresight_stop(struct adreno_device *adreno_dev) { }
|
||||
static inline void adreno_coresight_remove(struct adreno_device *adreno_dev) { }
|
||||
#endif
|
||||
#endif
|
Loading…
Reference in New Issue
Block a user