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msm: kgsl: Make all GMU code target specific

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Move all the GMU code to a6xx target specific code. This is the first in
several steps to make the GMU code more modular and flexibile for
various usecases.

Change-Id: Ic0dedbad0e70771c301705a0eb4ed422efb4c80a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This commit is contained in:
Jordan Crouse 2020-05-27 10:38:28 -06:00
parent 3c09b03d0c
commit c359b1dd27
8 changed files with 1756 additions and 37 deletions
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1
drivers/gpu/msm/Makefile
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@ -9,7 +9,6 @@ msm_kgsl-y = \
kgsl_drawobj.o \
kgsl_events.o \
kgsl_ioctl.o \
kgsl_gmu.o \
kgsl_gmu_core.o \
kgsl_hfi.o \
kgsl_mmu.o \

1
drivers/gpu/msm/adreno.h
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@ -667,7 +667,6 @@ enum adreno_regs {
ADRENO_REG_GBIF_HALT_ACK,
ADRENO_REG_GMU_AO_INTERRUPT_EN,
ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR,
ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS,
ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK,
ADRENO_REG_GMU_PWR_COL_KEEPALIVE,
ADRENO_REG_GMU_AHB_FENCE_STATUS,

2
drivers/gpu/msm/adreno_a6xx.c
View File

@ -2486,8 +2486,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
A6XX_GMU_AO_INTERRUPT_EN),
ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR,
A6XX_GMU_AO_HOST_INTERRUPT_CLR),
ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS,
A6XX_GMU_AO_HOST_INTERRUPT_STATUS),
ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK,
A6XX_GMU_AO_HOST_INTERRUPT_MASK),
ADRENO_REG_DEFINE(ADRENO_REG_GMU_PWR_COL_KEEPALIVE,

1769
drivers/gpu/msm/adreno_a6xx_gmu.c
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File diff suppressed because it is too large Load Diff

5
drivers/gpu/msm/kgsl_bus.c
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@ -127,7 +127,7 @@ u32 *kgsl_bus_get_table(struct platform_device *pdev,
if (num <= 0)
return ERR_PTR(-EINVAL);
levels = devm_kcalloc(&pdev->dev, num, sizeof(*levels), GFP_KERNEL);
levels = kcalloc(num, sizeof(*levels), GFP_KERNEL);
if (!levels)
return ERR_PTR(-ENOMEM);
@ -171,6 +171,8 @@ done:
pwr->icc_path = of_icc_get(&pdev->dev, NULL);
if (IS_ERR(pwr->icc_path) && !gmu_core_scales_bandwidth(device)) {
WARN(1, "The CPU has no way to set the GPU bus levels\n");
kfree(pwr->ddr_table);
return PTR_ERR(pwr->icc_path);
}
@ -181,5 +183,6 @@ done:
void kgsl_bus_close(struct kgsl_device *device)
{
kfree(device->pwrctrl.ddr_table);
icc_put(device->pwrctrl.icc_path);
}

11
drivers/gpu/msm/kgsl_gmu.h
View File

@ -81,7 +81,6 @@ struct gmu_block_header {
/* GMU memdesc entries */
#define GMU_KERNEL_ENTRIES 16
extern struct gmu_dev_ops adreno_a6xx_gmudev;
#define KGSL_GMU_DEVICE(_a) ((struct gmu_device *)((_a)->gmu_core.ptr))
enum gmu_mem_type {
@ -96,7 +95,7 @@ enum gmu_mem_type {
};
enum gmu_context_index {
GMU_CONTEXT_USER = 0,
GMU_CONTEXT_USER,
GMU_CONTEXT_KERNEL,
};
@ -208,12 +207,4 @@ struct gmu_device {
atomic_t cm3_fault;
};
struct gmu_memdesc *gmu_get_memdesc(struct gmu_device *gmu,
unsigned int addr, unsigned int size);
unsigned int gmu_get_memtype_base(struct gmu_device *gmu,
enum gmu_mem_type type);
int gmu_prealloc_req(struct kgsl_device *device, struct gmu_block_header *blk);
int gmu_cache_finalize(struct kgsl_device *device);
#endif /* __KGSL_GMU_H */

2
drivers/gpu/msm/kgsl_gmu_core.c
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@ -11,7 +11,7 @@
#include "kgsl_trace.h"
static const struct of_device_id gmu_match_table[] = {
{ .compatible = "qcom,gpu-gmu", .data = &kgsl_gmu_driver },
{ .compatible = "qcom,gpu-gmu", .data = &a6xx_gmu_driver },
{ .compatible = "qcom,gpu-rgmu", .data = &kgsl_rgmu_driver },
{},
};

2
drivers/gpu/msm/kgsl_gmu_core.h
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@ -161,7 +161,7 @@ struct gmu_core_device {
unsigned long flags;
};
extern struct platform_driver kgsl_gmu_driver;
extern struct platform_driver a6xx_gmu_driver;
extern struct platform_driver kgsl_rgmu_driver;
/* GMU core functions */