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bindings: clk: gpucc: Add support for LIMITER reset

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Add support for the consumer to be able to set/reset the
GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR register as an when required
on BLAIR and HOLI platforms.

Change-Id: I0d041066e36c0152fdcc8e306367aebdc5fd6283
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
This commit is contained in:
Taniya Das 2021-12-14 16:32:21 +05:30 committed by Kalpak Kawadkar
parent c162308952
commit c5ebf4ce1a
2 changed files with 6 additions and 0 deletions
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3
include/dt-bindings/clock/qcom,gpucc-blair.h
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@ -31,4 +31,7 @@
#define GPU_CC_RBCPR_CLK_SRC 21
#define GPU_CC_SLEEP_CLK 22
/* GPU_CC resets */
#define GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 0
#endif

3
include/dt-bindings/clock/qcom,gpucc-holi.h
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@ -27,4 +27,7 @@
#define CX_GDSC 0
#define GX_GDSC 1
/* GPU_CC resets */
#define GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 0
#endif